diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
| commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
| tree | dbe4c8482b37e854302410318fc474f507310724 /tests/long/se | |
| parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
| download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz | |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/long/se')
17 files changed, 11545 insertions, 11526 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index bf75cb6d5..69b672058 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.062553 # Number of seconds simulated -sim_ticks 62553193500 # Number of ticks simulated -final_tick 62553193500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062555 # Number of seconds simulated +sim_ticks 62555455500 # Number of ticks simulated +final_tick 62555455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 434587 # Simulator instruction rate (inst/s) -host_op_rate 436752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 300043763 # Simulator tick rate (ticks/s) -host_mem_usage 405580 # Number of bytes of host memory used -host_seconds 208.48 # Real time elapsed on the host +host_inst_rate 428742 # Simulator instruction rate (inst/s) +host_op_rate 430877 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 296018745 # Simulator tick rate (ticks/s) +host_mem_usage 404460 # Number of bytes of host memory used +host_seconds 211.32 # Real time elapsed on the host sim_insts 90602850 # Number of instructions simulated sim_ops 91054081 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 49472 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 49536 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947264 # Number of bytes read from this memory -system.physmem.bytes_read::total 996736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 49472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 49472 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 773 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 996800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 49536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 49536 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 774 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14801 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15574 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 790879 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15143336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15934214 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 790879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 790879 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 790879 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15143336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15934214 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15574 # Number of read requests accepted +system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 791873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15142788 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15934661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 791873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 791873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 791873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15142788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15934661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 15574 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 996736 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 996800 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 996736 # Total read bytes from the system interface side +system.physmem.bytesReadSys 996800 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,7 +48,7 @@ system.physmem.perBankRdBursts::2 949 # Pe system.physmem.perBankRdBursts::3 1027 # Per bank write bursts system.physmem.perBankRdBursts::4 1050 # Per bank write bursts system.physmem.perBankRdBursts::5 1113 # Per bank write bursts -system.physmem.perBankRdBursts::6 1087 # Per bank write bursts +system.physmem.perBankRdBursts::6 1088 # Per bank write bursts system.physmem.perBankRdBursts::7 1088 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 62553092500 # Total gap between requests +system.physmem.totGap 62555354500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15574 # Read request sizes (log2) +system.physmem.readPktSize::6 15575 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15455 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 1540 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 646.524675 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 437.476336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 402.605762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 437.465548 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 402.658643 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 259 16.82% 16.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 178 11.56% 28.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 79 5.13% 33.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 177 11.49% 28.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 80 5.19% 33.51% # Bytes accessed per row activation system.physmem.bytesPerActivate::384-511 62 4.03% 37.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 82 5.32% 42.86% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 81 5.26% 48.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 41 2.66% 50.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 66 4.29% 55.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 40 2.60% 50.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 67 4.35% 55.06% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 692 44.94% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 1540 # Bytes accessed per row activation -system.physmem.totQLat 211075250 # Total ticks spent queuing -system.physmem.totMemAccLat 503087750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13553.05 # Average queueing delay per DRAM burst +system.physmem.totQLat 211097500 # Total ticks spent queuing +system.physmem.totMemAccLat 503128750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13553.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32303.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 32303.61 # Average memory access latency per DRAM burst system.physmem.avgRdBW 15.93 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 15.93 # Average system read bandwidth in MiByte/s @@ -217,66 +217,66 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14027 # Number of row buffer hits during reads +system.physmem.readRowHits 14028 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 90.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4016507.80 # Average gap between requests +system.physmem.avgGap 4016395.15 # Average gap between requests system.physmem.pageHitRate 90.07 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 6047580 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 3202980 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 58533720 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 58540860 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 210821520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 136590810 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 8775360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 736795110 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 212078880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 14428861800 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 15801707760 # Total energy per rank (pJ) -system.physmem_0.averagePower 252.612326 # Core power per rank (mW) -system.physmem_0.totalIdleTime 62230723750 # Total Idle time Per DRAM Rank +system.physmem_0.actBackEnergy 136590240 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 8764320 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 737385060 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 211641120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14429375100 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 15802368780 # Total energy per rank (pJ) +system.physmem_0.averagePower 252.613756 # Core power per rank (mW) +system.physmem_0.totalIdleTime 62232966250 # Total Idle time Per DRAM Rank system.physmem_0.memoryStateTime::IDLE 9906000 # Time in different power states system.physmem_0.memoryStateTime::REF 89372000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 60062733500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 552254250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 223131000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1615796750 # Time in different power states +system.physmem_0.memoryStateTime::SREF 60064867500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 551102250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 223150500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1617057250 # Time in different power states system.physmem_1.actEnergy 4998000 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 2641320 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 52664640 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 256919520.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 136418100 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 13273920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 827375520 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 248165280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14377479765 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 15920005755 # Total energy per rank (pJ) -system.physmem_1.averagePower 254.503484 # Core power per rank (mW) -system.physmem_1.totalIdleTime 62218080000 # Total Idle time Per DRAM Rank +system.physmem_1.actBackEnergy 136410120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13262400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 827323080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 248273280 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14377994265 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 15920556885 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.503090 # Core power per rank (mW) +system.physmem_1.totalIdleTime 62220218000 # Total Idle time Per DRAM Rank system.physmem_1.memoryStateTime::IDLE 20713000 # Time in different power states system.physmem_1.memoryStateTime::REF 109118000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 59758619500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 646225750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 203975250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1814542000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 20808248 # Number of BP lookups -system.cpu.branchPred.condPredicted 17115636 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 756798 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8965663 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8840828 # Number of BTB hits +system.physmem_1.memoryStateTime::SREF 59760759500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 646525750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 203991750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1814347500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 20806620 # Number of BP lookups +system.cpu.branchPred.condPredicted 17114048 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 756880 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8968258 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8843232 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.607632 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 61995 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.605905 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 61975 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu.branchPred.indirectLookups 26211 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 24795 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1416 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 665 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectHits 24793 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1418 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 666 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 125106387 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 125110911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602850 # Number of instructions committed system.cpu.committedOps 91054081 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2182224 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2181045 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.380822 # CPI: cycles per instruction -system.cpu.ipc 0.724206 # IPC: instructions per cycle +system.cpu.cpi 1.380872 # CPI: cycles per instruction +system.cpu.ipc 0.724180 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 63822829 70.09% 70.09% # Class of committed instruction system.cpu.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction @@ -446,60 +446,60 @@ system.cpu.op_class_0::FloatMemWrite 22 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 91054081 # Class of committed instruction -system.cpu.tickCycles 110521789 # Number of cycles that the object actually ticked -system.cpu.idleCycles 14584598 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 946101 # number of replacements -system.cpu.dcache.tags.tagsinuse 3621.109986 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26274729 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 950197 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.651875 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20754063500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3621.109986 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.884060 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.884060 # Average percentage of cache occupancy +system.cpu.tickCycles 110528679 # Number of cycles that the object actually ticked +system.cpu.idleCycles 14582232 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 946104 # number of replacements +system.cpu.dcache.tags.tagsinuse 3621.120784 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26274613 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 950200 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 27.651666 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20754332500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3621.120784 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.884063 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.884063 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 232 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2202 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1662 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2198 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1666 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55461283 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55461283 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21605780 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21605780 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4660667 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4660667 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55461064 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55461064 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21605665 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21605665 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660666 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660666 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 508 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 508 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26266447 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26266447 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26266955 # number of overall hits -system.cpu.dcache.overall_hits::total 26266955 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 906496 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 906496 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 74314 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 74314 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 26266331 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26266331 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26266839 # number of overall hits +system.cpu.dcache.overall_hits::total 26266839 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906500 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906500 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74315 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 4 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 4 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 980810 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 980810 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 980814 # number of overall misses -system.cpu.dcache.overall_misses::total 980814 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832179000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11832179000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760205500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2760205500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14592384500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14592384500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14592384500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14592384500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22512276 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22512276 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 980815 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 980815 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 980819 # number of overall misses +system.cpu.dcache.overall_misses::total 980819 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11832236000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11832236000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2760278000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2760278000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14592514000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14592514000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14592514000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14592514000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22512165 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22512165 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 512 # number of SoftPFReq accesses(hits+misses) @@ -508,10 +508,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27247257 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27247257 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27247769 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27247769 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 27247146 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27247146 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27247658 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27247658 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040267 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.040267 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015695 # miss rate for WriteReq accesses @@ -522,50 +522,50 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.035997 system.cpu.dcache.demand_miss_rate::total 0.035997 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.035996 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.035996 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.654397 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.654397 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.469790 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.469790 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.891233 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14877.891233 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.830557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14877.830557 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13052.659680 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13052.659680 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37142.945570 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37142.945570 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14877.947421 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14877.947421 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14877.886746 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14877.886746 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 943282 # number of writebacks -system.cpu.dcache.writebacks::total 943282 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3066 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3066 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27550 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27550 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 30616 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 30616 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 30616 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 30616 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903430 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 903430 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 943285 # number of writebacks +system.cpu.dcache.writebacks::total 943285 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3067 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3067 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27551 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27551 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 30618 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 30618 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 30618 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 30618 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903433 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 903433 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46764 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 46764 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 3 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 950194 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 950194 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 950197 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 950197 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889871500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596189500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 950197 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 950197 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 950200 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 950200 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10889912000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10889912000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1596274500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1596274500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 170000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 170000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486061000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12486061000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486231000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12486231000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12486186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12486186500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12486356500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12486356500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040131 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009876 # mshr miss rate for WriteReq accesses @@ -574,73 +574,73 @@ system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005859 system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005859 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.034873 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.034872 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.918400 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.918400 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34132.869301 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34132.869301 # average WriteReq mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034873 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.034873 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12053.923202 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12053.923202 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34134.686939 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34134.686939 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 56666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 56666.666667 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.538669 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.538669 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.676091 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.676091 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13140.629259 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13140.629259 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13140.766681 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13140.766681 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 689.568187 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27835083 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 801 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34750.415730 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 689.583421 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27839479 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 34712.567332 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 689.568187 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.336703 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.336703 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 796 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 689.583421 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.336711 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.336711 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 740 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.388672 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55672569 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55672569 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 27835083 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27835083 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27835083 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27835083 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27835083 # number of overall hits -system.cpu.icache.overall_hits::total 27835083 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 801 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 801 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 801 # 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average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 89053.615960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 89053.615960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,132 +649,132 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::writebacks 5 # number of writebacks system.cpu.icache.writebacks::total 5 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 801 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 801 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 801 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 801 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.345093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15574 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 674.588306 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 10633.516821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020587 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.324509 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.345096 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15575 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 63 # 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number of WritebackClean accesses(hits+misses) system.cpu.l2cache.WritebackClean_accesses::total 4 # number of WritebackClean accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 46764 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 46764 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 801 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 801 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 903433 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 903433 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 950197 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 950998 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 801 # 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number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 951002 # number of overall (read+write) accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.311008 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.311008 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966292 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966292 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.966334 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.966334 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000291 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000291 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966292 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.966334 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015583 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016384 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966292 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016385 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.966334 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015583 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016384 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81287.610011 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81287.610011 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89277.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89277.777778 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187212.927757 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187212.927757 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83472.498556 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89277.777778 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83169.041669 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83472.498556 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016385 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81293.557481 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81293.557481 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89172.903226 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89172.903226 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 187220.532319 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 187220.532319 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 83473.334617 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89172.903226 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83175.018572 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 83473.334617 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -793,122 +793,122 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 6 system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14544 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14544 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 773 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 773 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 774 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 774 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 257 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 257 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 773 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 14801 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 15574 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 773 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15575 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14801 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 15574 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036807000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036807000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61297500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61297500 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46234000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46234000 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61297500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083041000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1144338500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61297500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083041000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1144338500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1036893500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1036893500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 61295500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 61295500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 46236000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 46236000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 61295500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1083129500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1144425000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 61295500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1083129500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1144425000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311008 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.311008 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965044 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.965087 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000284 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000284 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016376 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965044 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965087 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015577 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016376 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71287.610011 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71287.610011 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79298.188875 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79298.188875 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179898.832685 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179898.832685 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79298.188875 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73173.501790 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73477.494542 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1897104 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 946122 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71293.557481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71293.557481 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 79193.152455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 79193.152455 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 179906.614786 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 179906.614786 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 79193.152455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73179.481116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73478.330658 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1897111 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 946125 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 150 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 904234 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 943282 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 943285 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 2819 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 46764 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 46764 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 801 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 903433 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1607 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2848102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121182656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 121234240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 802 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 903436 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1609 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2846504 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2848113 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 51648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 121183040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 950998 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 951002 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000175 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.013211 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 950832 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 950836 99.98% 99.98% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 166 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 950998 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1891839000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 951002 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1891845500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1201999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1203499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1425298494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1425302994 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 15574 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 15575 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 62553193500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1030 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 62555455500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1031 # Transaction distribution system.membus.trans_dist::ReadExReq 14544 # Transaction distribution system.membus.trans_dist::ReadExResp 14544 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1030 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31148 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 996736 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 1031 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31150 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31150 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 996800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 996800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 15574 # Request fanout histogram +system.membus.snoop_fanout::samples 15575 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15574 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 15575 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15574 # Request fanout histogram -system.membus.reqLayer0.occupancy 21778500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 15575 # Request fanout histogram +system.membus.reqLayer0.occupancy 21782500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 82137500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 82144500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 2da35dc4f..e99ff0d50 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058681 # Number of seconds simulated -sim_ticks 58681066500 # Number of ticks simulated -final_tick 58681066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058521 # Number of seconds simulated +sim_ticks 58521086000 # Number of ticks simulated +final_tick 58521086000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 243006 # Simulator instruction rate (inst/s) -host_op_rate 244216 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 157411271 # Simulator tick rate (ticks/s) -host_mem_usage 492224 # Number of bytes of host memory used -host_seconds 372.79 # Real time elapsed on the host +host_inst_rate 243648 # Simulator instruction rate (inst/s) +host_op_rate 244862 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 157397000 # Simulator tick rate (ticks/s) +host_mem_usage 492140 # Number of bytes of host memory used +host_seconds 371.81 # Real time elapsed on the host sim_insts 90589799 # Number of instructions simulated sim_ops 91041030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 44800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 219520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 922368 # Number of bytes read from this memory -system.physmem.bytes_read::total 1186688 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6784 # Number of bytes written to this memory -system.physmem.bytes_written::total 6784 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 700 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3430 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14412 # Number of read requests responded to by this memory -system.physmem.num_reads::total 18542 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 106 # Number of write requests responded to by this memory -system.physmem.num_writes::total 106 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 763449 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3740900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 15718324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 20222673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 763449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 763449 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 115608 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 115608 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 115608 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 763449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3740900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 15718324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 20338281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 18543 # Number of read requests accepted -system.physmem.writeReqs 106 # Number of write requests accepted -system.physmem.readBursts 18543 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 106 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1180544 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 4608 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1186752 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 220224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 # Number of bytes read from this memory +system.physmem.bytes_read::total 1186880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4736 # Number of bytes written to this memory +system.physmem.bytes_written::total 4736 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3441 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14405 # Number of read requests responded to by this memory +system.physmem.num_reads::total 18545 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 74 # Number of write requests responded to by this memory +system.physmem.num_writes::total 74 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 764442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3763156 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 20281237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 764442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 764442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80928 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 764442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3763156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 20362165 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 18546 # Number of read requests accepted +system.physmem.writeReqs 74 # Number of write requests accepted +system.physmem.readBursts 18546 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 74 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1183360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue +system.physmem.bytesWritten 3328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1186944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 3245 # Per bank write bursts -system.physmem.perBankRdBursts::1 921 # Per bank write bursts -system.physmem.perBankRdBursts::2 954 # Per bank write bursts +system.physmem.perBankRdBursts::0 3297 # Per bank write bursts +system.physmem.perBankRdBursts::1 920 # Per bank write bursts +system.physmem.perBankRdBursts::2 949 # Per bank write bursts system.physmem.perBankRdBursts::3 1031 # Per bank write bursts -system.physmem.perBankRdBursts::4 1065 # Per bank write bursts -system.physmem.perBankRdBursts::5 1115 # Per bank write bursts +system.physmem.perBankRdBursts::4 1067 # Per bank write bursts +system.physmem.perBankRdBursts::5 1119 # Per bank write bursts system.physmem.perBankRdBursts::6 1093 # Per bank write bursts -system.physmem.perBankRdBursts::7 1100 # Per bank write bursts +system.physmem.perBankRdBursts::7 1097 # Per bank write bursts system.physmem.perBankRdBursts::8 1024 # Per bank write bursts -system.physmem.perBankRdBursts::9 962 # Per bank write bursts -system.physmem.perBankRdBursts::10 933 # Per bank write bursts +system.physmem.perBankRdBursts::9 961 # Per bank write bursts +system.physmem.perBankRdBursts::10 934 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 904 # Per bank write bursts +system.physmem.perBankRdBursts::12 902 # Per bank write bursts system.physmem.perBankRdBursts::13 895 # Per bank write bursts -system.physmem.perBankRdBursts::14 1401 # Per bank write bursts -system.physmem.perBankRdBursts::15 904 # Per bank write bursts -system.physmem.perBankWrBursts::0 2 # Per bank write bursts +system.physmem.perBankRdBursts::14 1399 # Per bank write bursts +system.physmem.perBankRdBursts::15 903 # Per bank write bursts +system.physmem.perBankWrBursts::0 1 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts +system.physmem.perBankWrBursts::2 2 # Per bank write bursts system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 12 # Per bank write bursts -system.physmem.perBankWrBursts::5 8 # Per bank write bursts -system.physmem.perBankWrBursts::6 10 # Per bank write bursts -system.physmem.perBankWrBursts::7 7 # Per bank write bursts +system.physmem.perBankWrBursts::4 1 # Per bank write bursts +system.physmem.perBankWrBursts::5 14 # Per bank write bursts +system.physmem.perBankWrBursts::6 9 # Per bank write bursts +system.physmem.perBankWrBursts::7 3 # Per bank write bursts system.physmem.perBankWrBursts::8 1 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 1 # Per bank write bursts +system.physmem.perBankWrBursts::10 2 # Per bank write bursts system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 5 # Per bank write bursts +system.physmem.perBankWrBursts::12 1 # Per bank write bursts system.physmem.perBankWrBursts::13 12 # Per bank write bursts -system.physmem.perBankWrBursts::14 8 # Per bank write bursts -system.physmem.perBankWrBursts::15 6 # Per bank write bursts +system.physmem.perBankWrBursts::14 5 # Per bank write bursts +system.physmem.perBankWrBursts::15 1 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58681058000 # Total gap between requests +system.physmem.totGap 58521077500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 18543 # Read request sizes (log2) +system.physmem.readPktSize::6 18546 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 106 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12536 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 316 # What read queue length does an incoming req see +system.physmem.writePktSize::6 74 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 12593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 500 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 319 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 299 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 103 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -149,24 +149,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -198,109 +198,111 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 398.104980 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 217.970166 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 405.874685 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 839 28.23% 28.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 987 33.21% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89 2.99% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 64 2.15% 66.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 64 2.15% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 65 2.19% 70.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 54 1.82% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 55 1.85% 74.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 755 25.40% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2972 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 4544.500000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 1447.547305 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7502.381200 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 2 50.00% 50.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-2047 1 25.00% 75.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::15360-15871 1 25.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 4 100.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4 # Writes before turning the bus around for reads -system.physmem.totQLat 829373528 # Total ticks spent queuing -system.physmem.totMemAccLat 1175236028 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 92230000 # Total ticks spent in databus transfers -system.physmem.avgQLat 44962.24 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 3004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.652463 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 214.589229 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 405.543781 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 3004 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 6161.333333 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 2123.401593 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 8586.829993 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.333333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.306995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.154701 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2 66.67% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3 # Writes before turning the bus around for reads +system.physmem.totQLat 837911216 # Total ticks spent queuing +system.physmem.totMemAccLat 1184598716 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 92450000 # Total ticks spent in databus transfers +system.physmem.avgQLat 45316.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 63712.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 20.12 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.08 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 20.22 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 64066.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 20.22 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 20.28 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.08 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.16 # Data bus utilization in percentage system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.34 # Average write queue length when enqueuing -system.physmem.readRowHits 15527 # Number of row buffer hits during reads -system.physmem.writeRowHits 11 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.18 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 11.00 # Row buffer hit rate for writes -system.physmem.avgGap 3146606.15 # Average gap between requests -system.physmem.pageHitRate 83.78 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15943620 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8459055 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 75134220 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 203580 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1849451760.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 458311920 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 99516480 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 3997068570 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3182851200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 10077393330 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 19767987555 # Total energy per rank (pJ) -system.physmem_0.averagePower 336.871642 # Core power per rank (mW) -system.physmem_0.totalIdleTime 57408712347 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 196273000 # Time in different power states -system.physmem_0.memoryStateTime::REF 786774000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 40354533250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 8288648060 # Time in different power states -system.physmem_0.memoryStateTime::ACT 289307153 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 8765531037 # Time in different power states -system.physmem_1.actEnergy 5333580 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2819685 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 56563080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 172260 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 259378080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 131548590 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 14205120 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 785395590 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 262919520 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 13470232590 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 14988765045 # Total energy per rank (pJ) -system.physmem_1.averagePower 255.427603 # Core power per rank (mW) -system.physmem_1.totalIdleTime 58353780091 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 23548250 # Time in different power states -system.physmem_1.memoryStateTime::REF 110212000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 55948105250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 684663397 # Time in different power states -system.physmem_1.memoryStateTime::ACT 192205159 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1722332444 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 28234239 # Number of BP lookups -system.cpu.branchPred.condPredicted 23266690 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 835421 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11829840 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11748052 # Number of BTB hits +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 13.38 # Average write queue length when enqueuing +system.physmem.readRowHits 15512 # Number of row buffer hits during reads +system.physmem.writeRowHits 18 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 25.71 # Row buffer hit rate for writes +system.physmem.avgGap 3142915.01 # Average gap between requests +system.physmem.pageHitRate 83.67 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16243500 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8614650 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 75484080 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 156600 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1895549760.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 464945010 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 99199680 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 4173482430 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3272736480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9883191315 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 19894073865 # Total energy per rank (pJ) +system.physmem_0.averagePower 339.947098 # Core power per rank (mW) +system.physmem_0.totalIdleTime 57233116090 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 194944250 # Time in different power states +system.physmem_0.memoryStateTime::REF 806364000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 39558059500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 8522710566 # Time in different power states +system.physmem_0.memoryStateTime::ACT 286661660 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 9152346024 # Time in different power states +system.physmem_1.actEnergy 5255040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2785530 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 56527380 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 114840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 247699920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 125328180 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 13397280 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 772336890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 242624160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 13451278005 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 14917407225 # Total energy per rank (pJ) +system.physmem_1.averagePower 254.906533 # Core power per rank (mW) +system.physmem_1.totalIdleTime 58211272096 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 21634250 # Time in different power states +system.physmem_1.memoryStateTime::REF 105218000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 55885668250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 631842954 # Time in different power states +system.physmem_1.memoryStateTime::ACT 182961654 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1693760892 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 28121660 # Number of BP lookups +system.cpu.branchPred.condPredicted 23134709 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 844714 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11731332 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11630363 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.308630 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 74543 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 96 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 27224 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 25476 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1748 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 245 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 99.139322 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 80725 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 95 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 28301 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 25845 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 2456 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 243 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -330,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -360,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -390,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -421,240 +423,240 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 117362134 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 117042173 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 746504 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 134908625 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28234239 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11848071 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 115710996 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1674249 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 948 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32275841 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 117296446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.155292 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.317650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 755365 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134380549 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28121660 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11736933 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 115370240 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1692793 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1033 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32086744 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116973882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.154260 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.318237 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 59759710 50.95% 50.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13934020 11.88% 62.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9230571 7.87% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34372145 29.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 117296446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.240574 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.149507 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8834504 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 65062525 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33013030 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9560979 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 825408 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4097904 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 11817 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114396314 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1984657 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 825408 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15270391 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 50319403 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 113009 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35408802 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15359433 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110873352 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1412133 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11133960 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1550028 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2088318 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 507009 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129946854 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483157007 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119448195 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 430 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116973882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.240269 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.148138 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8865418 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 65026599 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 32710680 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9589004 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 782181 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9831266 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 64876 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 113761457 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2108425 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 782181 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15316274 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 50229704 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 114341 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35119945 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15411437 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110456918 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1289549 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11149602 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1576334 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2138216 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 510190 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129202611 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 481340709 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 118978784 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 633 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22633935 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 4409 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 4401 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21513701 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26805540 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5347415 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 519015 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 253842 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109668195 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8283 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101366364 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1074602 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18635448 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41675725 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 65 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 117296446 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.864190 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.988217 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 21889692 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 4408 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 4400 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 21529051 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26813393 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5308956 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 540635 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 272789 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109383305 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8282 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101253910 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 993650 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18350557 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 40868291 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116973882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.865611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.989909 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 55661536 47.45% 47.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 31364227 26.74% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22008293 18.76% 92.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7064324 6.02% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1197751 1.02% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 315 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 117296446 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116973882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9780929 48.66% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9614642 47.84% 96.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 702971 3.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71970702 71.00% 71.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10697 0.01% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 57 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 124 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24337480 24.01% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5047270 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101366364 # Type of FU issued -system.cpu.iq.rate 0.863706 # Inst issue rate -system.cpu.iq.fu_busy_cnt 20098632 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.198277 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 341201935 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128312613 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99607782 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 473 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 622 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121464746 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 250 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 288157 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 101253910 # Type of FU issued +system.cpu.iq.rate 0.865106 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20139291 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198899 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340613998 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127742533 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 645 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 896 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 147 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121392865 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 289487 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4329629 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1502 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1344 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 602571 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4337482 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1323 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 564112 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7583 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130792 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7586 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 131115 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 825408 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8297291 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 773487 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109689301 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 782181 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8303656 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 706645 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109404410 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26805540 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5347415 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4395 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 182523 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 427569 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1344 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 435014 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412394 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 847408 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100110032 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23803163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1256332 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26813393 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5308956 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4394 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 183005 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 362995 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1323 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 354101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 451870 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 805971 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100068536 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23799476 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1185374 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 12823 # number of nop insts executed -system.cpu.iew.exec_refs 28718949 # number of memory reference insts executed -system.cpu.iew.exec_branches 20621210 # Number of branches executed -system.cpu.iew.exec_stores 4915786 # Number of stores executed -system.cpu.iew.exec_rate 0.853001 # Inst execution rate -system.cpu.iew.wb_sent 99693474 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99607900 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59692176 # num instructions producing a value -system.cpu.iew.wb_consumers 95528763 # num instructions consuming a value -system.cpu.iew.wb_rate 0.848723 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624861 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 17363908 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 28747002 # number of memory reference insts executed +system.cpu.iew.exec_branches 20644390 # Number of branches executed +system.cpu.iew.exec_stores 4947526 # Number of stores executed +system.cpu.iew.exec_rate 0.854978 # Inst execution rate +system.cpu.iew.wb_sent 99653444 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99568306 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59603520 # num instructions producing a value +system.cpu.iew.wb_consumers 95472454 # num instructions consuming a value +system.cpu.iew.wb_rate 0.850705 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624301 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 17204380 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 823705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 114608461 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.794476 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.731976 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 780499 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 114317449 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.796498 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.736161 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 78183874 68.22% 68.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18612814 16.24% 84.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7153278 6.24% 90.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3469165 3.03% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1644308 1.43% 95.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 541542 0.47% 95.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 703493 0.61% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179022 0.16% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4120965 3.60% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 114608461 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 114317449 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602408 # Number of instructions committed system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,80 +706,80 @@ system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction -system.cpu.commit.bw_lim_events 4120965 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 218899309 # The number of ROB reads -system.cpu.rob.rob_writes 219523661 # The number of ROB writes -system.cpu.timesIdled 582 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 65688 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 4142947 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 218426787 # The number of ROB reads +system.cpu.rob.rob_writes 219173124 # The number of ROB writes +system.cpu.timesIdled 593 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 68291 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589799 # Number of Instructions Simulated system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.295534 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.295534 # CPI: Total CPI of All Threads -system.cpu.ipc 0.771883 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.771883 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108098001 # number of integer regfile reads -system.cpu.int_regfile_writes 58691976 # number of integer regfile writes +system.cpu.cpi 1.292002 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.292002 # CPI: Total CPI of All Threads +system.cpu.ipc 0.773993 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.773993 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108095256 # number of integer regfile reads +system.cpu.int_regfile_writes 58597145 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 98 # number of floating regfile writes -system.cpu.cc_regfile_reads 369004563 # number of cc regfile reads -system.cpu.cc_regfile_writes 58686890 # number of cc regfile writes -system.cpu.misc_regfile_reads 28409682 # number of misc regfile reads +system.cpu.fp_regfile_writes 127 # number of floating regfile writes +system.cpu.cc_regfile_reads 368871207 # number of cc regfile reads +system.cpu.cc_regfile_writes 58517884 # number of cc regfile writes +system.cpu.misc_regfile_reads 28439348 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 5470632 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.769242 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18249828 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 511.768178 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18243100 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.335651 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 38122500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.769242 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999549 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999549 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 3.334421 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 38187500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999547 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61906996 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61906996 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 13887361 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13887361 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4354163 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4354163 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61896540 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61896540 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 13880582 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13880582 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4354214 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4354214 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18241524 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18241524 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18242046 # number of overall hits -system.cpu.dcache.overall_hits::total 18242046 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9587281 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9587281 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 380818 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 380818 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 18234796 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18234796 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18235318 # number of overall hits +system.cpu.dcache.overall_hits::total 18235318 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9588832 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9588832 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 380767 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 380767 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9968099 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9968099 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9968106 # number of overall misses -system.cpu.dcache.overall_misses::total 9968106 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 89375617500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 89375617500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4089956224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4089956224 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9969599 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9969599 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9969606 # number of overall misses +system.cpu.dcache.overall_misses::total 9969606 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 89393317500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4103772083 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 93465573724 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 93465573724 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 93465573724 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 93465573724 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23474642 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23474642 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 93497089583 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 93497089583 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23469414 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) @@ -786,475 +788,475 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28209623 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28209623 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28210152 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28210152 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408410 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080427 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.080427 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28204395 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28204395 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28204924 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28204924 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.408567 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080416 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353358 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353358 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353352 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353352 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.311248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.311248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10739.923596 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10739.923596 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.353477 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.353470 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9376.469247 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9376.469247 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9376.462662 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9376.462662 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331655 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 128757 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 121530 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12840 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.728997 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 10.027804 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 331670 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 131340 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 121646 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 # average number of cycles each access was blocked system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks system.cpu.dcache.writebacks::total 5470632 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4338725 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4338725 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158229 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 158229 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4340269 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 158185 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4496954 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4496954 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4496954 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4496954 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248556 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5248556 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222589 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222589 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4498454 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4498454 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5248563 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 222582 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 5471145 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 5471145 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 5471149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43819499500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 43819499500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2297613115 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2297613115 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 43818706500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2301862483 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2301862483 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 235500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 235500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46117112615 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 46117112615 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46117348115 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 46117348115 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223584 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223584 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047009 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047009 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 46120568983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 46120568983 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 46120804483 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047008 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047008 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193946 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.193946 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.193943 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.867670 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.867670 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10322.222190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10322.222190 # average WriteReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193982 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193979 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193979 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8348.705446 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.151963 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.151963 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.188844 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.188844 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 448 # number of replacements -system.cpu.icache.tags.tagsinuse 427.601453 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32274679 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35623.266004 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8429.783708 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 449 # number of replacements +system.cpu.icache.tags.tagsinuse 426.857560 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32085580 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 907 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35375.501654 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 427.601453 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835159 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.833706 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.833706 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 335 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.894531 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64552564 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64552564 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 32274679 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32274679 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32274679 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32274679 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32274679 # number of overall hits -system.cpu.icache.overall_hits::total 32274679 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1150 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1150 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1150 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1150 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1150 # number of overall misses -system.cpu.icache.overall_misses::total 1150 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 79102980 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 79102980 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 79102980 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 79102980 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 79102980 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 79102980 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32275829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32275829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32275829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32275829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32275829 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32275829 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 64174375 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64174375 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 32085580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32085580 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32085580 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32085580 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32085580 # number of overall hits +system.cpu.icache.overall_hits::total 32085580 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses +system.cpu.icache.overall_misses::total 1154 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 81624480 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 81624480 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 81624480 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 81624480 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 81624480 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 81624480 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32086734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32086734 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32086734 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32086734 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32086734 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32086734 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68785.200000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68785.200000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68785.200000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68785.200000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68785.200000 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 21255 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 760 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 230 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 92.413043 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 126.666667 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 448 # number of writebacks -system.cpu.icache.writebacks::total 448 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 243 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 243 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 243 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 243 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 243 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 243 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 907 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 907 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 907 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 907 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 907 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 907 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60408984 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 60408984 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60408984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 60408984 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60408984 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 60408984 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70731.785095 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70731.785095 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70731.785095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70731.785095 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 21770 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 1853 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 229 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 95.065502 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 449 # number of writebacks +system.cpu.icache.writebacks::total 449 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 246 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 246 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 246 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61609984 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 61609984 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66603.069460 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66603.069460 # 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average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5295978 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 268023 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3398 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9680 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 832 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.003906 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884705 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 180526200 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 180526200 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.004089 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.884399 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180525307 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180525307 # 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number of WritebackClean accesses(hits+misses) -system.cpu.l2cache.WritebackClean_accesses::total 11011 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 499 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 499 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 701 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 3123 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 3123 # number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 701 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3622 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4323 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 701 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3622 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.772026 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000662 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.000790 # miss rate for overall accesses -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21300 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21300 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 127617.764471 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 127617.764471 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82794.159544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82794.159544 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 198613.694676 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 198613.694676 # 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number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.unused_prefetches 3 # number of HardPF blocks evicted w/o reference -system.cpu.l2cache.writebacks::writebacks 106 # number of writebacks -system.cpu.l2cache.writebacks::total 106 # number of writebacks +system.cpu.l2cache.unused_prefetches 1 # number of HardPF blocks evicted w/o reference +system.cpu.l2cache.writebacks::writebacks 74 # number of writebacks +system.cpu.l2cache.writebacks::total 74 # number of writebacks system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001517 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001517 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.772878 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000589 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000589 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000755 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.772878 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000627 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.058618 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3434.482939 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15300 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 132970.845481 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 132970.845481 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76825.249643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76825.249643 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 191433.937824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 191433.937824 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167137.342691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76825.249643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185589.332556 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3434.482939 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5543.287704 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 10943136 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471098 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2874 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 302216 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 302215 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5245880 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 5457301 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 13885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 42 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 318509 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5245799 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 25 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 318221 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 226170 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 226170 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 907 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244974 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadExReq 226252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 226252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16415197 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16415200 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700360704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 318663 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 7168 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5790713 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.052689 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.223412 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 700360832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 318326 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 5120 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5790377 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.052651 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 5485610 94.73% 94.73% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 305102 5.27% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5790713 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10942648026 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.6 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::total 5790377 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1361495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1362995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 18697 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 3032 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 18651 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 3037 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 58681066500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 18200 # Transaction distribution -system.membus.trans_dist::WritebackDirty 106 # Transaction distribution -system.membus.trans_dist::CleanEvict 42 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 18205 # Transaction distribution +system.membus.trans_dist::WritebackDirty 74 # Transaction distribution +system.membus.trans_dist::CleanEvict 25 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 342 # Transaction distribution -system.membus.trans_dist::ReadExResp 342 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 18201 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 37239 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1193472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1193472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 340 # Transaction distribution +system.membus.trans_dist::ReadExResp 340 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 18206 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 37196 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1191616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1191616 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 18549 # Request fanout histogram +system.membus.snoop_fanout::samples 18552 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 18549 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 18552 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 18549 # Request fanout histogram -system.membus.reqLayer0.occupancy 29669004 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 18552 # Request fanout histogram +system.membus.reqLayer0.occupancy 29380556 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 97336094 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 97369032 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 716a9adc9..8690264ef 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.065833 # Number of seconds simulated -sim_ticks 65832730500 # Number of ticks simulated -final_tick 65832730500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.065721 # Number of seconds simulated +sim_ticks 65721494500 # Number of ticks simulated +final_tick 65721494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 190384 # Simulator instruction rate (inst/s) -host_op_rate 335236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79331786 # Simulator tick rate (ticks/s) -host_mem_usage 416808 # Number of bytes of host memory used -host_seconds 829.84 # Real time elapsed on the host +host_inst_rate 191999 # Simulator instruction rate (inst/s) +host_op_rate 338080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 79869594 # Simulator tick rate (ticks/s) +host_mem_usage 415448 # Number of bytes of host memory used +host_seconds 822.86 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 69952 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory -system.physmem.bytes_read::total 1962496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 69952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 69952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory -system.physmem.bytes_written::total 19776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1093 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 19136 # Number of bytes written to this memory +system.physmem.bytes_written::total 19136 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30664 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory -system.physmem.num_writes::total 309 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1062572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 28747767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 29810339 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1062572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1062572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 300398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 300398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 300398 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1062572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 28747767 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 30110736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30664 # Number of read requests accepted -system.physmem.writeReqs 309 # Number of write requests accepted -system.physmem.readBursts 30664 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1954304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8192 # Total number of bytes read from write queue -system.physmem.bytesWritten 18368 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1962496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 128 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 299 # Number of write requests responded to by this memory +system.physmem.num_writes::total 299 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1046842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 28796424 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 29843265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1046842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1046842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 291168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 291168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 291168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1046842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 28796424 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 30134433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30646 # Number of read requests accepted +system.physmem.writeReqs 299 # Number of write requests accepted +system.physmem.readBursts 30646 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 299 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1952832 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue +system.physmem.bytesWritten 17216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1961344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 19136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1947 # Per bank write bursts -system.physmem.perBankRdBursts::1 2076 # Per bank write bursts -system.physmem.perBankRdBursts::2 2053 # Per bank write bursts -system.physmem.perBankRdBursts::3 1954 # Per bank write bursts -system.physmem.perBankRdBursts::4 2067 # Per bank write bursts +system.physmem.perBankRdBursts::0 1937 # Per bank write bursts +system.physmem.perBankRdBursts::1 2081 # Per bank write bursts +system.physmem.perBankRdBursts::2 2039 # Per bank write bursts +system.physmem.perBankRdBursts::3 1941 # Per bank write bursts +system.physmem.perBankRdBursts::4 2068 # Per bank write bursts system.physmem.perBankRdBursts::5 1911 # Per bank write bursts -system.physmem.perBankRdBursts::6 1975 # Per bank write bursts -system.physmem.perBankRdBursts::7 1868 # Per bank write bursts -system.physmem.perBankRdBursts::8 1952 # Per bank write bursts -system.physmem.perBankRdBursts::9 1938 # Per bank write bursts +system.physmem.perBankRdBursts::6 1977 # Per bank write bursts +system.physmem.perBankRdBursts::7 1878 # Per bank write bursts +system.physmem.perBankRdBursts::8 1945 # Per bank write bursts +system.physmem.perBankRdBursts::9 1939 # Per bank write bursts system.physmem.perBankRdBursts::10 1805 # Per bank write bursts system.physmem.perBankRdBursts::11 1794 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts -system.physmem.perBankRdBursts::13 1799 # Per bank write bursts -system.physmem.perBankRdBursts::14 1826 # Per bank write bursts +system.physmem.perBankRdBursts::13 1800 # Per bank write bursts +system.physmem.perBankRdBursts::14 1827 # Per bank write bursts system.physmem.perBankRdBursts::15 1779 # Per bank write bursts -system.physmem.perBankWrBursts::0 25 # Per bank write bursts -system.physmem.perBankWrBursts::1 120 # Per bank write bursts -system.physmem.perBankWrBursts::2 28 # Per bank write bursts -system.physmem.perBankWrBursts::3 32 # Per bank write bursts +system.physmem.perBankWrBursts::0 8 # Per bank write bursts +system.physmem.perBankWrBursts::1 125 # Per bank write bursts +system.physmem.perBankWrBursts::2 25 # Per bank write bursts +system.physmem.perBankWrBursts::3 26 # Per bank write bursts system.physmem.perBankWrBursts::4 54 # Per bank write bursts -system.physmem.perBankWrBursts::5 2 # Per bank write bursts -system.physmem.perBankWrBursts::6 17 # Per bank write bursts +system.physmem.perBankWrBursts::5 8 # Per bank write bursts +system.physmem.perBankWrBursts::6 14 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 6 # Per bank write bursts @@ -83,28 +83,28 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 65832525500 # Total gap between requests +system.physmem.totGap 65721290500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30664 # Read request sizes (log2) +system.physmem.readPktSize::6 30646 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 309 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29955 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 299 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -145,14 +145,14 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see @@ -160,18 +160,18 @@ system.physmem.wrQLenPdf::26 16 # Wh system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -194,355 +194,353 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2862 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 688.995108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 484.121076 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 395.829774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 415 14.50% 14.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 275 9.61% 24.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 149 5.21% 29.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 128 4.47% 33.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 140 4.89% 38.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 122 4.26% 42.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 77 2.69% 45.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 86 3.00% 48.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1470 51.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2862 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 1905.625000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 24.516989 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 7552.373489 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 15 93.75% 93.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 6.25% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.937500 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.914548 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.928709 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 12 75.00% 87.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 6.25% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads -system.physmem.totQLat 411710000 # Total ticks spent queuing -system.physmem.totMemAccLat 984260000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 152680000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13482.77 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2852 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 690.064516 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 482.522488 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 397.377699 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 418 14.66% 14.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 289 10.13% 24.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 128 4.49% 29.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 119 4.17% 33.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 133 4.66% 38.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 123 4.31% 42.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 83 2.91% 45.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2852 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 15 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2030.466667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.801531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 7801.447410 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 15 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 15 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.933333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.931540 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.258199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1 6.67% 6.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 14 93.33% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 15 # Writes before turning the bus around for reads +system.physmem.totQLat 402617750 # Total ticks spent queuing +system.physmem.totMemAccLat 974736500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 152565000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13194.96 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32232.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 29.69 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.28 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 29.81 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31944.96 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 29.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 29.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.29 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.23 # Data bus utilization in percentage system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.03 # Average write queue length when enqueuing -system.physmem.readRowHits 27751 # Number of row buffer hits during reads -system.physmem.writeRowHits 206 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.88 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.67 # Row buffer hit rate for writes -system.physmem.avgGap 2125481.08 # Average gap between requests -system.physmem.pageHitRate 90.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 11059860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5878455 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 113176140 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1451160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 315310320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 256763340 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 17698560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 981638610 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 270128640 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15008515620 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 16981623105 # Total energy per rank (pJ) -system.physmem_0.averagePower 257.950589 # Core power per rank (mW) -system.physmem_0.totalIdleTime 65223686000 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 24830750 # Time in different power states -system.physmem_0.memoryStateTime::REF 133713250 # Time in different power states -system.physmem_0.memoryStateTime::SREF 62367507500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 703478750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 450500500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 2152699750 # Time in different power states -system.physmem_1.actEnergy 9403380 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4982835 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 104850900 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 12.51 # Average write queue length when enqueuing +system.physmem.readRowHits 27734 # Number of row buffer hits during reads +system.physmem.writeRowHits 187 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.89 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.54 # Row buffer hit rate for writes +system.physmem.avgGap 2123809.68 # Average gap between requests +system.physmem.pageHitRate 90.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 11052720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5855685 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 113040480 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1357200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 309163920.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 263324610 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 16569120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 979073610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 268447200 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 14975920920 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 16943805465 # Total energy per rank (pJ) +system.physmem_0.averagePower 257.812234 # Core power per rank (mW) +system.physmem_0.totalIdleTime 65100637750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 22061500 # Time in different power states +system.physmem_0.memoryStateTime::REF 131194000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 62254705500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 699065250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 467433500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 2147034750 # Time in different power states +system.physmem_1.actEnergy 9374820 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4967655 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 104822340 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 389067120.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 256987920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 20546880 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1156119600 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 409490400 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 14841811380 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 17194149375 # Total energy per rank (pJ) -system.physmem_1.averagePower 261.179341 # Core power per rank (mW) -system.physmem_1.totalIdleTime 65212352000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 31901000 # Time in different power states -system.physmem_1.memoryStateTime::REF 165222000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 61612056250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1066374000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 421666750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2535510500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40426123 # Number of BP lookups -system.cpu.branchPred.condPredicted 40426123 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1402729 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 26580139 # Number of BTB lookups +system.physmem_1.refreshEnergy 372471840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 249536310 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 19488480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1119740490 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 403290240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 14835337125 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 17119488570 # Total energy per rank (pJ) +system.physmem_1.averagePower 260.485370 # Core power per rank (mW) +system.physmem_1.totalIdleTime 65120969250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 28589000 # Time in different power states +system.physmem_1.memoryStateTime::REF 158136000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 61616793750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1050209250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 412212500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2455554000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40406290 # Number of BP lookups +system.cpu.branchPred.condPredicted 40406290 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1431845 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26031629 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6011508 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 87453 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 26580139 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 21161652 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5418487 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 517301 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 6025963 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 91921 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 26031629 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 20992529 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5039100 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 530263 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 131665462 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 131442990 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 30553171 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 219967171 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40426123 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 27173160 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 99460538 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2919977 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 306 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 5927 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 105822 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 73 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 157 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 29763575 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 354176 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 15 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 131585982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.941987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.406730 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 30464048 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 219898668 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40406290 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 27018492 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 99269738 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2979935 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 465 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 128961 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 29660171 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 359072 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 17 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 131360995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.946103 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.409063 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 65985920 50.15% 50.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4028379 3.06% 53.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3611314 2.74% 55.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6113229 4.65% 60.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7745533 5.89% 66.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5553246 4.22% 70.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3377028 2.57% 73.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2847646 2.16% 75.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 32323687 24.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 65827184 50.11% 50.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4032527 3.07% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3600376 2.74% 55.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6081929 4.63% 60.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7728911 5.88% 66.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5535416 4.21% 70.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3331669 2.54% 73.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2842658 2.16% 75.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 32380325 24.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 131585982 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.307037 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.670652 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15243618 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64765794 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 40224064 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9892518 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1459988 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 362269877 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1459988 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 20789530 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11237370 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18362 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 44279240 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 53801492 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 352719757 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 16498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 793095 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 46882908 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5193491 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 355158766 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 934950269 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 575705414 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 24139 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 131360995 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307405 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.672959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15255907 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64520496 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 40208811 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9885814 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1489967 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 362265652 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1489967 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 20796133 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11129664 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 23832 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 44255424 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 53665975 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 352608748 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 23342 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 777450 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 46732943 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5205031 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 354925639 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 934456502 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 575559102 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 21159 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 75946019 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 487 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 484 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 64820498 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 112428453 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 38501164 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 51645718 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9056873 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 344114716 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4351 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 317908509 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166833 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 65926603 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 102202913 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3906 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 131585982 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.415976 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.164934 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 75712892 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 482 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 483 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 64647332 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 112313472 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 38475522 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 51426374 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8868395 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343765046 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3883 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 317634440 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 163759 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 65576465 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 101836454 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3438 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 131360995 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.418027 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.167913 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 35686444 27.12% 27.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20105227 15.28% 42.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17162197 13.04% 55.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17623881 13.39% 68.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15350950 11.67% 80.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12863479 9.78% 90.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 6692822 5.09% 95.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4078738 3.10% 98.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2022244 1.54% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 35651981 27.14% 27.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20061286 15.27% 42.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17078933 13.00% 55.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17586289 13.39% 68.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15273572 11.63% 80.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12870930 9.80% 90.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 6718617 5.11% 95.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4059315 3.09% 98.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2060072 1.57% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 131585982 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 131360995 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 364988 8.91% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3541451 86.44% 95.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 188937 4.61% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 10 0.00% 99.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 1524 0.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 367555 8.92% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.92% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3559749 86.40% 95.32% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 191317 4.64% 99.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 13 0.00% 99.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 1395 0.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 33340 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 181836417 57.20% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11458 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 362 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 334 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 101309174 31.87% 89.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34711229 10.92% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 553 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 5642 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 181647745 57.19% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11501 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 497 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 296 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 101245285 31.87% 89.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34690277 10.92% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 508 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 4992 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 317908509 # Type of FU issued -system.cpu.iq.rate 2.414517 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4096910 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012887 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 771648435 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 410069961 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 313720076 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 18308 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 36184 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 4316 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 321964016 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8063 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 57535034 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 317634440 # Type of FU issued +system.cpu.iq.rate 2.416519 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4120029 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012971 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 770896978 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 409373525 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 313389776 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 16685 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 31480 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3775 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 321713926 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7204 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 57497351 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 21649068 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 67666 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 63141 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 7061412 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 21534087 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66072 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 62227 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 7035770 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4025 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 141941 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4204 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 141777 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1459988 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8072611 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3068372 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 344119067 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 127232 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 112428453 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 38501164 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1782 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2921 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3074772 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 63141 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 534039 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1041947 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1575986 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 315496434 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 100557512 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2412075 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1489967 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8057522 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2987683 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343768929 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 139556 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 112313472 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 38475522 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1604 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2862 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2991864 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 62227 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 520614 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1090823 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1611437 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 315197484 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 100490397 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2436956 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 134869578 # number of memory reference insts executed -system.cpu.iew.exec_branches 32108537 # Number of branches executed -system.cpu.iew.exec_stores 34312066 # Number of stores executed -system.cpu.iew.exec_rate 2.396197 # Inst execution rate -system.cpu.iew.wb_sent 314359591 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 313724392 # cumulative count of insts written-back -system.cpu.iew.wb_producers 237724315 # num instructions producing a value -system.cpu.iew.wb_consumers 343443925 # num instructions consuming a value -system.cpu.iew.wb_rate 2.382739 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692178 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 66051294 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 134782236 # number of memory reference insts executed +system.cpu.iew.exec_branches 32089039 # Number of branches executed +system.cpu.iew.exec_stores 34291839 # Number of stores executed +system.cpu.iew.exec_rate 2.397979 # Inst execution rate +system.cpu.iew.wb_sent 314036708 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 313393551 # cumulative count of insts written-back +system.cpu.iew.wb_producers 237399400 # num instructions producing a value +system.cpu.iew.wb_consumers 342887037 # num instructions consuming a value +system.cpu.iew.wb_rate 2.384255 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692355 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 65692241 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1408834 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 122136825 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.277712 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.048100 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1439325 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 121896437 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.282203 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.051706 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 57021615 46.69% 46.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16508640 13.52% 60.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 11210798 9.18% 69.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8746505 7.16% 76.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2078517 1.70% 78.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1759712 1.44% 79.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 926228 0.76% 80.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 725763 0.59% 81.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23159047 18.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 56939574 46.71% 46.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16454719 13.50% 60.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 11025665 9.05% 69.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8756483 7.18% 76.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2109912 1.73% 78.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1768746 1.45% 79.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 935268 0.77% 80.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 726580 0.60% 80.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23179490 19.02% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 122136825 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 121896437 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -592,466 +590,466 @@ system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23159047 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 443221536 # The number of ROB reads -system.cpu.rob.rob_writes 698006714 # The number of ROB writes -system.cpu.timesIdled 877 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 79480 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 23179490 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 442601652 # The number of ROB reads +system.cpu.rob.rob_writes 697313320 # The number of ROB writes +system.cpu.timesIdled 909 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 81995 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.833386 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.833386 # CPI: Total CPI of All Threads -system.cpu.ipc 1.199924 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.199924 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 502917784 # number of integer regfile reads -system.cpu.int_regfile_writes 247848787 # number of integer regfile writes -system.cpu.fp_regfile_reads 4075 # number of floating regfile reads -system.cpu.fp_regfile_writes 819 # number of floating regfile writes -system.cpu.cc_regfile_reads 109098841 # number of cc regfile reads -system.cpu.cc_regfile_writes 65494445 # number of cc regfile writes -system.cpu.misc_regfile_reads 201957201 # number of misc regfile reads +system.cpu.cpi 0.831978 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.831978 # CPI: Total CPI of All Threads +system.cpu.ipc 1.201955 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.201955 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 502529726 # number of integer regfile reads +system.cpu.int_regfile_writes 247564665 # number of integer regfile writes +system.cpu.fp_regfile_reads 3566 # number of floating regfile reads +system.cpu.fp_regfile_writes 731 # number of floating regfile writes +system.cpu.cc_regfile_reads 108994485 # number of cc regfile reads +system.cpu.cc_regfile_writes 65428204 # number of cc regfile writes +system.cpu.misc_regfile_reads 201784346 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2073306 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.354566 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 71520008 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2077402 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.427621 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 21024099500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.354566 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993006 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993006 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2073509 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.268199 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 71482624 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2077605 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.406263 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 21075173500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.268199 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992985 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992985 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 500 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3447 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 504 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3445 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 150691296 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 150691296 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 40173982 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 40173982 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31346026 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31346026 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 71520008 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 71520008 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 71520008 # number of overall hits -system.cpu.dcache.overall_hits::total 71520008 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2693213 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2693213 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93726 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93726 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2786939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2786939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2786939 # number of overall misses -system.cpu.dcache.overall_misses::total 2786939 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 32416728500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 32416728500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3181034987 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3181034987 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35597763487 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35597763487 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35597763487 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35597763487 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 42867195 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 42867195 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 150633517 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150633517 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 40136683 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 40136683 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345941 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345941 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 71482624 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 71482624 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 71482624 # number of overall hits +system.cpu.dcache.overall_hits::total 71482624 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2701521 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2701521 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93811 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93811 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2795332 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2795332 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2795332 # number of overall misses +system.cpu.dcache.overall_misses::total 2795332 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32454671000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32454671000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3177582491 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3177582491 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35632253491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35632253491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35632253491 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35632253491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 42838204 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 42838204 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 74306947 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 74306947 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 74306947 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 74306947 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.062827 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.062827 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002981 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037506 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037506 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037506 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037506 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12036.451814 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12036.451814 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33939.728432 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33939.728432 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12773.068764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12773.068764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12773.068764 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 220832 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 385 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 43178 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.114456 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.250000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2066926 # number of writebacks -system.cpu.dcache.writebacks::total 2066926 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 697625 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 697625 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11912 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11912 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 709537 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 709537 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 709537 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 709537 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995588 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1995588 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81814 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81814 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2077402 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2077402 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2077402 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2077402 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24271228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 24271228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3023849487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3023849487 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27295077987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27295077987 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27295077987 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27295077987 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046553 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046553 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002602 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002602 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.027957 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027957 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027957 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.444603 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.444603 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36960.049466 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36960.049466 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13139.044820 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13139.044820 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 93 # number of replacements -system.cpu.icache.tags.tagsinuse 878.108473 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 29762089 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1121 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 26549.588760 # Average number of references to valid blocks. +system.cpu.dcache.demand_accesses::cpu.data 74277956 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 74277956 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 74277956 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 74277956 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063063 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.063063 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002984 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002984 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12013.480924 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12013.480924 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33872.173743 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33872.173743 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12747.055982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12747.055982 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 219709 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 682 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 43158 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.090806 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 113.666667 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2066902 # number of writebacks +system.cpu.dcache.writebacks::total 2066902 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705827 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 705827 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11900 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11900 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 717727 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 717727 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 717727 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 717727 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995694 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1995694 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81911 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81911 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2077605 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2077605 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2077605 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2077605 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24272933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 24272933500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3020316491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3020316491 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27293249991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 27293249991 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27293249991 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 27293249991 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046587 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046587 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002605 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002605 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.027971 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027971 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027971 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12162.652942 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12162.652942 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36873.148796 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36873.148796 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13136.881164 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 13136.881164 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 86 # number of replacements +system.cpu.icache.tags.tagsinuse 865.699388 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 29658716 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1101 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 26937.980018 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 878.108473 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.428764 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.428764 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1028 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 910 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59528269 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59528269 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 29762089 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 29762089 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 29762089 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 29762089 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 29762089 # number of overall hits -system.cpu.icache.overall_hits::total 29762089 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1485 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1485 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1485 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1485 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1485 # number of overall misses -system.cpu.icache.overall_misses::total 1485 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 149774999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 149774999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 149774999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 149774999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 149774999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 149774999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 29763574 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 29763574 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 29763574 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 100858.585185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 100858.585185 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 100858.585185 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2965 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 865.699388 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.422705 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.422705 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1015 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 900 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.495605 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 59321439 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59321439 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 29658716 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 29658716 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 29658716 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 29658716 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 29658716 # number of overall hits +system.cpu.icache.overall_hits::total 29658716 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1453 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1453 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1453 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1453 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1453 # number of overall misses +system.cpu.icache.overall_misses::total 1453 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 154504998 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 154504998 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 154504998 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 154504998 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 154504998 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 154504998 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1101 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1101 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1995663 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 1995663 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1101 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2077605 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2078706 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1101 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2077605 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2078706 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353860 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353860 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.976385 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.976385 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000288 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000288 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.976385 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014233 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014743 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.976385 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014233 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014743 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80740.360739 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80740.360739 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 103534.883721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 103534.883721 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 153764.347826 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 153764.347826 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82910.069830 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 103534.883721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82160.292178 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82910.069830 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks -system.cpu.l2cache.writebacks::total 309 # number of writebacks -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28990 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28990 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1093 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1093 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 581 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 581 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.writebacks::writebacks 299 # number of writebacks +system.cpu.l2cache.writebacks::total 299 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1075 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1075 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 575 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 575 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 29571 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1093 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30646 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29571 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30664 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2055891000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2055891000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 101960000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 101960000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 86879500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 86879500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 101960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2142770500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 2244730500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 101960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2142770500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 2244730500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.354193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.354193 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.975022 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000291 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000291 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014753 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.975022 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014235 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014753 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70917.247327 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70917.247327 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93284.537969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93284.537969 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 149534.423408 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 149534.423408 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93284.537969 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72461.888337 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73204.099270 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4151922 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073402 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 20 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 335 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 335 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_misses::total 30646 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2051187500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2051187500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 100550000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 100550000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 82664500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 82664500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 100550000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2133852000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2234402000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4152301 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 330 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1996675 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2067235 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 93 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6765 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81848 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1121 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995554 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2335 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228110 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6230445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265236992 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265314688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 694 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 19776 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2079217 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.000172 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.013121 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1996764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 86 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6988 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 81942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 81942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6231007 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265324416 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 680 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19136 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2079386 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000170 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.013047 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2078859 99.98% 99.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 358 0.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2079217 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4142980000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2079386 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4143138500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1681500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1652498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3116103000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3116407500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 31023 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 359 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 30996 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 350 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 65832730500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1674 # Transaction distribution -system.membus.trans_dist::WritebackDirty 309 # Transaction distribution -system.membus.trans_dist::CleanEvict 50 # Transaction distribution -system.membus.trans_dist::ReadExReq 28990 # Transaction distribution -system.membus.trans_dist::ReadExResp 28990 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1674 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61687 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61687 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1982272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1982272 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1982272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1650 # Transaction distribution +system.membus.trans_dist::WritebackDirty 299 # Transaction distribution +system.membus.trans_dist::CleanEvict 51 # Transaction distribution +system.membus.trans_dist::ReadExReq 28996 # Transaction distribution +system.membus.trans_dist::ReadExResp 28996 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1650 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61642 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1980480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 30664 # Request fanout histogram +system.membus.snoop_fanout::samples 30646 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30664 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30646 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30664 # Request fanout histogram -system.membus.reqLayer0.occupancy 43676000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30646 # Request fanout histogram +system.membus.reqLayer0.occupancy 43591500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 161581250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 161486250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 5f5ab2bca..4152fbfe4 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,106 +1,106 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.368600 # Number of seconds simulated -sim_ticks 368600047500 # Number of ticks simulated -final_tick 368600047500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.368651 # Number of seconds simulated +sim_ticks 368651185500 # Number of ticks simulated +final_tick 368651185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 377886 # Simulator instruction rate (inst/s) -host_op_rate 409300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 274959159 # Simulator tick rate (ticks/s) -host_mem_usage 276756 # Number of bytes of host memory used -host_seconds 1340.56 # Real time elapsed on the host +host_inst_rate 378825 # Simulator instruction rate (inst/s) +host_op_rate 410318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 275680946 # Simulator tick rate (ticks/s) +host_mem_usage 276920 # Number of bytes of host memory used +host_seconds 1337.24 # Real time elapsed on the host sim_insts 506579366 # Number of instructions simulated sim_ops 548692589 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 179840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9053376 # Number of bytes read from this memory -system.physmem.bytes_read::total 9233216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 179840 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6241792 # Number of bytes written to this memory -system.physmem.bytes_written::total 6241792 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141459 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144269 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97528 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97528 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 487900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24561516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25049416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 487900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 487900 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16933780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16933780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16933780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 487900 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24561516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 41983196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144269 # Number of read requests accepted -system.physmem.writeReqs 97528 # Number of write requests accepted -system.physmem.readBursts 144269 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97528 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9225856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue -system.physmem.bytesWritten 6240448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9233216 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6241792 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 179712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9049216 # Number of bytes read from this memory +system.physmem.bytes_read::total 9228928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 179712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 179712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6241472 # Number of bytes written to this memory +system.physmem.bytes_written::total 6241472 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2808 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141394 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144202 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97523 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97523 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 487485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24546825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25034310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 487485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 487485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16930563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16930563 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16930563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 487485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24546825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41964873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144202 # Number of read requests accepted +system.physmem.writeReqs 97523 # Number of write requests accepted +system.physmem.readBursts 144202 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97523 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9222208 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6720 # Total number of bytes read from write queue +system.physmem.bytesWritten 6240000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9228928 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6241472 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 105 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9372 # Per bank write bursts -system.physmem.perBankRdBursts::1 8929 # Per bank write bursts -system.physmem.perBankRdBursts::2 8963 # Per bank write bursts -system.physmem.perBankRdBursts::3 8667 # Per bank write bursts -system.physmem.perBankRdBursts::4 9424 # Per bank write bursts -system.physmem.perBankRdBursts::5 9372 # Per bank write bursts -system.physmem.perBankRdBursts::6 8974 # Per bank write bursts -system.physmem.perBankRdBursts::7 8127 # Per bank write bursts -system.physmem.perBankRdBursts::8 8635 # Per bank write bursts -system.physmem.perBankRdBursts::9 8697 # Per bank write bursts -system.physmem.perBankRdBursts::10 8761 # Per bank write bursts -system.physmem.perBankRdBursts::11 9485 # Per bank write bursts -system.physmem.perBankRdBursts::12 9346 # Per bank write bursts -system.physmem.perBankRdBursts::13 9545 # Per bank write bursts -system.physmem.perBankRdBursts::14 8729 # Per bank write bursts -system.physmem.perBankRdBursts::15 9128 # Per bank write bursts -system.physmem.perBankWrBursts::0 6253 # Per bank write bursts -system.physmem.perBankWrBursts::1 6118 # Per bank write bursts -system.physmem.perBankWrBursts::2 6042 # Per bank write bursts -system.physmem.perBankWrBursts::3 5901 # Per bank write bursts -system.physmem.perBankWrBursts::4 6273 # Per bank write bursts -system.physmem.perBankWrBursts::5 6263 # Per bank write bursts -system.physmem.perBankWrBursts::6 6069 # Per bank write bursts +system.physmem.perBankRdBursts::0 9327 # Per bank write bursts +system.physmem.perBankRdBursts::1 8931 # Per bank write bursts +system.physmem.perBankRdBursts::2 8953 # Per bank write bursts +system.physmem.perBankRdBursts::3 8672 # Per bank write bursts +system.physmem.perBankRdBursts::4 9421 # Per bank write bursts +system.physmem.perBankRdBursts::5 9371 # Per bank write bursts +system.physmem.perBankRdBursts::6 8975 # Per bank write bursts +system.physmem.perBankRdBursts::7 8126 # Per bank write bursts +system.physmem.perBankRdBursts::8 8631 # Per bank write bursts +system.physmem.perBankRdBursts::9 8699 # Per bank write bursts +system.physmem.perBankRdBursts::10 8760 # Per bank write bursts +system.physmem.perBankRdBursts::11 9484 # Per bank write bursts +system.physmem.perBankRdBursts::12 9351 # Per bank write bursts +system.physmem.perBankRdBursts::13 9541 # Per bank write bursts +system.physmem.perBankRdBursts::14 8731 # Per bank write bursts +system.physmem.perBankRdBursts::15 9124 # Per bank write bursts +system.physmem.perBankWrBursts::0 6232 # Per bank write bursts +system.physmem.perBankWrBursts::1 6121 # Per bank write bursts +system.physmem.perBankWrBursts::2 6045 # Per bank write bursts +system.physmem.perBankWrBursts::3 5902 # Per bank write bursts +system.physmem.perBankWrBursts::4 6267 # Per bank write bursts +system.physmem.perBankWrBursts::5 6264 # Per bank write bursts +system.physmem.perBankWrBursts::6 6070 # Per bank write bursts system.physmem.perBankWrBursts::7 5535 # Per bank write bursts system.physmem.perBankWrBursts::8 5819 # Per bank write bursts -system.physmem.perBankWrBursts::9 5920 # Per bank write bursts +system.physmem.perBankWrBursts::9 5921 # Per bank write bursts system.physmem.perBankWrBursts::10 5985 # Per bank write bursts -system.physmem.perBankWrBursts::11 6510 # Per bank write bursts -system.physmem.perBankWrBursts::12 6360 # Per bank write bursts -system.physmem.perBankWrBursts::13 6344 # Per bank write bursts -system.physmem.perBankWrBursts::14 6013 # Per bank write bursts +system.physmem.perBankWrBursts::11 6509 # Per bank write bursts +system.physmem.perBankWrBursts::12 6365 # Per bank write bursts +system.physmem.perBankWrBursts::13 6345 # Per bank write bursts +system.physmem.perBankWrBursts::14 6018 # Per bank write bursts system.physmem.perBankWrBursts::15 6102 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 368600022000 # Total gap between requests +system.physmem.totGap 368651160000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144269 # Read request sizes (log2) +system.physmem.readPktSize::6 144202 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97528 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143801 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97523 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143745 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 333 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -145,32 +145,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 5746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -194,116 +194,116 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63970 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 241.763327 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.115864 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 241.210402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22774 35.60% 35.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18302 28.61% 64.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7461 11.66% 75.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8049 12.58% 88.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2117 3.31% 91.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1180 1.84% 93.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 776 1.21% 94.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 623 0.97% 95.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2688 4.20% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63970 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5740 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.113240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 375.658190 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5737 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 64014 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 241.533165 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 161.867212 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.438904 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22835 35.67% 35.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18294 28.58% 64.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7516 11.74% 75.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7993 12.49% 88.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2085 3.26% 91.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1176 1.84% 93.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 786 1.23% 94.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 642 1.00% 95.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2687 4.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64014 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5742 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.094566 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 375.615355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5739 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5740 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5740 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.987282 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.957535 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.009458 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2852 49.69% 49.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 159 2.77% 52.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 2701 47.06% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 19 0.33% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 6 0.10% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5740 # Writes before turning the bus around for reads -system.physmem.totQLat 3577410500 # Total ticks spent queuing -system.physmem.totMemAccLat 6280298000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24816.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5742 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5742 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.980146 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.950575 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.005103 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2875 50.07% 50.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 152 2.65% 52.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 2688 46.81% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 17 0.30% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 6 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5742 # Writes before turning the bus around for reads +system.physmem.totQLat 3587327500 # Total ticks spent queuing +system.physmem.totMemAccLat 6289146250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720485000 # Total ticks spent in databus transfers +system.physmem.avgQLat 24895.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43566.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 43645.23 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.02 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 16.93 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.05 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 16.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.06 # Average write queue length when enqueuing -system.physmem.readRowHits 110541 # Number of row buffer hits during reads -system.physmem.writeRowHits 67141 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.68 # Row buffer hit rate for reads +system.physmem.avgWrQLen 19.95 # Average write queue length when enqueuing +system.physmem.readRowHits 110436 # Number of row buffer hits during reads +system.physmem.writeRowHits 67138 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.64 # Row buffer hit rate for reads system.physmem.writeRowHitRate 68.84 # Row buffer hit rate for writes -system.physmem.avgGap 1524419.34 # Average gap between requests -system.physmem.pageHitRate 73.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 229615260 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 122028225 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512851920 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 252929880 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7711888080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3985232520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 353635200 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 24742392420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8329190880 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 68838786810 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 115080429525 # Total energy per rank (pJ) -system.physmem_0.averagePower 312.209478 # Core power per rank (mW) -system.physmem_0.totalIdleTime 358934929250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 533175250 # Time in different power states -system.physmem_0.memoryStateTime::REF 3272498000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 282985158000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21690772000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5858998750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 54259445500 # Time in different power states -system.physmem_1.actEnergy 227194800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 120737925 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 516407640 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 256056660 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7588960080.000002 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3990680010 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 342748800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 24389261460 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8128903200 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 69135043560 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 114698287785 # Total energy per rank (pJ) -system.physmem_1.averagePower 311.172742 # Core power per rank (mW) -system.physmem_1.totalIdleTime 358951299500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 511434000 # Time in different power states -system.physmem_1.memoryStateTime::REF 3220288000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 284296687500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 21168817000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5916972250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 53485848750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 132103819 # Number of BP lookups -system.cpu.branchPred.condPredicted 98193306 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5910048 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 68601561 # Number of BTB lookups -system.cpu.branchPred.BTBHits 60590477 # Number of BTB hits +system.physmem.avgGap 1525084.95 # Average gap between requests +system.physmem.pageHitRate 73.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229772340 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 122107920 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512480640 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 252835920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 7717419840.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4012679730 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 354856800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 24782953050 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8303052480 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 68829850950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 115120015110 # Total energy per rank (pJ) +system.physmem_0.averagePower 312.273551 # Core power per rank (mW) +system.physmem_0.totalIdleTime 358922434750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 536706250 # Time in different power states +system.physmem_0.memoryStateTime::REF 3274898000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 282951785250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21622731000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5916696250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 54348368750 # Time in different power states +system.physmem_1.actEnergy 227351880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 120825210 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 516371940 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 256114080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 7627682400.000002 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3951722790 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 344311680 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 24510614460 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8148381600 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 69110361900 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 114816583080 # Total energy per rank (pJ) +system.physmem_1.averagePower 311.450463 # Core power per rank (mW) +system.physmem_1.totalIdleTime 359082796500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 515499000 # Time in different power states +system.physmem_1.memoryStateTime::REF 3236866000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 284111116500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 21219892250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5815970250 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 53751841500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 132096754 # Number of BP lookups +system.cpu.branchPred.condPredicted 98183062 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5916233 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68556674 # Number of BTB lookups +system.cpu.branchPred.BTBHits 60606255 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 88.322301 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10017121 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 18743 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3891575 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 3883028 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 8547 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 54138 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 88.403144 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10020256 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 19127 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3891736 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 3883139 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 8597 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 54132 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -333,7 +333,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -363,7 +363,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -393,7 +393,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -424,16 +424,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 737200095 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 737302371 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506579366 # Number of instructions committed system.cpu.committedOps 548692589 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12939783 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12932918 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.455251 # CPI: cycles per instruction -system.cpu.ipc 0.687167 # IPC: instructions per cycle +system.cpu.cpi 1.455453 # CPI: cycles per instruction +system.cpu.ipc 0.687071 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 375609862 68.46% 68.46% # Class of committed instruction system.cpu.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction @@ -473,346 +473,346 @@ system.cpu.op_class_0::FloatMemWrite 16 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 548692589 # Class of committed instruction -system.cpu.tickCycles 694074449 # Number of cycles that the object actually ticked -system.cpu.idleCycles 43125646 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1141337 # number of replacements -system.cpu.dcache.tags.tagsinuse 4070.214598 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171083823 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1145433 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.361703 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5072633500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4070.214598 # Average occupied blocks per requestor +system.cpu.tickCycles 694166450 # Number of cycles that the object actually ticked +system.cpu.idleCycles 43135921 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1141334 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.216677 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171085721 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1145430 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.363751 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5072789500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.216677 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993705 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 543 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 548 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3502 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346338043 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346338043 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114566012 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114566012 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53537935 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53537935 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2794 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2794 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 346341652 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346341652 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114567880 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114567880 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53537967 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53537967 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2792 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2792 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168103947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168103947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168106741 # number of overall hits -system.cpu.dcache.overall_hits::total 168106741 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 811353 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 811353 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 701114 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 701114 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 168105847 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168105847 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168108639 # number of overall hits +system.cpu.dcache.overall_hits::total 168108639 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 811293 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 811293 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 701082 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 701082 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 15 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 15 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1512467 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1512467 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1512482 # number of overall misses -system.cpu.dcache.overall_misses::total 1512482 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14511839000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14511839000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 24015670000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 24015670000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 38527509000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 38527509000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 38527509000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 38527509000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115377365 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115377365 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1512375 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1512375 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1512390 # number of overall misses +system.cpu.dcache.overall_misses::total 1512390 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14512864500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14512864500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24025186500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24025186500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 38538051000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 38538051000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 38538051000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 38538051000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115379173 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115379173 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2809 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2809 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2807 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2807 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169616414 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169616414 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169619223 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169619223 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169618222 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169618222 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169621029 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169621029 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007032 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012926 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.012926 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005340 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.005340 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008917 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008917 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008917 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008917 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17885.974416 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17885.974416 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34253.587862 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34253.587862 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25473.289004 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25473.289004 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25473.036373 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25473.036373 # average overall miss latency +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005344 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.005344 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008916 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008916 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008916 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008916 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17888.561223 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17888.561223 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34268.725342 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34268.725342 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 25481.809075 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 25481.809075 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 25481.556345 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 25481.556345 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1068942 # number of writebacks -system.cpu.dcache.writebacks::total 1068942 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22320 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 22320 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344726 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344726 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 367046 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 367046 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 367046 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 367046 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789033 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 789033 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356388 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356388 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 1068964 # number of writebacks +system.cpu.dcache.writebacks::total 1068964 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22242 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 22242 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344715 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344715 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366957 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366957 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366957 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366957 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 789051 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 789051 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356367 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356367 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 12 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 12 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1145421 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1145421 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1145433 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1145433 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13416892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 13416892000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12196191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12196191500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4297000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25613083500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 25613083500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25617380500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 25617380500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1145418 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1145418 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1145430 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1145430 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 13418418500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 13418418500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12201205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12201205500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 4179500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 4179500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25619624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25619624000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25623803500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25623803500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006839 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006839 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006571 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004272 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004272 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006570 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006570 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.004275 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.004275 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006753 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006753 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006753 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17004.221623 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17004.221623 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34221.667116 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34221.667116 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 358083.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 358083.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22361.283319 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22361.283319 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22364.800473 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22364.800473 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 18178 # number of replacements -system.cpu.icache.tags.tagsinuse 1186.508929 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 199149019 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 20050 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9932.619401 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17005.768322 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17005.768322 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34237.753496 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 34237.753496 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 348291.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 348291.666667 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22367.052028 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22367.052028 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22370.466550 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22370.466550 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 18132 # number of replacements +system.cpu.icache.tags.tagsinuse 1186.493230 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 199187334 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 20004 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9957.375225 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1186.508929 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.579350 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.579350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1186.493230 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.579342 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.579342 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 311 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1400 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 318 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1398 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 398358188 # Number of tag accesses -system.cpu.icache.tags.data_accesses 398358188 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 199149019 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 199149019 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 199149019 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 199149019 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 199149019 # number of overall hits -system.cpu.icache.overall_hits::total 199149019 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 20050 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 20050 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 20050 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 20050 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 20050 # number of overall misses -system.cpu.icache.overall_misses::total 20050 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 544279500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 544279500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 544279500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 544279500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 544279500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 544279500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 199169069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 199169069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 199169069 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 199169069 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 199169069 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 199169069 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000101 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000101 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000101 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000101 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000101 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000101 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27146.109726 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27146.109726 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27146.109726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27146.109726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27146.109726 # average overall miss latency +system.cpu.icache.tags.tag_accesses 398434680 # Number of tag accesses +system.cpu.icache.tags.data_accesses 398434680 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 199187334 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 199187334 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 199187334 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 199187334 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 199187334 # number of overall hits +system.cpu.icache.overall_hits::total 199187334 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 20004 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 20004 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 20004 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 20004 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 20004 # number of overall misses +system.cpu.icache.overall_misses::total 20004 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 543340500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 543340500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 543340500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 543340500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 543340500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 543340500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 199207338 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 199207338 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 199207338 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 199207338 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 199207338 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 199207338 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000100 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000100 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000100 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000100 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000100 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000100 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27161.592681 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27161.592681 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27161.592681 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27161.592681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27161.592681 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27161.592681 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 18178 # number of writebacks -system.cpu.icache.writebacks::total 18178 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20050 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 20050 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 20050 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 20050 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 20050 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 20050 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 524229500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 524229500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 524229500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 524229500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 524229500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 524229500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000101 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000101 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000101 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26146.109726 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26146.109726 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26146.109726 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26146.109726 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 112761 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29076.848035 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2174458 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 145529 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.941750 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 102118428000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 133.889045 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 307.541066 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28635.417923 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.004086 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009385 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.873884 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.887355 # Average percentage of cache occupancy +system.cpu.icache.writebacks::writebacks 18132 # number of writebacks +system.cpu.icache.writebacks::total 18132 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 20004 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 20004 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 20004 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 20004 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 20004 # 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mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000100 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000100 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26161.592681 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26161.592681 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26161.592681 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26161.592681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26161.592681 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26161.592681 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 112700 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29077.009680 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2174426 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 145468 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.947796 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 102124248000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 135.271970 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 308.139631 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28633.598078 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.004128 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009404 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.873828 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.887360 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 981 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 988 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31579 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18705537 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18705537 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 1068942 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 1068942 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 17940 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 17940 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255660 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255660 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 17239 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 17239 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 748301 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 748301 # number of ReadSharedReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17239 # 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number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356638 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 20050 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadCleanReq_accesses::total 20050 # number of ReadCleanReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 788795 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.ReadSharedReq_accesses::total 788795 # number of ReadSharedReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 20050 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1145433 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1165483 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 20050 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1145433 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1165483 # 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number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.writebacks::writebacks 97528 # number of writebacks -system.cpu.l2cache.writebacks::total 97528 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97523 # number of writebacks +system.cpu.l2cache.writebacks::total 97523 # number of writebacks system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 13 # number of ReadSharedReq MSHR hits @@ -823,126 +823,126 @@ system.cpu.l2cache.demand_mshr_hits::total 14 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 13 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 14 # 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Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100957 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100957 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2808 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2808 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 40437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 40437 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2808 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141394 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144202 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141394 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144202 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7975130500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7975130500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 283956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 283956000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 3955182000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 3955182000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283956000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11930312500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12214268500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283956000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11930312500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12214268500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283095 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283095 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.140372 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.051263 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.051263 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123732 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.140372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123442 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123732 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78995.319790 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 78995.319790 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 101123.931624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 101123.931624 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 97810.965205 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 97810.965205 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 101123.931624 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84376.370284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84702.490257 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 2324900 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 1159536 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 4992 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 2618 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2615 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 808845 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 1166470 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 18178 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 87628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356638 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 20050 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 788795 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58278 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432203 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3490481 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2446592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141720000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 144166592 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 112761 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6241792 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1278244 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.006015 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.077350 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 808815 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 1166487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 18132 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 87547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356619 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 20004 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 788811 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58140 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3432194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3490334 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2440704 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141721216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 144161920 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 112700 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6241472 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1278134 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.006011 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.077328 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1270559 99.40% 99.40% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 7682 0.60% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1270454 99.40% 99.40% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 7677 0.60% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1278244 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2249619000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1278134 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2249546000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30098453 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30029453 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1718157983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1718153483 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 254412 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 110315 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 254284 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 110251 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 368600047500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 43291 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97528 # Transaction distribution -system.membus.trans_dist::CleanEvict 12615 # Transaction distribution -system.membus.trans_dist::ReadExReq 100978 # Transaction distribution -system.membus.trans_dist::ReadExResp 100978 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 43291 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398681 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 398681 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15475008 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15475008 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 368651185500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 43245 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97523 # Transaction distribution +system.membus.trans_dist::CleanEvict 12559 # Transaction distribution +system.membus.trans_dist::ReadExReq 100957 # Transaction distribution +system.membus.trans_dist::ReadExResp 100957 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 43245 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 398486 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 398486 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15470400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15470400 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 144269 # Request fanout histogram +system.membus.snoop_fanout::samples 144202 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 144269 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 144202 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 144269 # Request fanout histogram -system.membus.reqLayer0.occupancy 685127000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 144202 # Request fanout histogram +system.membus.reqLayer0.occupancy 684899000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 765884750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 765515250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 3dfc36814..d29a9ad2d 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.236024 # Number of seconds simulated -sim_ticks 236023688000 # Number of ticks simulated -final_tick 236023688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.235850 # Number of seconds simulated +sim_ticks 235850129000 # Number of ticks simulated +final_tick 235850129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 256452 # Simulator instruction rate (inst/s) -host_op_rate 277829 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 119803336 # Simulator tick rate (ticks/s) -host_mem_usage 301968 # Number of bytes of host memory used -host_seconds 1970.09 # Real time elapsed on the host +host_inst_rate 254127 # Simulator instruction rate (inst/s) +host_op_rate 275309 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118629630 # Simulator tick rate (ticks/s) +host_mem_usage 302132 # Number of bytes of host memory used +host_seconds 1988.12 # Real time elapsed on the host sim_insts 505234934 # Number of instructions simulated sim_ops 547348155 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 640832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10509760 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16394496 # Number of bytes read from this memory -system.physmem.bytes_read::total 27545088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 640832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 640832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18630208 # Number of bytes written to this memory -system.physmem.bytes_written::total 18630208 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 164215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 256164 # Number of read requests responded to by this memory -system.physmem.num_reads::total 430392 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 291097 # Number of write requests responded to by this memory -system.physmem.num_writes::total 291097 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2715117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 44528412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 69461231 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 116704761 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2715117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2715117 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 78933637 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 78933637 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 78933637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2715117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 44528412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 69461231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 195638397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 430392 # Number of read requests accepted -system.physmem.writeReqs 291097 # Number of write requests accepted -system.physmem.readBursts 430392 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 291097 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27379648 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 165440 # Total number of bytes read from write queue -system.physmem.bytesWritten 18628032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27545088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18630208 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2585 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10497792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 # Number of bytes read from this memory +system.physmem.bytes_read::total 27559104 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651264 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18653440 # Number of bytes written to this memory +system.physmem.bytes_written::total 18653440 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 164028 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 256407 # Number of read requests responded to by this memory +system.physmem.num_reads::total 430611 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 291460 # Number of write requests responded to by this memory +system.physmem.num_writes::total 291460 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2761347 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 44510436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 116850070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2761347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2761347 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 79090226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 79090226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 79090226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2761347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 44510436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 195940296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 430611 # Number of read requests accepted +system.physmem.writeReqs 291460 # Number of write requests accepted +system.physmem.readBursts 430611 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 291460 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 27396288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 162816 # Total number of bytes read from write queue +system.physmem.bytesWritten 18651392 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 27559104 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18653440 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2544 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 9 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27300 # Per bank write bursts -system.physmem.perBankRdBursts::1 26589 # Per bank write bursts -system.physmem.perBankRdBursts::2 25489 # Per bank write bursts -system.physmem.perBankRdBursts::3 32817 # Per bank write bursts -system.physmem.perBankRdBursts::4 28238 # Per bank write bursts -system.physmem.perBankRdBursts::5 30052 # Per bank write bursts -system.physmem.perBankRdBursts::6 25322 # Per bank write bursts -system.physmem.perBankRdBursts::7 24428 # Per bank write bursts -system.physmem.perBankRdBursts::8 25638 # Per bank write bursts -system.physmem.perBankRdBursts::9 25508 # Per bank write bursts -system.physmem.perBankRdBursts::10 25695 # Per bank write bursts -system.physmem.perBankRdBursts::11 26146 # Per bank write bursts -system.physmem.perBankRdBursts::12 27543 # Per bank write bursts -system.physmem.perBankRdBursts::13 26122 # Per bank write bursts -system.physmem.perBankRdBursts::14 24924 # Per bank write bursts -system.physmem.perBankRdBursts::15 25996 # Per bank write bursts -system.physmem.perBankWrBursts::0 18688 # Per bank write bursts -system.physmem.perBankWrBursts::1 18252 # Per bank write bursts -system.physmem.perBankWrBursts::2 17892 # Per bank write bursts -system.physmem.perBankWrBursts::3 17877 # Per bank write bursts -system.physmem.perBankWrBursts::4 18635 # Per bank write bursts -system.physmem.perBankWrBursts::5 18189 # Per bank write bursts -system.physmem.perBankWrBursts::6 17877 # Per bank write bursts -system.physmem.perBankWrBursts::7 17743 # Per bank write bursts -system.physmem.perBankWrBursts::8 17943 # Per bank write bursts -system.physmem.perBankWrBursts::9 17697 # Per bank write bursts -system.physmem.perBankWrBursts::10 18014 # Per bank write bursts -system.physmem.perBankWrBursts::11 18785 # Per bank write bursts -system.physmem.perBankWrBursts::12 18684 # Per bank write bursts -system.physmem.perBankWrBursts::13 18184 # Per bank write bursts -system.physmem.perBankWrBursts::14 18324 # Per bank write bursts -system.physmem.perBankWrBursts::15 18279 # Per bank write bursts +system.physmem.perBankRdBursts::0 27102 # Per bank write bursts +system.physmem.perBankRdBursts::1 26174 # Per bank write bursts +system.physmem.perBankRdBursts::2 25664 # Per bank write bursts +system.physmem.perBankRdBursts::3 33006 # Per bank write bursts +system.physmem.perBankRdBursts::4 27996 # Per bank write bursts +system.physmem.perBankRdBursts::5 29984 # Per bank write bursts +system.physmem.perBankRdBursts::6 25487 # Per bank write bursts +system.physmem.perBankRdBursts::7 24586 # Per bank write bursts +system.physmem.perBankRdBursts::8 25526 # Per bank write bursts +system.physmem.perBankRdBursts::9 25681 # Per bank write bursts +system.physmem.perBankRdBursts::10 25862 # Per bank write bursts +system.physmem.perBankRdBursts::11 26092 # Per bank write bursts +system.physmem.perBankRdBursts::12 27614 # Per bank write bursts +system.physmem.perBankRdBursts::13 26106 # Per bank write bursts +system.physmem.perBankRdBursts::14 25123 # Per bank write bursts +system.physmem.perBankRdBursts::15 26064 # Per bank write bursts +system.physmem.perBankWrBursts::0 18530 # Per bank write bursts +system.physmem.perBankWrBursts::1 18172 # Per bank write bursts +system.physmem.perBankWrBursts::2 17960 # Per bank write bursts +system.physmem.perBankWrBursts::3 17946 # Per bank write bursts +system.physmem.perBankWrBursts::4 18535 # Per bank write bursts +system.physmem.perBankWrBursts::5 18092 # Per bank write bursts +system.physmem.perBankWrBursts::6 17937 # Per bank write bursts +system.physmem.perBankWrBursts::7 17864 # Per bank write bursts +system.physmem.perBankWrBursts::8 17881 # Per bank write bursts +system.physmem.perBankWrBursts::9 17814 # Per bank write bursts +system.physmem.perBankWrBursts::10 18253 # Per bank write bursts +system.physmem.perBankWrBursts::11 18685 # Per bank write bursts +system.physmem.perBankWrBursts::12 18794 # Per bank write bursts +system.physmem.perBankWrBursts::13 18180 # Per bank write bursts +system.physmem.perBankWrBursts::14 18427 # Per bank write bursts +system.physmem.perBankWrBursts::15 18358 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 236023635500 # Total gap between requests +system.physmem.totGap 235850076500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 430392 # Read request sizes (log2) +system.physmem.readPktSize::6 430611 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 291097 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 318668 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60537 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6198 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 10 # What read queue length does an incoming req see +system.physmem.writePktSize::6 291460 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 318665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4311 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3288 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,37 +149,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 12073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 14859 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17602 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 18085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 18518 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18609 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 12035 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 14838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 18906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -198,127 +198,123 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 328591 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 140.009775 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 98.675291 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 178.430270 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 209431 63.74% 63.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 79588 24.22% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14900 4.53% 92.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7308 2.22% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4939 1.50% 96.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2586 0.79% 97.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1820 0.55% 97.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1543 0.47% 98.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6476 1.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 328591 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17028 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.118628 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 145.022717 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17026 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 329170 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 139.885214 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 98.537517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 178.782393 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 329170 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17054 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.096224 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 145.074041 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17028 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17028 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.093199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.022957 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.821852 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 10045 58.99% 58.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 6192 36.36% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 538 3.16% 98.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 158 0.93% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 50 0.29% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 18 0.11% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 8 0.05% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 3 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 4 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::50-51 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-53 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::90-91 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-93 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17028 # Writes before turning the bus around for reads -system.physmem.totQLat 14230918095 # Total ticks spent queuing -system.physmem.totMemAccLat 22252299345 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2139035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33264.81 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17054 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.088542 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.022727 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.689258 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17054 # Writes before turning the bus around for reads +system.physmem.totQLat 14249250266 # Total ticks spent queuing +system.physmem.totMemAccLat 22275506516 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2140335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33287.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52014.81 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 78.92 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 116.70 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 78.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52037.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 116.16 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 79.08 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 116.85 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 79.09 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.52 # Data bus utilization in percentage +system.physmem.busUtil 1.53 # Data bus utilization in percentage system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing -system.physmem.readRowHits 308090 # Number of row buffer hits during reads -system.physmem.writeRowHits 82180 # Number of row buffer hits during writes -system.physmem.readRowHitRate 72.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 28.23 # Row buffer hit rate for writes -system.physmem.avgGap 327134.07 # Average gap between requests -system.physmem.pageHitRate 54.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1195143180 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 635214690 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1572477900 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 757698660 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15717574080.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 13455213090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 610838880 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 46153778370 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17481507840 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 15586959435 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 113172096165 # Total energy per rank (pJ) -system.physmem_0.averagePower 479.494648 # Core power per rank (mW) -system.physmem_0.totalIdleTime 204913310074 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 902504711 # Time in different power states -system.physmem_0.memoryStateTime::REF 6666906000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 58174043250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 45524259021 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23540851965 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 101215123053 # Time in different power states -system.physmem_1.actEnergy 1151060820 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 611788155 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1482064080 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 761650200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15007050240.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 13420176330 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 597461760 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 42655727700 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16961144160 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 17790500985 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 110444200560 # Total energy per rank (pJ) -system.physmem_1.averagePower 467.936931 # Core power per rank (mW) -system.physmem_1.totalIdleTime 205025277615 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 898721445 # Time in different power states -system.physmem_1.memoryStateTime::REF 6366412000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67312288506 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 44168958563 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23733276940 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 93544030546 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174594111 # Number of BP lookups -system.cpu.branchPred.condPredicted 131059017 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7233933 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90232346 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78999638 # Number of BTB hits +system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing +system.physmem.readRowHits 308139 # Number of row buffer hits during reads +system.physmem.writeRowHits 82177 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.98 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 28.20 # Row buffer hit rate for writes +system.physmem.avgGap 326630.04 # Average gap between requests +system.physmem.pageHitRate 54.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1195207440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 635245050 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1570792860 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 757087920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15735398640.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 13510945980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 615046560 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 46117601610 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 17430135360 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 15587831640 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 113161874670 # Total energy per rank (pJ) +system.physmem_0.averagePower 479.804155 # Core power per rank (mW) +system.physmem_0.totalIdleTime 204603400415 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 912794276 # Time in different power states +system.physmem_0.memoryStateTime::REF 6674692000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 58078463500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 45390268663 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23659127059 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 101134783502 # Time in different power states +system.physmem_1.actEnergy 1155130620 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 613955100 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1485605520 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 764166240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15039011520.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13474802850 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 604322400 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 42537889890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 17081497440 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 17718944700 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 110481339780 # Total energy per rank (pJ) +system.physmem_1.averagePower 468.438739 # Core power per rank (mW) +system.physmem_1.totalIdleTime 204713337667 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 914400899 # Time in different power states +system.physmem_1.memoryStateTime::REF 6380142000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 66945121250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 44482448304 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23842248434 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 93285768113 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 174426540 # Number of BP lookups +system.cpu.branchPred.condPredicted 130958868 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7258964 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 89936054 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78903188 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.551351 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106114 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104453 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 4688512 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 4673325 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 15187 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 53879 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 87.732544 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12071651 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104612 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 4685817 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 4672093 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 13724 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -348,7 +344,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -378,7 +374,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -408,7 +404,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -439,134 +435,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 472047377 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 471700259 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7665841 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 727531021 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174594111 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95779077 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 455980909 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14521279 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 6370 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 74 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 14846 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 235277273 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 36996 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 470928679 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.672614 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.189870 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7689412 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 726848478 # Number of instructions fetch has processed +system.cpu.fetch.Branches 174426540 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95646932 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 455559849 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14571167 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 7088 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 169 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 15067 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 235109896 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 36736 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 470557168 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.672087 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.189865 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 101212688 21.49% 21.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132055507 28.04% 49.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57355152 12.18% 61.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 180305332 38.29% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 470928679 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.369866 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.541225 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32549304 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 125870927 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 282926168 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22809881 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6772399 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 23857268 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495900 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 710989368 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29087460 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6772399 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63357486 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61253040 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40466365 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 273530421 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 25548968 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 682720764 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 12849971 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 10025216 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2519363 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1823930 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2318589 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 827514324 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3000521547 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 718647704 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 470557168 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.369783 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.540912 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32637512 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 125886415 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 282414401 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22855437 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6763403 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 71909343 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 530427 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 710086582 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29127059 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6763403 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63488458 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61155779 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40463668 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 273022741 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 25663119 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 681926435 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 12775010 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 10060236 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2531231 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1813266 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2373970 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 826391408 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2997146717 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 717894841 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 173418650 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1545803 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1536177 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 43812625 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 142363196 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67528532 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12884136 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11268568 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 664776091 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2979332 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 608934070 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5749195 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 120407268 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 306545068 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1700 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 470928679 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.293049 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.104484 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 172295734 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1545774 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1536126 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 43961162 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 142203026 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67513624 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12913434 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11193544 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 664083030 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2979301 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 608560988 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5743597 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119714176 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 304959820 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1669 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 470557168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.293277 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.104886 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 154505965 32.81% 32.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100895056 21.42% 54.23% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 145511490 30.90% 85.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63049261 13.39% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6966284 1.48% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 623 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 470928679 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 470557168 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71893204 53.11% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 30 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 53.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44308845 32.73% 85.84% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19163928 14.16% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 14 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 412595854 67.76% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 352107 0.06% 67.81% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued @@ -596,84 +592,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 133581364 21.94% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62404700 10.25% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 26 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 608934070 # Type of FU issued -system.cpu.iq.rate 1.289985 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135366043 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.222300 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1829911935 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 788191546 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594211471 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 100 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 608560988 # Type of FU issued +system.cpu.iq.rate 1.290143 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135463169 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222596 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1828885813 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 786805257 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 97 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 744300035 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 78 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7286788 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 744024094 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 7272380 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 26479913 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 24891 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29414 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10668312 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 26319743 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24134 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29234 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10653404 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 225406 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 23080 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 224604 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 23301 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6772399 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 23806628 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 967662 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 669248404 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6763403 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23756716 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 981361 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 668554311 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 142363196 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67528532 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1490790 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 256473 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 573815 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29414 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3591193 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3742987 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7334180 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 598436406 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129089013 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10497664 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 142203026 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67513624 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1490759 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 256987 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 586437 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29234 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3560929 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3767464 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7328393 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 598121332 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 128978812 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10439656 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1492981 # number of nop insts executed -system.cpu.iew.exec_refs 190011710 # number of memory reference insts executed -system.cpu.iew.exec_branches 131264327 # Number of branches executed -system.cpu.iew.exec_stores 60922697 # Number of stores executed -system.cpu.iew.exec_rate 1.267746 # Inst execution rate -system.cpu.iew.wb_sent 595457934 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594211487 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349573647 # num instructions producing a value -system.cpu.iew.wb_consumers 571370339 # num instructions consuming a value -system.cpu.iew.wb_rate 1.258796 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.611816 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 107140247 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1491980 # number of nop insts executed +system.cpu.iew.exec_refs 189925083 # number of memory reference insts executed +system.cpu.iew.exec_branches 131214447 # Number of branches executed +system.cpu.iew.exec_stores 60946271 # Number of stores executed +system.cpu.iew.exec_rate 1.268011 # Inst execution rate +system.cpu.iew.wb_sent 595160432 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 593918729 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349300209 # num instructions producing a value +system.cpu.iew.wb_consumers 571006140 # num instructions consuming a value +system.cpu.iew.wb_rate 1.259102 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 106531473 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6745693 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 454265599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.207866 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.884244 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6736784 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 453954004 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.208695 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.885174 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 225450125 49.63% 49.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116407668 25.63% 75.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43488632 9.57% 84.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23202465 5.11% 89.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 11495162 2.53% 92.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7755603 1.71% 94.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8270201 1.82% 95.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4246101 0.93% 96.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13949642 3.07% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 454265599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 453954004 # Number of insts commited each cycle system.cpu.commit.committedInsts 506578818 # Number of instructions committed system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -723,560 +719,558 @@ system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction -system.cpu.commit.bw_lim_events 13949642 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1096141105 # The number of ROB reads -system.cpu.rob.rob_writes 1328357052 # The number of ROB writes -system.cpu.timesIdled 14656 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1118698 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 13948036 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1095222342 # The number of ROB reads +system.cpu.rob.rob_writes 1327086117 # The number of ROB writes +system.cpu.timesIdled 14782 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1143091 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505234934 # Number of Instructions Simulated system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.934313 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.934313 # CPI: Total CPI of All Threads -system.cpu.ipc 1.070306 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.070306 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 610147261 # number of integer regfile reads -system.cpu.int_regfile_writes 327343686 # number of integer regfile writes +system.cpu.cpi 0.933626 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.933626 # CPI: Total CPI of All Threads +system.cpu.ipc 1.071093 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.071093 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 609897818 # number of integer regfile reads +system.cpu.int_regfile_writes 327085541 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2166295309 # number of cc regfile reads -system.cpu.cc_regfile_writes 376541599 # number of cc regfile writes -system.cpu.misc_regfile_reads 217608578 # number of misc regfile reads +system.cpu.cc_regfile_reads 2165040622 # number of cc regfile reads +system.cpu.cc_regfile_writes 376344417 # number of cc regfile writes +system.cpu.misc_regfile_reads 217537377 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2817163 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.628180 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168869146 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2817675 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 59.932088 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 504794000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.628180 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999274 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999274 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2817480 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.627959 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168773991 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2817992 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 59.891579 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 504701000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 355269881 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 355269881 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 114167630 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114167630 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51721570 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51721570 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2787 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2787 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 355076080 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 355076080 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 114071383 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114071383 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51722665 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51722665 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2778 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 165889200 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 165889200 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 165891987 # number of overall hits -system.cpu.dcache.overall_hits::total 165891987 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4839460 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4839460 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2517479 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2517479 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7356939 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7356939 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7356950 # number of overall misses -system.cpu.dcache.overall_misses::total 7356950 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63959252000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63959252000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19900951428 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19900951428 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1024000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1024000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83860203428 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83860203428 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83860203428 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83860203428 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119007090 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119007090 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 165794048 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 165794048 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 165796826 # number of overall hits +system.cpu.dcache.overall_hits::total 165796826 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4838662 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4838662 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2516384 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2516384 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 65 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 7355046 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7355046 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7355056 # number of overall misses +system.cpu.dcache.overall_misses::total 7355056 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 63735397500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19938555937 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 83673953437 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 83673953437 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 118910045 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2798 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2798 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2788 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488621 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173246139 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173246139 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173248937 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173248937 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040665 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040665 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046415 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046415 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003931 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003931 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173149094 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173149094 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173151882 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173151882 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040692 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046394 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.042465 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.042465 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.042465 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.042465 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13216.196022 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13216.196022 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7905.111196 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7905.111196 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15515.151515 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15515.151515 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 11398.790098 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 11398.790098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 11398.773055 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 11398.773055 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1096029 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042478 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042477 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1100252 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 221098 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 4.957209 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2817163 # number of writebacks -system.cpu.dcache.writebacks::total 2817163 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2541567 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2541567 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1997678 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1997678 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4539245 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4539245 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4539245 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4539245 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2297893 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2297893 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519801 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519801 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2817694 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2817694 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2817704 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2817704 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32776399000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 32776399000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4786328496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4786328496 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1261500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1261500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37562727496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37562727496 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37563988996 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37563988996 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019309 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009584 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003574 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003574 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016264 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016264 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14263.675028 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14263.675028 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9208.001708 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9208.001708 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 126150 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 126150 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13331.017313 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 13331.017313 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13331.417706 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 13331.417706 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 76621 # number of replacements -system.cpu.icache.tags.tagsinuse 466.068009 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 235191085 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 77133 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3049.162939 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 116620130500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 466.068009 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.910289 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.910289 # Average percentage of cache occupancy +system.cpu.dcache.blocked::no_targets 221126 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2817480 # number of writebacks +system.cpu.dcache.writebacks::total 2817480 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2540507 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1996523 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4537030 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4537030 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2298155 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519861 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2818016 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2818025 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 # 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Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 470631453 # Number of tag accesses -system.cpu.icache.tags.data_accesses 470631453 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 235191085 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 235191085 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 235191085 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 235191085 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 235191085 # number of overall hits -system.cpu.icache.overall_hits::total 235191085 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 86061 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 86061 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 86061 # 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number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 235277146 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 235277146 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 235277146 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 470296624 # Number of tag accesses +system.cpu.icache.tags.data_accesses 470296624 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 235023805 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 235023805 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 235023805 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 235023805 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 235023805 # number of overall hits +system.cpu.icache.overall_hits::total 235023805 # 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number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 235109772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 235109772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 235109772 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 235109772 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 235109772 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 235109772 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # 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average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22737.250305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22737.250305 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 201943 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7203 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 28.293703 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 191.375000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 76621 # number of writebacks -system.cpu.icache.writebacks::total 76621 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8898 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8898 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8898 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8898 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8898 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8898 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77163 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 77163 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 77163 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 77163 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 77163 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 77163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1533201777 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1533201777 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1533201777 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1533201777 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1533201777 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1533201777 # number of overall MSHR miss cycles +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 76537 # number of writebacks +system.cpu.icache.writebacks::total 76537 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 8885 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 8885 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 8885 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 8885 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 8885 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 77082 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 77082 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 77082 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 77082 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 77082 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1551815800 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1551815800 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19869.649664 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19869.649664 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19869.649664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19869.649664 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 8513489 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8514918 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 429 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 8513754 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8515198 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 454 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 744218 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 389920 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15006.987953 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2697445 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 405523 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.651768 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 744250 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 390446 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15006.522104 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2698185 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 406039 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.645138 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14934.817227 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 72.170726 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.911549 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004405 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.915954 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 103 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15500 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 35 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 249 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 665 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5454 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6553 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2579 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.006287 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.946045 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 95362177 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 95362177 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 2356317 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 2356317 # 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number of writebacks +system.cpu.l2cache.writebacks::total 291460 # number of writebacks +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1597 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1597 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4534 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4534 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 6131 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 6142 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 6131 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 6142 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 356126 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 356126 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 33 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3684 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3684 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10176 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10176 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 160345 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 160345 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10176 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 164029 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174205 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10176 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 164029 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 356126 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 530331 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 21400232213 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 517000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 517000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 462922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 462922500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 973097500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 973097500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007060 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.129820 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069927 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069927 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060186 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.129820 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058280 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.183107 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 59945.212612 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15568.965517 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15568.965517 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 127356.309362 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 127356.309362 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95312.144213 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95312.144213 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87186.572603 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87186.572603 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88503.162523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95312.144213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88087.985263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 59945.212612 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69332.064095 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5788651 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2893810 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26608 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 99788 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99240 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 548 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2372852 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2647414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 537467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 98823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 402669 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2373057 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 543587 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 98986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 403295 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 29 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521984 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 77163 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295691 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230912 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8452572 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8683484 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9839936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360629696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 370469632 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 792623 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 18632384 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 3687456 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.034433 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.183151 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 522015 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 522015 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8684194 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 370499456 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 793778 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 18655808 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 3688848 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.034290 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3561035 96.57% 96.57% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 125873 3.41% 99.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 548 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3687456 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5788109505 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3688848 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 115773436 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 115655928 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4226542968 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4227026456 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 820344 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 413808 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 821093 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 414041 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 236023688000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 426709 # Transaction distribution -system.membus.trans_dist::WritebackDirty 291097 # Transaction distribution -system.membus.trans_dist::CleanEvict 98823 # Transaction distribution -system.membus.trans_dist::UpgradeReq 32 # Transaction distribution -system.membus.trans_dist::ReadExReq 3682 # Transaction distribution -system.membus.trans_dist::ReadExResp 3682 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 426710 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1250735 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1250735 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46175232 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 46175232 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 426929 # Transaction distribution +system.membus.trans_dist::WritebackDirty 291460 # Transaction distribution +system.membus.trans_dist::CleanEvict 98986 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36 # Transaction distribution +system.membus.trans_dist::ReadExReq 3681 # Transaction distribution +system.membus.trans_dist::ReadExResp 3681 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 426930 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1251703 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 46212480 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 430424 # Request fanout histogram +system.membus.snoop_fanout::samples 430647 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430424 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430647 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430424 # Request fanout histogram -system.membus.reqLayer0.occupancy 2210945378 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 430647 # Request fanout histogram +system.membus.reqLayer0.occupancy 2213026745 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2277916539 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2279181090 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index 1d6cdc3c5..eaf30dab2 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.487172 # Number of seconds simulated -sim_ticks 487172057000 # Number of ticks simulated -final_tick 487172057000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.487051 # Number of seconds simulated +sim_ticks 487050729500 # Number of ticks simulated +final_tick 487050729500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 151495 # Simulator instruction rate (inst/s) -host_op_rate 280342 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89259825 # Simulator tick rate (ticks/s) -host_mem_usage 322228 # Number of bytes of host memory used -host_seconds 5457.91 # Real time elapsed on the host +host_inst_rate 151835 # Simulator instruction rate (inst/s) +host_op_rate 280970 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89437473 # Simulator tick rate (ticks/s) +host_mem_usage 318556 # Number of bytes of host memory used +host_seconds 5445.71 # Real time elapsed on the host sim_insts 826847303 # Number of instructions simulated sim_ops 1530082520 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 155008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24650432 # Number of bytes read from this memory -system.physmem.bytes_read::total 24805440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 155008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 155008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18909504 # Number of bytes written to this memory -system.physmem.bytes_written::total 18909504 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2422 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 385163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 387585 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 295461 # Number of write requests responded to by this memory -system.physmem.num_writes::total 295461 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 318179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 50599027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50917206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 318179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 38814837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 38814837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 38814837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 318179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 50599027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 89732043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 387585 # Number of read requests accepted -system.physmem.writeReqs 295461 # Number of write requests accepted -system.physmem.readBursts 387585 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 295461 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24785280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 20160 # Total number of bytes read from write queue -system.physmem.bytesWritten 18907584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24805440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18909504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 315 # Number of DRAM read bursts serviced by the write queue +system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 156352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24658560 # Number of bytes read from this memory +system.physmem.bytes_read::total 24814912 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 156352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 156352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory +system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 385290 # Number of read requests responded to by this memory +system.physmem.num_reads::total 387733 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory +system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 321018 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 50628320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50949338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 321018 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 321018 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 38828448 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 38828448 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 38828448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 321018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50628320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 89777786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 387733 # Number of read requests accepted +system.physmem.writeReqs 295491 # Number of write requests accepted +system.physmem.readBursts 387733 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24795072 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue +system.physmem.bytesWritten 18909504 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24814912 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24645 # Per bank write bursts -system.physmem.perBankRdBursts::1 26417 # Per bank write bursts -system.physmem.perBankRdBursts::2 24674 # Per bank write bursts -system.physmem.perBankRdBursts::3 24501 # Per bank write bursts -system.physmem.perBankRdBursts::4 23296 # Per bank write bursts -system.physmem.perBankRdBursts::5 23619 # Per bank write bursts -system.physmem.perBankRdBursts::6 24746 # Per bank write bursts -system.physmem.perBankRdBursts::7 24503 # Per bank write bursts -system.physmem.perBankRdBursts::8 23866 # Per bank write bursts -system.physmem.perBankRdBursts::9 23595 # Per bank write bursts -system.physmem.perBankRdBursts::10 24803 # Per bank write bursts -system.physmem.perBankRdBursts::11 23982 # Per bank write bursts -system.physmem.perBankRdBursts::12 23298 # Per bank write bursts -system.physmem.perBankRdBursts::13 23005 # Per bank write bursts -system.physmem.perBankRdBursts::14 24008 # Per bank write bursts -system.physmem.perBankRdBursts::15 24312 # Per bank write bursts -system.physmem.perBankWrBursts::0 19007 # Per bank write bursts -system.physmem.perBankWrBursts::1 19956 # Per bank write bursts -system.physmem.perBankWrBursts::2 19034 # Per bank write bursts -system.physmem.perBankWrBursts::3 18984 # Per bank write bursts -system.physmem.perBankWrBursts::4 18157 # Per bank write bursts -system.physmem.perBankWrBursts::5 18431 # Per bank write bursts -system.physmem.perBankWrBursts::6 19162 # Per bank write bursts -system.physmem.perBankWrBursts::7 19114 # Per bank write bursts -system.physmem.perBankWrBursts::8 18737 # Per bank write bursts -system.physmem.perBankWrBursts::9 17973 # Per bank write bursts -system.physmem.perBankWrBursts::10 18902 # Per bank write bursts -system.physmem.perBankWrBursts::11 17777 # Per bank write bursts -system.physmem.perBankWrBursts::12 17406 # Per bank write bursts -system.physmem.perBankWrBursts::13 16997 # Per bank write bursts -system.physmem.perBankWrBursts::14 17829 # Per bank write bursts +system.physmem.perBankRdBursts::0 24612 # Per bank write bursts +system.physmem.perBankRdBursts::1 26389 # Per bank write bursts +system.physmem.perBankRdBursts::2 24828 # Per bank write bursts +system.physmem.perBankRdBursts::3 24571 # Per bank write bursts +system.physmem.perBankRdBursts::4 23534 # Per bank write bursts +system.physmem.perBankRdBursts::5 23661 # Per bank write bursts +system.physmem.perBankRdBursts::6 24754 # Per bank write bursts +system.physmem.perBankRdBursts::7 24509 # Per bank write bursts +system.physmem.perBankRdBursts::8 23888 # Per bank write bursts +system.physmem.perBankRdBursts::9 23557 # Per bank write bursts +system.physmem.perBankRdBursts::10 24834 # Per bank write bursts +system.physmem.perBankRdBursts::11 24002 # Per bank write bursts +system.physmem.perBankRdBursts::12 23243 # Per bank write bursts +system.physmem.perBankRdBursts::13 22894 # Per bank write bursts +system.physmem.perBankRdBursts::14 23905 # Per bank write bursts +system.physmem.perBankRdBursts::15 24242 # Per bank write bursts +system.physmem.perBankWrBursts::0 18972 # Per bank write bursts +system.physmem.perBankWrBursts::1 19954 # Per bank write bursts +system.physmem.perBankWrBursts::2 19038 # Per bank write bursts +system.physmem.perBankWrBursts::3 19006 # Per bank write bursts +system.physmem.perBankWrBursts::4 18208 # Per bank write bursts +system.physmem.perBankWrBursts::5 18444 # Per bank write bursts +system.physmem.perBankWrBursts::6 19174 # Per bank write bursts +system.physmem.perBankWrBursts::7 19116 # Per bank write bursts +system.physmem.perBankWrBursts::8 18744 # Per bank write bursts +system.physmem.perBankWrBursts::9 17955 # Per bank write bursts +system.physmem.perBankWrBursts::10 18923 # Per bank write bursts +system.physmem.perBankWrBursts::11 17774 # Per bank write bursts +system.physmem.perBankWrBursts::12 17399 # Per bank write bursts +system.physmem.perBankWrBursts::13 16985 # Per bank write bursts +system.physmem.perBankWrBursts::14 17804 # Per bank write bursts system.physmem.perBankWrBursts::15 17965 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 487171969500 # Total gap between requests +system.physmem.totGap 487050613500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 387585 # Read request sizes (log2) +system.physmem.readPktSize::6 387733 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 295461 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 5721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 295491 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381263 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 5754 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,27 +145,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17686 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17703 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17705 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -194,360 +194,362 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 146660 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 297.911141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.290070 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.324639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53183 36.26% 36.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40977 27.94% 64.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13739 9.37% 73.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7432 5.07% 78.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5223 3.56% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3827 2.61% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2941 2.01% 86.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2699 1.84% 88.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16639 11.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 146660 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17684 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.898835 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 18.149529 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 215.763207 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17677 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 3 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 146416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.484100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 176.719176 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.748192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52816 36.07% 36.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41066 28.05% 64.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13865 9.47% 73.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7498 5.12% 78.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4985 3.40% 82.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3806 2.60% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2894 1.98% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2818 1.92% 88.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16668 11.38% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 146416 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17678 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.914866 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 18.161180 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 216.039339 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17672 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17684 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.706119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.679236 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.959383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 11362 64.25% 64.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 284 1.61% 65.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5921 33.48% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 108 0.61% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 8 0.05% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17684 # Writes before turning the bus around for reads -system.physmem.totQLat 9753002000 # Total ticks spent queuing -system.physmem.totMemAccLat 17014314500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1936350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25183.99 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 17678 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17678 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.713486 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.686282 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.965426 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 11315 64.01% 64.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 269 1.52% 65.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5957 33.70% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 123 0.70% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 10 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17678 # Writes before turning the bus around for reads +system.physmem.totQLat 9794922250 # Total ticks spent queuing +system.physmem.totMemAccLat 17059103500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1937115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25282.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43933.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 50.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 38.81 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 38.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44032.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 50.91 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.95 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 38.83 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.70 # Data bus utilization in percentage system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.76 # Average write queue length when enqueuing -system.physmem.readRowHits 316112 # Number of row buffer hits during reads -system.physmem.writeRowHits 219918 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.43 # Row buffer hit rate for writes -system.physmem.avgGap 713234.50 # Average gap between requests -system.physmem.pageHitRate 78.51 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 536813760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 285300510 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1402303140 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 792630900 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 13522080000.000004 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8880806910 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 733930560 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 36188602890 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 17013808320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 84109110615 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 163471886265 # Total energy per rank (pJ) -system.physmem_0.averagePower 335.552673 # Core power per rank (mW) -system.physmem_0.totalIdleTime 465770843500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1167963000 # Time in different power states -system.physmem_0.memoryStateTime::REF 5742590000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 342103131000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 44306910500 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14490068000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 79361394500 # Time in different power states -system.physmem_1.actEnergy 510417180 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 271274190 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1362804660 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 749518920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 13134242160.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8898960840 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 723582720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 34400258100 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 16618152960 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 85296284295 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 161971426545 # Total energy per rank (pJ) -system.physmem_1.averagePower 332.472734 # Core power per rank (mW) -system.physmem_1.totalIdleTime 465759347500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1160536750 # Time in different power states -system.physmem_1.memoryStateTime::REF 5578620000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 347043695250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 43276363250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14673424500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 75439417250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 297986094 # Number of BP lookups -system.cpu.branchPred.condPredicted 297986094 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 23626998 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 229902551 # Number of BTB lookups +system.physmem.avgWrQLen 20.96 # Average write queue length when enqueuing +system.physmem.readRowHits 316322 # Number of row buffer hits during reads +system.physmem.writeRowHits 220133 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.50 # Row buffer hit rate for writes +system.physmem.avgGap 712871.05 # Average gap between requests +system.physmem.pageHitRate 78.55 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 538191780 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 286032945 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1405566120 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 792980640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 13571251200.000004 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8851881120 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 742850400 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 36305173020 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 16998972000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 84070895340 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 163568832135 # Total energy per rank (pJ) +system.physmem_0.averagePower 335.835307 # Core power per rank (mW) +system.physmem_0.totalIdleTime 465691902250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1184996500 # Time in different power states +system.physmem_0.memoryStateTime::REF 5763492000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 341808238000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 44268234250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14409717250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 79616051500 # Time in different power states +system.physmem_1.actEnergy 507311280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 269615775 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1360634100 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 749325780 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 13094905200.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8819547870 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 717418080 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 34208424030 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 16648938720 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 85396744800 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 161777173725 # Total energy per rank (pJ) +system.physmem_1.averagePower 332.156722 # Core power per rank (mW) +system.physmem_1.totalIdleTime 465831856000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1145526000 # Time in different power states +system.physmem_1.memoryStateTime::REF 5561926000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 347456670000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 43356567250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14511269750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 75018770500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 299198029 # Number of BP lookups +system.cpu.branchPred.condPredicted 299198029 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 24258277 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 226066805 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 40347150 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4410395 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 229902551 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 119869207 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 110033344 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 11602477 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 40193400 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4437789 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 226066805 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 118144411 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 107922394 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 11883156 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 974344115 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 974101460 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 229691872 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1587782946 # Number of instructions fetch has processed -system.cpu.fetch.Branches 297986094 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 160216357 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 719926348 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 48165553 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1415 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 32240 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 400644 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 8846 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 32 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 216441049 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6311436 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 974144173 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.051993 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.490984 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 230169557 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1594277830 # Number of instructions fetch has processed +system.cpu.fetch.Branches 299198029 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 158337811 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718471067 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 49469999 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 2698 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 34945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 480096 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 4714 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 216546560 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6526632 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 973898145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.063667 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.497102 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 482346160 49.51% 49.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 36602331 3.76% 53.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 36258722 3.72% 56.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33122325 3.40% 60.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 28552285 2.93% 63.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 29954375 3.07% 66.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 40147511 4.12% 70.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 37554957 3.86% 74.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 249605507 25.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 481357803 49.43% 49.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 36544666 3.75% 53.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 36285723 3.73% 56.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 32866211 3.37% 60.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 28367371 2.91% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 29577354 3.04% 66.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39843150 4.09% 70.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36876934 3.79% 74.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 252178933 25.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 974144173 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.305832 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.629592 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 165741449 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 390914156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 312062305 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 81343487 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 24082776 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2744526803 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 24082776 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 201646050 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 200648481 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15573 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 351553209 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 196198084 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2627040726 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 843366 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 120856771 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 22890286 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 43959941 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2707701926 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6592856104 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4207544155 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 2527327 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 973898145 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.307153 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.636665 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 166490369 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 388298779 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 313723542 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80650456 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 24734999 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2751923456 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 24734999 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 202899221 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 199700520 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14210 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 351959746 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 194589449 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2631585273 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 503822 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 119585114 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 21729790 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 44646970 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2710512651 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6600728549 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4213051781 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1976674 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1090740354 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1231 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1132 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 368340883 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 608352131 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 244132697 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 253219333 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 76661135 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2419790234 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 118502 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1999387601 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3615961 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 889826216 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1510217601 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 117950 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 974144173 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.052456 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.105356 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1093551079 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 884 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 794 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 367177164 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 608809294 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 243550763 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 252688912 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 75518257 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2418516015 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 104540 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1999668107 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3656750 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 888538035 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1505526254 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 103988 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 973898145 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.053262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.107501 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 345565196 35.47% 35.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 135254480 13.88% 49.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 130135429 13.36% 62.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 118774957 12.19% 74.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 97965180 10.06% 84.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 67350848 6.91% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 45621638 4.68% 96.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 22618956 2.32% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 10857489 1.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 345655298 35.49% 35.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 135232191 13.89% 49.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 129689064 13.32% 62.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 119012847 12.22% 74.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 97852872 10.05% 84.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 66913699 6.87% 91.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 45825912 4.71% 96.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 22646304 2.33% 98.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 11069958 1.14% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 974144173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 973898145 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11247867 43.19% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11962828 45.93% 89.12% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2737897 10.51% 99.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 96082 0.37% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11137608 43.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11929198 46.06% 89.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2740827 10.58% 99.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 92541 0.36% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2913186 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1333691578 66.71% 66.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 358355 0.02% 66.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 4798525 0.24% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 471253849 23.57% 90.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 185928557 9.30% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 5 0.00% 99.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 443541 0.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2900375 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1333719780 66.70% 66.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 357536 0.02% 66.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 4798411 0.24% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 471767183 23.59% 90.69% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 185670018 9.29% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 6 0.00% 99.98% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 454793 0.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1999387601 # Type of FU issued -system.cpu.iq.rate 2.052034 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26044674 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013026 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5001332322 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 3306265401 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1924007332 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1247688 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4044576 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 235696 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2021979456 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 539633 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 179731986 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1999668107 # Type of FU issued +system.cpu.iq.rate 2.052833 # Inst issue rate +system.cpu.iq.fu_busy_cnt 25900174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012952 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5001578236 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3304560217 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1922724831 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1213047 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 3212370 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 280288 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2022120560 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 547346 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 180407023 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 224269113 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 336817 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 641986 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 94974502 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 224726218 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 356451 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 693943 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 94392568 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 32014 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 878 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 33314 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 814 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 24082776 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 149888848 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 6862033 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2419908736 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1314714 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 608352426 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 244132697 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 41176 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1469227 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4543982 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 641986 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8726699 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 20674839 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 29401538 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1945912356 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 456814163 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 53475245 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 24734999 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149663879 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 6607902 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2418620555 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1417513 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 608809531 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 243550763 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 36150 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1478128 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4302509 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 693943 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8551096 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 21778410 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 30329506 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1944942401 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 457167604 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 54725706 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 635656680 # number of memory reference insts executed -system.cpu.iew.exec_branches 185192217 # Number of branches executed -system.cpu.iew.exec_stores 178842517 # Number of stores executed -system.cpu.iew.exec_rate 1.997151 # Inst execution rate -system.cpu.iew.wb_sent 1934768958 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1924243028 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1457137045 # num instructions producing a value -system.cpu.iew.wb_consumers 2204058928 # num instructions consuming a value -system.cpu.iew.wb_rate 1.974911 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.661115 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 889901292 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 635670117 # number of memory reference insts executed +system.cpu.iew.exec_branches 185387955 # Number of branches executed +system.cpu.iew.exec_stores 178502513 # Number of stores executed +system.cpu.iew.exec_rate 1.996653 # Inst execution rate +system.cpu.iew.wb_sent 1933639401 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1923005119 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1456045504 # num instructions producing a value +system.cpu.iew.wb_consumers 2200626785 # num instructions consuming a value +system.cpu.iew.wb_rate 1.974132 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.661650 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 888612801 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 23658010 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 841376599 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818547 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.459268 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 24293835 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 840170563 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.821157 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.461954 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 361645102 42.98% 42.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 184788916 21.96% 64.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57757386 6.86% 71.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 87297113 10.38% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 30407785 3.61% 85.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 26554015 3.16% 88.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10439709 1.24% 90.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 9044560 1.07% 91.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 73442013 8.73% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 361187525 42.99% 42.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 184077910 21.91% 64.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57677028 6.86% 71.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 87256558 10.39% 82.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 30345133 3.61% 85.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 26488854 3.15% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10500866 1.25% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9042630 1.08% 91.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 73594059 8.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 841376599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 840170563 # Number of insts commited each cycle system.cpu.commit.committedInsts 826847303 # Number of instructions committed system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -597,495 +599,494 @@ system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction -system.cpu.commit.bw_lim_events 73442013 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3187918398 # The number of ROB reads -system.cpu.rob.rob_writes 4974407602 # The number of ROB writes -system.cpu.timesIdled 2034 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 199942 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 73594059 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3185271825 # The number of ROB reads +system.cpu.rob.rob_writes 4972894886 # The number of ROB writes +system.cpu.timesIdled 2025 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 203315 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826847303 # Number of Instructions Simulated system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.178385 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.178385 # CPI: Total CPI of All Threads -system.cpu.ipc 0.848619 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.848619 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2928729782 # number of integer regfile reads -system.cpu.int_regfile_writes 1576941499 # number of integer regfile writes -system.cpu.fp_regfile_reads 236699 # number of floating regfile reads -system.cpu.fp_regfile_writes 4 # number of floating regfile writes -system.cpu.cc_regfile_reads 617876716 # number of cc regfile reads -system.cpu.cc_regfile_writes 419949697 # number of cc regfile writes -system.cpu.misc_regfile_reads 1064375270 # number of misc regfile reads +system.cpu.cpi 1.178091 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.178091 # CPI: Total CPI of All Threads +system.cpu.ipc 0.848831 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.848831 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2927263565 # number of integer regfile reads +system.cpu.int_regfile_writes 1575987355 # number of integer regfile writes +system.cpu.fp_regfile_reads 281295 # number of floating regfile reads +system.cpu.fp_regfile_writes 5 # number of floating regfile writes +system.cpu.cc_regfile_reads 617980900 # number of cc regfile reads +system.cpu.cc_regfile_writes 419571241 # number of cc regfile writes +system.cpu.misc_regfile_reads 1064489388 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2546054 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.989792 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 421112007 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2550150 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.132250 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1890456500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.989792 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998044 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998044 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2545571 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.077195 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 420813077 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2549667 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.046289 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1863239500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.077195 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998066 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998066 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3458 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 606 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3449 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 851486020 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 851486020 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 272742549 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 272742549 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148366794 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148366794 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 421109343 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 421109343 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 421109343 # number of overall hits -system.cpu.dcache.overall_hits::total 421109343 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2567175 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2567175 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791417 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791417 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3358592 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3358592 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3358592 # number of overall misses -system.cpu.dcache.overall_misses::total 3358592 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 63549852500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 63549852500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26385909500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26385909500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 89935762000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 89935762000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 89935762000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 89935762000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 275309724 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 275309724 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 850870799 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 850870799 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 272443625 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 272443625 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148366897 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148366897 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 420810522 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 420810522 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 420810522 # number of overall hits +system.cpu.dcache.overall_hits::total 420810522 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2558730 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2558730 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791314 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791314 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3350044 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3350044 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3350044 # number of overall misses +system.cpu.dcache.overall_misses::total 3350044 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 62817542000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 62817542000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 26367570500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 26367570500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 89185112500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 89185112500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 89185112500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 89185112500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 275002355 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 275002355 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 424467935 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 424467935 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 424467935 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 424467935 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009325 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009325 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005306 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.007912 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.007912 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.007912 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.007912 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24754.780060 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24754.780060 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33340.084304 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33340.084304 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26777.817014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26777.817014 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26777.817014 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 12440 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10775 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 917 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.565976 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 769.642857 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2337949 # number of writebacks -system.cpu.dcache.writebacks::total 2337949 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 800910 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 800910 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5810 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 5810 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 806720 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 806720 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 806720 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 806720 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1766265 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1766265 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785607 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 785607 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2551872 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2551872 # 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number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006416 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006012 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006012 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21276.538911 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21276.538911 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32451.737319 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32451.737319 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24716.881568 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24716.881568 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 4004 # number of replacements -system.cpu.icache.tags.tagsinuse 1085.037164 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 216431030 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5719 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 37844.208778 # Average number of references to valid blocks. +system.cpu.dcache.demand_accesses::cpu.data 424160566 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 424160566 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 424160566 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 424160566 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009304 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.007898 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.007898 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.007898 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.007898 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24550.281585 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24550.281585 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33321.248581 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33321.248581 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26622.071979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26622.071979 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 9991 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 13057 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 901 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.088790 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 1004.384615 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 2337865 # number of writebacks +system.cpu.dcache.writebacks::total 2337865 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792851 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 792851 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5950 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 5950 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 798801 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 798801 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25475564000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 25475564000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63101626000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 63101626000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63101626000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 63101626000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005265 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21307.270770 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21307.270770 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.906499 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.906499 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 3942 # number of replacements +system.cpu.icache.tags.tagsinuse 1083.391017 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 216536709 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5668 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 38203.371383 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1085.037164 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.529803 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.529803 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1715 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1083.391017 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.529000 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.529000 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1726 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1557 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.837402 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 432889551 # Number of tag accesses -system.cpu.icache.tags.data_accesses 432889551 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 216431266 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 216431266 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 216431266 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 216431266 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 216431266 # number of overall hits -system.cpu.icache.overall_hits::total 216431266 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 9783 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 9783 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 9783 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 9783 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 9783 # number of overall misses -system.cpu.icache.overall_misses::total 9783 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 586259000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 586259000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 586259000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 586259000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 586259000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 586259000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 216441049 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 216441049 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 216441049 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 216441049 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 216441049 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 216441049 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 80 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.842773 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 433100363 # Number of tag accesses +system.cpu.icache.tags.data_accesses 433100363 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 216536917 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 216536917 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 216536917 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 216536917 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 216536917 # number of overall hits +system.cpu.icache.overall_hits::total 216536917 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 9643 # number of overall misses +system.cpu.icache.overall_misses::total 9643 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 597021000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 597021000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 597021000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 597021000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 597021000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 597021000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 216546560 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 216546560 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 216546560 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 216546560 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 216546560 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 216546560 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000045 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000045 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59926.300726 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 59926.300726 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 59926.300726 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 59926.300726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 59926.300726 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 59926.300726 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 654 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 486 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 65.400000 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 486 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 4004 # number of writebacks -system.cpu.icache.writebacks::total 4004 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2330 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2330 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2330 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2330 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2330 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2330 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 7453 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 7453 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 7453 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 7453 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 7453 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 7453 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 386965000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 386965000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 386965000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 386965000 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84606.357292 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84890.063109 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 5109383 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2550327 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23034 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 3629 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3621 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 8 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 1773498 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 2633410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4004 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 268667 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 1722 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 1722 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 784105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 784105 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 7453 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1766045 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17090 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7649798 # 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Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 3565 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3558 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 1772876 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2633356 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 3942 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 268356 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1576 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 784034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 784034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 7243 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765633 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7648057 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7664832 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 610048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312802048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 313412096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 357794 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 19017216 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2914627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.008154 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.089959 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2888424 99.08% 99.08% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 26916 0.92% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 8 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2890867 99.18% 99.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 23753 0.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2915348 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4896697394 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2914627 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4895855901 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 11180498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10867494 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3826086106 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3825288599 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 740706 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 353592 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 740964 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 353722 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 487172057000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 180821 # Transaction distribution -system.membus.trans_dist::WritebackDirty 295461 # Transaction distribution -system.membus.trans_dist::CleanEvict 57651 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 180910 # Transaction distribution +system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution +system.membus.trans_dist::CleanEvict 57731 # Transaction distribution system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 206764 # Transaction distribution -system.membus.trans_dist::ReadExResp 206764 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 180821 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128291 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128291 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1128291 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43714944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43714944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43714944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 206823 # Transaction distribution +system.membus.trans_dist::ReadExResp 206823 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 180910 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1128697 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43726336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43726336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43726336 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 387594 # Request fanout histogram +system.membus.snoop_fanout::samples 387742 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 387594 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 387742 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 387594 # Request fanout histogram -system.membus.reqLayer0.occupancy 1998981000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 387742 # Request fanout histogram +system.membus.reqLayer0.occupancy 1998138500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 2050982000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2051606500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index b2bc0dd63..812de15cb 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,43 +1,43 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.225207 # Number of seconds simulated -sim_ticks 225206521000 # Number of ticks simulated -final_tick 225206521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.225185 # Number of seconds simulated +sim_ticks 225184887000 # Number of ticks simulated +final_tick 225184887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 289736 # Simulator instruction rate (inst/s) -host_op_rate 347860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238979319 # Simulator tick rate (ticks/s) -host_mem_usage 279872 # Number of bytes of host memory used -host_seconds 942.37 # Real time elapsed on the host +host_inst_rate 292846 # Simulator instruction rate (inst/s) +host_op_rate 351594 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 241521552 # Simulator tick rate (ticks/s) +host_mem_usage 280036 # Number of bytes of host memory used +host_seconds 932.36 # Real time elapsed on the host sim_insts 273037855 # Number of instructions simulated sim_ops 327812212 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 219136 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266432 # Number of bytes read from this memory -system.physmem.bytes_read::total 485568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219136 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219136 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3424 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485504 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4163 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7587 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 973045 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1183056 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2156101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 973045 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 973045 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 973045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1183056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2156101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7587 # Number of read requests accepted +system.physmem.num_reads::total 7586 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 972854 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1183170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2156024 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 972854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 972854 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 972854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1183170 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2156024 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7586 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7587 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7586 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485568 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485504 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485568 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485504 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -57,7 +57,7 @@ system.physmem.perBankRdBursts::11 428 # Pe system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 705 # Per bank write bursts system.physmem.perBankRdBursts::14 639 # Per bank write bursts -system.physmem.perBankRdBursts::15 543 # Per bank write bursts +system.physmem.perBankRdBursts::15 542 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 225206267000 # Total gap between requests +system.physmem.totGap 225184633000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7587 # Read request sizes (log2) +system.physmem.readPktSize::6 7586 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,7 +91,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6690 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 845 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -187,26 +187,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1511 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 320.635341 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.281375 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 328.659938 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 540 35.74% 35.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 351 23.23% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 165 10.92% 69.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 80 5.29% 75.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 78 5.16% 80.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 55 3.64% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 33 2.18% 86.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 36 2.38% 88.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 173 11.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1511 # Bytes accessed per row activation -system.physmem.totQLat 232471000 # Total ticks spent queuing -system.physmem.totMemAccLat 374727250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37935000 # Total ticks spent in databus transfers -system.physmem.avgQLat 30640.70 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.017893 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.649066 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.624854 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 538 35.65% 35.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 351 23.26% 58.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 166 11.00% 69.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 79 5.24% 75.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 78 5.17% 80.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 56 3.71% 84.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 32 2.12% 86.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.39% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 173 11.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1509 # Bytes accessed per row activation +system.physmem.totQLat 232077250 # Total ticks spent queuing +system.physmem.totMemAccLat 374314750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30592.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 49390.70 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 49342.84 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.16 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.16 # Average system read bandwidth in MiByte/s @@ -217,66 +217,66 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6073 # Number of row buffer hits during reads +system.physmem.readRowHits 6074 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.04 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 29683177.41 # Average gap between requests -system.physmem.pageHitRate 80.04 # Row buffer hit rate, read and write combined +system.physmem.avgGap 29684238.47 # Average gap between requests +system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 4726680 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 2504700 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 27553260 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 284578320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 100446540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 15488640 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 721249500 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 385420800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 53424510300 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 54966478740 # Total energy per rank (pJ) -system.physmem_0.averagePower 244.071435 # Core power per rank (mW) -system.physmem_0.totalIdleTime 224945712750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 29370000 # Time in different power states +system.physmem_0.actBackEnergy 100520070 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 15505920 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 721291110 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 385301760 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 53419321200 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 54961303020 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.071899 # Core power per rank (mW) +system.physmem_0.totalIdleTime 224923904000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 29388000 # Time in different power states system.physmem_0.memoryStateTime::REF 121010000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 222360521000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1003708750 # Time in different power states -system.physmem_0.memoryStateTime::ACT 110211000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1581700250 # Time in different power states -system.physmem_1.actEnergy 6083280 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3229545 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 26617920 # Energy for read commands per rank (pJ) +system.physmem_0.memoryStateTime::SREF 222338897000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1003385750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 110367750 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1581838500 # Time in different power states +system.physmem_1.actEnergy 6069000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3221955 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 26610780 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 394598880.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 121237860 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 22348800 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 914380890 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 605052000 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 53195794545 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 55289408190 # Total energy per rank (pJ) -system.physmem_1.averagePower 245.505361 # Core power per rank (mW) -system.physmem_1.totalIdleTime 224881567000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 42133000 # Time in different power states +system.physmem_1.actBackEnergy 121194540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 22344960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 914224140 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 605228160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 53190600045 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 55284153510 # Total energy per rank (pJ) +system.physmem_1.averagePower 245.505612 # Core power per rank (mW) +system.physmem_1.totalIdleTime 224860041750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 42127000 # Time in different power states system.physmem_1.memoryStateTime::REF 167838000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 221301429000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 1575669750 # Time in different power states -system.physmem_1.memoryStateTime::ACT 114195250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 2005256000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 32430299 # Number of BP lookups -system.cpu.branchPred.condPredicted 16924101 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 738493 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17494977 # Number of BTB lookups -system.cpu.branchPred.BTBHits 12858505 # Number of BTB hits +system.physmem_1.memoryStateTime::SREF 221279795000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 1576124250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 114092500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 2004910250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 32421416 # Number of BP lookups +system.cpu.branchPred.condPredicted 16919401 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 734831 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17534346 # Number of BTB lookups +system.cpu.branchPred.BTBHits 12860140 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 73.498268 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6523139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 73.342570 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6521085 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2303930 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2264813 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 39117 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 128237 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 2302887 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2263691 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 39196 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 128438 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 450413042 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 450369774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037855 # Number of instructions committed system.cpu.committedOps 327812212 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2063976 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2044614 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.649636 # CPI: cycles per instruction -system.cpu.ipc 0.606194 # IPC: instructions per cycle +system.cpu.cpi 1.649477 # CPI: cycles per instruction +system.cpu.ipc 0.606253 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 104312542 31.82% 31.82% # Class of committed instruction system.cpu.op_class_0::IntMult 2145905 0.65% 32.48% # Class of committed instruction @@ -446,16 +446,16 @@ system.cpu.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 327812212 # Class of committed instruction -system.cpu.tickCycles 434950536 # Number of cycles that the object actually ticked -system.cpu.idleCycles 15462506 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 434912818 # Number of cycles that the object actually ticked +system.cpu.idleCycles 15456956 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 1355 # number of replacements -system.cpu.dcache.tags.tagsinuse 3085.768110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168654205 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.765100 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168647477 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4512 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37379.034796 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37377.543661 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768110 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.765100 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.753361 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id @@ -465,23 +465,23 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 7 system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337326812 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337326812 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 86521430 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86521430 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 337313356 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337313356 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 86514704 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86514704 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82047447 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 82047447 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 63538 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 63538 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 63536 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 63536 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168568877 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168568877 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168632415 # number of overall hits -system.cpu.dcache.overall_hits::total 168632415 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 168562151 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168562151 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168625687 # number of overall hits +system.cpu.dcache.overall_hits::total 168625687 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 1710 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 1710 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 5230 # number of WriteReq misses @@ -492,28 +492,28 @@ system.cpu.dcache.demand_misses::cpu.data 6940 # n system.cpu.dcache.demand_misses::total 6940 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 6945 # number of overall misses system.cpu.dcache.overall_misses::total 6945 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 177324000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 177324000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 487891500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 487891500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 665215500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 665215500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 665215500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 665215500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86523140 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86523140 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 177071500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 177071500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 487051000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 487051000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 664122500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 664122500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 664122500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 664122500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86516414 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86516414 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 63543 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 63543 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 63541 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 63541 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168575817 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168575817 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168639360 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168639360 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168569091 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168569091 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168632632 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168632632 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -524,14 +524,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000041 system.cpu.dcache.demand_miss_rate::total 0.000041 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000041 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000041 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103698.245614 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 103698.245614 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93287.093690 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 93287.093690 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 95852.377522 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 95852.377522 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 95783.369330 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 95783.369330 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 103550.584795 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 103550.584795 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 93126.386233 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 93126.386233 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 95694.884726 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 95694.884726 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 95625.989921 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 95625.989921 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -558,16 +558,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4509 system.cpu.dcache.demand_mshr_misses::total 4509 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4512 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4512 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 172098000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 172098000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285707500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 285707500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171838500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 171838500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 285292000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 285292000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 259000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 259000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457805500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 457805500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 458064500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 458064500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 457130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 457130500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 457389500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 457389500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -578,24 +578,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105001.830384 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105001.830384 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99549.651568 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99549.651568 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104843.502135 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104843.502135 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 99404.878049 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 99404.878049 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 86333.333333 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 86333.333333 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101531.492570 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 101531.492570 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101521.387411 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 101521.387411 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 38188 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.800722 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 69819801 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 40125 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1740.057346 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101381.791972 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 101381.791972 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101371.786348 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 101371.786348 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 38251 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.799688 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 69805458 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 40188 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1736.972678 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.800722 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.799688 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.939844 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id @@ -605,179 +605,179 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 32 system.cpu.icache.tags.age_task_id_blocks_1024::3 277 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1484 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 139759979 # Number of tag accesses -system.cpu.icache.tags.data_accesses 139759979 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 69819801 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 69819801 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 69819801 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 69819801 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 69819801 # number of overall hits -system.cpu.icache.overall_hits::total 69819801 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 40126 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 40126 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 40126 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 40126 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 40126 # number of overall misses -system.cpu.icache.overall_misses::total 40126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 817900500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 817900500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 817900500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 817900500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 817900500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 817900500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 69859927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 69859927 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 69859927 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 69859927 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 69859927 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 69859927 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000574 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000574 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000574 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000574 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000574 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000574 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20383.305089 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20383.305089 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20383.305089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20383.305089 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20383.305089 # average overall miss latency +system.cpu.icache.tags.tag_accesses 139731482 # Number of tag accesses +system.cpu.icache.tags.data_accesses 139731482 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 69805458 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 69805458 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 69805458 # 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number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 818936000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 818936000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 69845647 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 69845647 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 69845647 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 69845647 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 69845647 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 69845647 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000575 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000575 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000575 # 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number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 38188 # number of writebacks -system.cpu.icache.writebacks::total 38188 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40126 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 40126 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 40126 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 40126 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 40126 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 40126 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 777775500 # 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number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 40189 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 40189 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 40189 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 40189 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 40189 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 40189 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 778748000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 778748000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 778748000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 778748000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 778748000 # 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average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19377.142999 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19377.142999 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 6596.216022 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 61516 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7587 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 8.108080 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 6596.199570 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 61643 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 8.125890 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.840742 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.375280 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096675 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3167.827893 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3428.371677 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096674 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.104626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.201301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 7587 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::total 0.201300 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 7586 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 789 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 788 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 6671 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231537 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 560755 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 560755 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.231506 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 561762 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 561762 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 1010 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 1010 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 23270 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 23270 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::writebacks 23333 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 23333 # 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average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.170667 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98384.548003 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98384.548003 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92703.211679 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92703.211679 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 123238.148148 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 123238.148148 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 100231.943898 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92703.211679 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 106365.604186 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 100231.943898 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -796,122 +796,122 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 41 system.cpu.l2cache.overall_mshr_hits::total 43 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3424 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3424 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 150320500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 283130000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 402570000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 685700000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 283130000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 402570000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 685700000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085331 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085173 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.797199 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.797199 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.169967 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085331 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.169705 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085173 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922651 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.169967 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88530.133146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88530.133146 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82626.752336 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82626.752336 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 115034.377387 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 115034.377387 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82626.752336 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96864.040356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90438.776855 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 84181 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 39645 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.169705 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 88384.548003 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 88384.548003 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82713.993573 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82713.993573 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 114836.134454 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 114836.134454 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82713.993573 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 96701.897670 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90390.192460 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 84307 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 39708 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 15035 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 41767 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 41830 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 1010 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 38188 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 38251 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 345 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 40126 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 40189 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 1642 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118439 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 118628 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10379 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 128818 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5012032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 129007 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5020096 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 5365440 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 5373504 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 44638 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.339106 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.473411 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44701 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.338628 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.473248 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 29501 66.09% 66.09% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 15137 33.91% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 29564 66.14% 66.14% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 15137 33.86% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44638 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 81288500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 44701 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 81414500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 60188498 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 60282998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6789457 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 7587 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 7586 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 225206521000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4733 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 225184887000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4732 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4733 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15174 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15174 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485568 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 4732 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15172 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485504 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 7587 # Request fanout histogram +system.membus.snoop_fanout::samples 7586 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7587 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7586 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7587 # Request fanout histogram -system.membus.reqLayer0.occupancy 9082500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7586 # Request fanout histogram +system.membus.reqLayer0.occupancy 9076000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 40299000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40293000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index c49c5de69..faffc36d8 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,66 +1,66 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.124349 # Number of seconds simulated -sim_ticks 124348696500 # Number of ticks simulated -final_tick 124348696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.124341 # Number of seconds simulated +sim_ticks 124340889500 # Number of ticks simulated +final_tick 124340889500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 233440 # Simulator instruction rate (inst/s) -host_op_rate 280271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 106315167 # Simulator tick rate (ticks/s) -host_mem_usage 292792 # Number of bytes of host memory used -host_seconds 1169.62 # Real time elapsed on the host +host_inst_rate 229813 # Simulator instruction rate (inst/s) +host_op_rate 275917 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 104656772 # Simulator tick rate (ticks/s) +host_mem_usage 292960 # Number of bytes of host memory used +host_seconds 1188.08 # Real time elapsed on the host sim_insts 273037218 # Number of instructions simulated sim_ops 327811600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 1887808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 14649536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 167872 # Number of bytes read from this memory -system.physmem.bytes_read::total 16705216 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1887808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1887808 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 29497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 228899 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2623 # Number of read requests responded to by this memory -system.physmem.num_reads::total 261019 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 15181566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 117810129 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1350010 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 134341706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 15181566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 15181566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 15181566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 117810129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1350010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134341706 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 261020 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 1894400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 14645312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 169216 # Number of bytes read from this memory +system.physmem.bytes_read::total 16708928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1894400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 29600 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 228833 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2644 # Number of read requests responded to by this memory +system.physmem.num_reads::total 261077 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 15235535 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117783555 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1360904 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 134379994 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 15235535 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 15235535 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 15235535 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117783555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1360904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 134379994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 261078 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 261020 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 261078 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 16705280 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 16708992 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 16705280 # Total read bytes from the system interface side +system.physmem.bytesReadSys 16708992 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1258 # Per bank write bursts -system.physmem.perBankRdBursts::1 69987 # Per bank write bursts -system.physmem.perBankRdBursts::2 1297 # Per bank write bursts -system.physmem.perBankRdBursts::3 10756 # Per bank write bursts -system.physmem.perBankRdBursts::4 42907 # Per bank write bursts -system.physmem.perBankRdBursts::5 121816 # Per bank write bursts -system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 252 # Per bank write bursts -system.physmem.perBankRdBursts::8 224 # Per bank write bursts +system.physmem.perBankRdBursts::0 1259 # Per bank write bursts +system.physmem.perBankRdBursts::1 69989 # Per bank write bursts +system.physmem.perBankRdBursts::2 1294 # Per bank write bursts +system.physmem.perBankRdBursts::3 10805 # Per bank write bursts +system.physmem.perBankRdBursts::4 42847 # Per bank write bursts +system.physmem.perBankRdBursts::5 121814 # Per bank write bursts +system.physmem.perBankRdBursts::6 160 # Per bank write bursts +system.physmem.perBankRdBursts::7 259 # Per bank write bursts +system.physmem.perBankRdBursts::8 225 # Per bank write bursts system.physmem.perBankRdBursts::9 562 # Per bank write bursts -system.physmem.perBankRdBursts::10 7773 # Per bank write bursts +system.physmem.perBankRdBursts::10 7823 # Per bank write bursts system.physmem.perBankRdBursts::11 812 # Per bank write bursts -system.physmem.perBankRdBursts::12 1213 # Per bank write bursts -system.physmem.perBankRdBursts::13 743 # Per bank write bursts -system.physmem.perBankRdBursts::14 657 # Per bank write bursts +system.physmem.perBankRdBursts::12 1216 # Per bank write bursts +system.physmem.perBankRdBursts::13 747 # Per bank write bursts +system.physmem.perBankRdBursts::14 656 # Per bank write bursts system.physmem.perBankRdBursts::15 610 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 124348687000 # Total gap between requests +system.physmem.totGap 124340880000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 261020 # Read request sizes (log2) +system.physmem.readPktSize::6 261078 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,20 +95,20 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 204123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 43351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 212 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 172 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 60 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 24 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 204158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 181 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 245.871432 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.817049 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.519544 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18227 26.83% 26.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22195 32.67% 59.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11448 16.85% 76.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6857 10.09% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4767 7.02% 93.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2062 3.04% 96.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1306 1.92% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 411 0.61% 99.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 660 0.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67933 # Bytes accessed per row activation -system.physmem.totQLat 4577430956 # Total ticks spent queuing -system.physmem.totMemAccLat 9471555956 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1305100000 # Total ticks spent in databus transfers -system.physmem.avgQLat 17536.71 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 67983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 245.745201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.705876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.483366 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18259 26.86% 26.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22263 32.75% 59.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 11383 16.74% 76.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6868 10.10% 86.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4760 7.00% 93.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2080 3.06% 96.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1310 1.93% 98.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 394 0.58% 99.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 666 0.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67983 # Bytes accessed per row activation +system.physmem.totQLat 4612072505 # Total ticks spent queuing +system.physmem.totMemAccLat 9507285005 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1305390000 # Total ticks spent in databus transfers +system.physmem.avgQLat 17665.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 36286.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 134.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 36415.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 134.38 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 134.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 134.38 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.05 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 1.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 193077 # Number of row buffer hits during reads +system.physmem.readRowHits 193085 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.97 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 476395.25 # Average gap between requests -system.physmem.pageHitRate 73.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 450269820 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 239312700 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1773761640 # Energy for read commands per rank (pJ) +system.physmem.avgGap 476259.51 # Average gap between requests +system.physmem.pageHitRate 73.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 450291240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 239324085 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1773768780 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9689184960.000002 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4649576640 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 227532000 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 45899424420 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 3643060800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 957889500 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 67530012480 # Total energy per rank (pJ) -system.physmem_0.averagePower 543.069721 # Core power per rank (mW) -system.physmem_0.totalIdleTime 113559853415 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 155359000 # Time in different power states -system.physmem_0.memoryStateTime::REF 4100146000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 3415967750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 9487195385 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6533205335 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 100656823030 # Time in different power states -system.physmem_1.actEnergy 34836060 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 18489240 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 89914020 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 9681809280.000002 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4644193560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 227236800 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 45907805700 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3604922400 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 978458700 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 67507810545 # Total energy per rank (pJ) +system.physmem_0.averagePower 542.925264 # Core power per rank (mW) +system.physmem_0.totalIdleTime 113563299646 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 155533000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4097020000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 3501663750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 9387944632 # Time in different power states +system.physmem_0.memoryStateTime::ACT 6524904104 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 100673824014 # Time in different power states +system.physmem_1.actEnergy 35171640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 18667605 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 90321000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3070741440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 722151240 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 123038400 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10175174880 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3785444640 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 22033476180 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 40053946380 # Total energy per rank (pJ) -system.physmem_1.averagePower 322.109899 # Core power per rank (mW) -system.physmem_1.totalIdleTime 122443240524 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 197934000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1303004000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 90271203500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 9858082832 # Time in different power states -system.physmem_1.memoryStateTime::ACT 404517976 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 22313954192 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 35976625 # Number of BP lookups -system.cpu.branchPred.condPredicted 19268286 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 984581 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17895680 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13922117 # Number of BTB hits +system.physmem_1.refreshEnergy 3119298000.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 731861760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 127236960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10304428080 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3803073120 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 21964091670 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 40194673995 # Total energy per rank (pJ) +system.physmem_1.averagePower 323.261913 # Core power per rank (mW) +system.physmem_1.totalIdleTime 122403387505 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 207240000 # Time in different power states +system.physmem_1.memoryStateTime::REF 1323736000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 89902145500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 9903979079 # Time in different power states +system.physmem_1.memoryStateTime::ACT 406525995 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 22597262926 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 36038003 # Number of BP lookups +system.cpu.branchPred.condPredicted 19334387 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 996297 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17830996 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13933502 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 77.795965 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6952257 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4419 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 2517536 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 2473662 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 43874 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 129189 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 78.142029 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6950609 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 4465 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 2515874 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2470358 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 45516 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 129389 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,135 +401,135 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 248697394 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 248681780 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13177926 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 309504909 # Number of instructions fetch has processed -system.cpu.fetch.Branches 35976625 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 23348036 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 231160130 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1995425 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1604 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 63 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3168 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 82224377 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 245340603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.517503 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.300446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13212448 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 309769989 # Number of instructions fetch has processed +system.cpu.fetch.Branches 36038003 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 23354469 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 231113604 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2018885 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 3406 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 82291256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 35072 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 245340926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.517468 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.300338 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 84898952 34.60% 34.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 40504202 16.51% 51.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 28011427 11.42% 62.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 91926022 37.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 84879866 34.60% 34.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 40535888 16.52% 51.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 28014472 11.42% 62.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 91910700 37.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 245340603 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.144660 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.244504 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27511038 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 94682480 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 97198198 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 25085064 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 863823 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6682260 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 134191 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 348414004 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3355254 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 863823 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 44231004 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 38750016 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 289461 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 104525811 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 56680488 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 344543449 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1457117 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 7869034 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 94704 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 8433947 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 28409379 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 3429059 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 394730853 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2217537837 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 335903225 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 192790660 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 245340926 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144916 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.245648 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27542743 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 94606230 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 97234991 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 25081957 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 875005 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 12946400 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 134756 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 348426325 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3406644 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 875005 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44284460 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 38724844 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 289442 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 104535895 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 56631280 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 344535849 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1483850 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 7863336 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 96546 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 8390481 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 28393613 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 3430855 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 394784790 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2217316444 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 335868704 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 192847846 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22500805 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 11602 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 11569 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 59464824 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89978946 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 84398563 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2367642 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1978869 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 343240723 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22618 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 339371435 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 952430 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 15451741 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36726619 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 498 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 245340603 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.383266 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.138851 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 22554742 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 11609 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11576 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 59430212 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89918066 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 84391902 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2366315 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1969070 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 343213178 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 22626 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 339325700 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 951900 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 15424204 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36793818 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 506 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 245340926 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.383078 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.139070 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 64256390 26.19% 26.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 77349427 31.53% 57.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 59666013 24.32% 82.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34385256 14.02% 96.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 8895869 3.63% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 775150 0.32% 99.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 12498 0.01% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 64299867 26.21% 26.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 77319752 31.52% 57.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 59651654 24.31% 82.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34378652 14.01% 96.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 8900677 3.63% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 777968 0.32% 99.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 12356 0.01% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 245340603 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 245340926 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8783262 6.81% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7311 0.01% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 160118 0.12% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 165260 0.13% 7.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 81600 0.06% 7.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 59605 0.05% 7.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 821029 0.64% 7.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 312918 0.24% 8.05% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 382736 0.30% 8.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 27486319 21.30% 29.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 41316597 32.01% 61.66% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 30690860 23.78% 85.44% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 18793838 14.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8768859 6.80% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7313 0.01% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 162373 0.13% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.93% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 163818 0.13% 7.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 81957 0.06% 7.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 59658 0.05% 7.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 818593 0.63% 7.80% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 313085 0.24% 8.04% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 382100 0.30% 8.34% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 27482783 21.31% 29.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 41323323 32.04% 61.68% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 30643180 23.76% 85.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 18783688 14.56% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 108168046 31.87% 31.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148103 0.63% 32.51% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 108181018 31.88% 31.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148109 0.63% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued @@ -550,93 +550,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6799230 2.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8596305 2.53% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3207463 0.95% 37.99% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592644 0.47% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20838397 6.14% 44.60% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7175267 2.11% 46.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140594 2.10% 48.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175297 0.05% 48.87% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 46512276 13.71% 62.57% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 55971076 16.49% 79.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 43494028 12.82% 91.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 27552709 8.12% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6799471 2.00% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8597209 2.53% 37.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3207374 0.95% 38.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592649 0.47% 38.47% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20858202 6.15% 44.61% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7175067 2.11% 46.73% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140627 2.10% 48.83% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175298 0.05% 48.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 46505269 13.71% 62.59% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 55942906 16.49% 79.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 43451689 12.81% 91.88% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 27550812 8.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 339371435 # Type of FU issued -system.cpu.iq.rate 1.364596 # Inst issue rate -system.cpu.iq.fu_busy_cnt 129061453 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.380296 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 766002730 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 235175743 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 219154982 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 288094626 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 123554211 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 116970856 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 298827396 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 169605492 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5587628 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 339325700 # Type of FU issued +system.cpu.iq.rate 1.364498 # Inst issue rate +system.cpu.iq.fu_busy_cnt 128990730 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.380138 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 765966009 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 235211704 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 219112487 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287968947 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 123463225 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 116939299 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 298793937 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 169522493 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5585313 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4246671 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7079 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14875 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2022946 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4185791 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7155 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14925 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2016285 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 158625 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 537538 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 158671 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 539433 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 863823 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1349690 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1747618 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 343264743 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 875005 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1351770 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1745589 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 343237205 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89978946 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 84398563 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 11585 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6720 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1741103 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14875 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 437791 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 454404 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 892195 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 337380808 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 89446151 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1990627 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 89918066 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 84391902 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 11593 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6365 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1739416 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14925 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 447604 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 457294 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 904898 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 337307001 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 89393919 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2018699 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1402 # number of nop insts executed -system.cpu.iew.exec_refs 172577891 # number of memory reference insts executed -system.cpu.iew.exec_branches 31542264 # Number of branches executed -system.cpu.iew.exec_stores 83131740 # Number of stores executed -system.cpu.iew.exec_rate 1.356592 # Inst execution rate -system.cpu.iew.wb_sent 336269596 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 336125838 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153087171 # num instructions producing a value -system.cpu.iew.wb_consumers 267302196 # num instructions consuming a value -system.cpu.iew.wb_rate 1.351545 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.572712 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 14157457 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 1401 # number of nop insts executed +system.cpu.iew.exec_refs 172494904 # number of memory reference insts executed +system.cpu.iew.exec_branches 31547244 # Number of branches executed +system.cpu.iew.exec_stores 83100985 # Number of stores executed +system.cpu.iew.exec_rate 1.356380 # Inst execution rate +system.cpu.iew.wb_sent 336195874 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 336051786 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153071265 # num instructions producing a value +system.cpu.iew.wb_consumers 267284033 # num instructions consuming a value +system.cpu.iew.wb_rate 1.351333 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.572691 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 14115058 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 850692 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 243149020 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.348195 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.043585 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 861860 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 243135580 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.348269 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.043603 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 113393055 46.64% 46.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 66012492 27.15% 73.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 21342156 8.78% 82.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13170021 5.42% 87.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8181798 3.36% 91.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4369731 1.80% 93.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2981979 1.23% 94.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2444680 1.01% 95.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11253108 4.63% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 113362923 46.63% 46.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 66036162 27.16% 73.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 21343595 8.78% 82.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13169605 5.42% 87.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8174730 3.36% 91.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4365960 1.80% 93.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2981752 1.23% 94.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2446011 1.01% 95.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11254842 4.63% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 243149020 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 243135580 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037830 # Number of instructions committed system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,555 +686,556 @@ system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction -system.cpu.commit.bw_lim_events 11253108 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 573863058 # The number of ROB reads -system.cpu.rob.rob_writes 686133284 # The number of ROB writes -system.cpu.timesIdled 39270 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3356791 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 11254842 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 573805485 # The number of ROB reads +system.cpu.rob.rob_writes 686062388 # The number of ROB writes +system.cpu.timesIdled 39277 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3340854 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037218 # Number of Instructions Simulated system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.910855 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.910855 # CPI: Total CPI of All Threads -system.cpu.ipc 1.097869 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.097869 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 325196483 # number of integer regfile reads -system.cpu.int_regfile_writes 134110146 # number of integer regfile writes -system.cpu.fp_regfile_reads 186451278 # number of floating regfile reads -system.cpu.fp_regfile_writes 131762607 # number of floating regfile writes -system.cpu.cc_regfile_reads 1279524952 # number of cc regfile reads -system.cpu.cc_regfile_writes 79965424 # number of cc regfile writes -system.cpu.misc_regfile_reads 1056166666 # number of misc regfile reads +system.cpu.cpi 0.910798 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.910798 # CPI: Total CPI of All Threads +system.cpu.ipc 1.097938 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.097938 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 325088854 # number of integer regfile reads +system.cpu.int_regfile_writes 134066659 # number of integer regfile writes +system.cpu.fp_regfile_reads 186464530 # number of floating regfile reads +system.cpu.fp_regfile_writes 131741747 # number of floating regfile writes +system.cpu.cc_regfile_reads 1279144313 # number of cc regfile reads +system.cpu.cc_regfile_writes 80001955 # number of cc regfile writes +system.cpu.misc_regfile_reads 1055862294 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 1542800 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.844324 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 161972906 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1543312 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 104.951498 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 90889000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.844324 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 1544317 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.844251 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 161914838 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1544829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 104.810848 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 91273000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.844251 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 333232684 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 333232684 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 80960207 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 80960207 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80921128 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80921128 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 69704 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 69704 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10908 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10908 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 333130269 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 333130269 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 80902071 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 80902071 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80921196 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80921196 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 69698 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 69698 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 161881335 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 161881335 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 161951039 # number of overall hits -system.cpu.dcache.overall_hits::total 161951039 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2740251 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2740251 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1131571 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1131571 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 161823267 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 161823267 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 161892965 # number of overall hits +system.cpu.dcache.overall_hits::total 161892965 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2746434 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2746434 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1131503 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1131503 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 13 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 13 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3871822 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3871822 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3871840 # number of overall misses -system.cpu.dcache.overall_misses::total 3871840 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47426688500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47426688500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9189520410 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9189520410 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3877937 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3877937 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3877950 # number of overall misses +system.cpu.dcache.overall_misses::total 3877950 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47498967000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47498967000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9188860405 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9188860405 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 56616208910 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 56616208910 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 56616208910 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 56616208910 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83700458 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83700458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 56687827405 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 56687827405 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 56687827405 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 56687827405 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83648505 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83648505 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 69722 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 69722 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10912 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10912 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 69711 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 69711 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 165753157 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 165753157 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 165822879 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 165822879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032739 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032739 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013791 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013791 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000258 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000258 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 165701204 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 165701204 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 165770915 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 165770915 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032833 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032833 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013790 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013790 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000186 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000186 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023359 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023359 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023349 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023349 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17307.424940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17307.424940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8121.028561 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 8121.028561 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023403 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023403 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023393 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023393 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17294.778247 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17294.778247 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8120.933312 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8120.933312 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14622.626998 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14622.626998 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14622.559018 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14622.559018 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14618.037221 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14618.037221 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.988217 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14617.988217 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1097340 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1101938 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136170 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 136754 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 8.058603 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 1542800 # number of writebacks -system.cpu.dcache.writebacks::total 1542800 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1417655 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1417655 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910848 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 910848 # number of WriteReq MSHR hits +system.cpu.dcache.avg_blocked_cycles::no_targets 8.057812 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 1544317 # number of writebacks +system.cpu.dcache.writebacks::total 1544317 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1422290 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1422290 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910806 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 910806 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2328503 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2328503 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2328503 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2328503 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1322596 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1322596 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220723 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220723 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # 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number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28913598193 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28913598193 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28914868193 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28914868193 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015802 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015802 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 2333096 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2333096 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2333096 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2333096 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1324144 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1324144 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220697 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220697 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 7 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 7 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1544841 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1544841 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1544848 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1544848 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27090401500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27090401500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844259187 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844259187 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 932500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 932500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28934660687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28934660687 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28935593187 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28935593187 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015830 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015830 # 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average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.012708 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.012708 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 115454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 115454.545455 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18734.686862 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18734.686862 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.376227 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.376227 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 725912 # number of replacements -system.cpu.icache.tags.tagsinuse 511.812539 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 81490807 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 726424 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 112.180775 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 347441500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.812539 # Average occupied blocks per requestor +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000100 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000100 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009323 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009323 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009319 # 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Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 97 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 98 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 67 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 165175152 # Number of tag accesses -system.cpu.icache.tags.data_accesses 165175152 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 81490807 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 81490807 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 81490807 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 81490807 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 81490807 # number of overall hits -system.cpu.icache.overall_hits::total 81490807 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 733549 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 733549 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 733549 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 733549 # 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average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 11483.927375 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 11483.927375 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 11483.927375 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 138949 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 124 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 4383 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 165310431 # Number of tag accesses +system.cpu.icache.tags.data_accesses 165310431 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 81555981 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 81555981 # 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number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8470113937 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8470113937 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8470113937 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 82291230 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 82291230 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 82291230 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 82291230 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 82291230 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 82291230 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008935 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008935 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008935 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008935 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008935 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008935 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 11520.061825 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 11520.061825 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 11520.061825 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 11520.061825 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 11520.061825 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 11520.061825 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 144128 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 153 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 4365 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 31.701802 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 41.333333 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 725912 # number of writebacks -system.cpu.icache.writebacks::total 725912 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7108 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726441 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 726441 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 726441 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 726441 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 726441 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 726441 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 7897580451 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 7897580451 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7897580451 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 7897580451 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7897580451 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 7897580451 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008835 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008835 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008835 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008835 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10871.606161 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10871.606161 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10871.606161 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10871.606161 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 403113 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 403204 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 83 # number of redundant prefetches already in prefetch queue +system.cpu.icache.avg_blocked_cycles::no_mshrs 33.019015 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 51 # 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miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.113756 # miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2388.888889 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2388.888889 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88855.696203 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88855.696203 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 89770.785492 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 89770.785492 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 78657.032709 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 78657.032709 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 89770.785492 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78692.227552 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79961.135006 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 89770.785492 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78692.227552 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79961.135006 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 56 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 56 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 55 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 55 # number of ReadExReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 11 # number of ReadCleanReq MSHR hits system.cpu.l2cache.ReadCleanReq_mshr_hits::total 11 # number of ReadCleanReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 35 # number of ReadSharedReq MSHR hits -system.cpu.l2cache.ReadSharedReq_mshr_hits::total 35 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 36 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 36 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 91 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16573484500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2480103000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16637653500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19117756500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2480103000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16637653500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203156315 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19320912815 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.944444 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.944444 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003321 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003321 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040611 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172516 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172516 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.113848 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040611 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148317 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003330 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003330 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040667 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172262 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172262 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.113711 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.137720 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3749.890977 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15588.235294 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15588.235294 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86997.953615 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86997.953615 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83114.990847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83114.990847 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72598.448060 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72598.448060 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73839.839472 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83114.990847 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72644.559391 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3749.890977 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61690.732691 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 4538483 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2268732 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254880 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 51558 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51557 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.137505 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3756.797067 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87304.761905 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87304.761905 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83784.432958 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83784.432958 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72659.490658 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72659.490658 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73975.392170 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61824.744777 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 4544579 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 2271779 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 51433 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51432 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 2049022 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 968252 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 1300460 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 55547 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 18 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220730 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 726441 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 1322582 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2178711 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4629460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6808171 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 92945280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197511168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 290456448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 55629 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 5248 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 2325318 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.131791 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338265 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 2052102 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 968794 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 1302965 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 55467 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 220698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220698 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 727972 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 1324131 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2183308 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4634013 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6817321 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93141504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197705344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 290846848 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 55544 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4928 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 2328287 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.131576 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.338031 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 2018862 86.82% 86.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 306455 13.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 2021941 86.84% 86.84% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 306345 13.16% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2325318 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4537953500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 3.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1089727365 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 2328287 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4544048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1092026360 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2314999455 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2317274956 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 261037 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 253739 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 261096 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 253777 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 124348696500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 260286 # Transaction distribution -system.membus.trans_dist::UpgradeReq 17 # Transaction distribution -system.membus.trans_dist::ReadExReq 733 # Transaction distribution -system.membus.trans_dist::ReadExResp 733 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 260287 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 522056 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16705216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 16705216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 260342 # Transaction distribution +system.membus.trans_dist::UpgradeReq 18 # Transaction distribution +system.membus.trans_dist::ReadExReq 735 # Transaction distribution +system.membus.trans_dist::ReadExResp 735 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 260343 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522173 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 522173 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16708928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 16708928 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 261037 # Request fanout histogram +system.membus.snoop_fanout::samples 261096 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 261037 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 261096 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 261037 # Request fanout histogram -system.membus.reqLayer0.occupancy 316168930 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 261096 # Request fanout histogram +system.membus.reqLayer0.occupancy 316188421 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1389509080 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1389693354 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 7545f6451..06d9deeed 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,96 +1,96 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.525654 # Number of seconds simulated -sim_ticks 525654485500 # Number of ticks simulated -final_tick 525654485500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.525648 # Number of seconds simulated +sim_ticks 525647850500 # Number of ticks simulated +final_tick 525647850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 282925 # Simulator instruction rate (inst/s) -host_op_rate 348318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232138645 # Simulator tick rate (ticks/s) -host_mem_usage 279272 # Number of bytes of host memory used -host_seconds 2264.40 # Real time elapsed on the host +host_inst_rate 304424 # Simulator instruction rate (inst/s) +host_op_rate 374786 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 249775392 # Simulator tick rate (ticks/s) +host_mem_usage 281156 # Number of bytes of host memory used +host_seconds 2104.48 # Real time elapsed on the host sim_insts 640655085 # Number of instructions simulated sim_ops 788730744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory -system.physmem.bytes_read::total 18638656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 18639040 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291229 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291235 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 312296 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 35145702 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 35457999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 312296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 312296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8047628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8047628 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8047628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 312296 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 35145702 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 43505627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291229 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 313031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 35146146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 35459177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 313031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 313031 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 8047730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8047730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8047730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 313031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 35146146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 43506907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291235 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 291229 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291235 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18617024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue -system.physmem.bytesWritten 4229248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18638656 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18619136 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18639040 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18281 # Per bank write bursts -system.physmem.perBankRdBursts::1 18133 # Per bank write bursts -system.physmem.perBankRdBursts::2 18221 # Per bank write bursts -system.physmem.perBankRdBursts::3 18176 # Per bank write bursts -system.physmem.perBankRdBursts::4 18285 # Per bank write bursts -system.physmem.perBankRdBursts::5 18412 # Per bank write bursts -system.physmem.perBankRdBursts::6 18178 # Per bank write bursts +system.physmem.perBankRdBursts::0 18288 # Per bank write bursts +system.physmem.perBankRdBursts::1 18134 # Per bank write bursts +system.physmem.perBankRdBursts::2 18217 # Per bank write bursts +system.physmem.perBankRdBursts::3 18185 # Per bank write bursts +system.physmem.perBankRdBursts::4 18292 # Per bank write bursts +system.physmem.perBankRdBursts::5 18424 # Per bank write bursts +system.physmem.perBankRdBursts::6 18179 # Per bank write bursts system.physmem.perBankRdBursts::7 17990 # Per bank write bursts -system.physmem.perBankRdBursts::8 18034 # Per bank write bursts -system.physmem.perBankRdBursts::9 18056 # Per bank write bursts -system.physmem.perBankRdBursts::10 18101 # Per bank write bursts -system.physmem.perBankRdBursts::11 18200 # Per bank write bursts -system.physmem.perBankRdBursts::12 18218 # Per bank write bursts -system.physmem.perBankRdBursts::13 18271 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18258 # Per bank write bursts +system.physmem.perBankRdBursts::8 18031 # Per bank write bursts +system.physmem.perBankRdBursts::9 18051 # Per bank write bursts +system.physmem.perBankRdBursts::10 18108 # Per bank write bursts +system.physmem.perBankRdBursts::11 18204 # Per bank write bursts +system.physmem.perBankRdBursts::12 18211 # Per bank write bursts +system.physmem.perBankRdBursts::13 18269 # Per bank write bursts +system.physmem.perBankRdBursts::14 18079 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts system.physmem.perBankWrBursts::0 4171 # Per bank write bursts system.physmem.perBankWrBursts::1 4099 # Per bank write bursts -system.physmem.perBankWrBursts::2 4135 # Per bank write bursts +system.physmem.perBankWrBursts::2 4134 # Per bank write bursts system.physmem.perBankWrBursts::3 4146 # Per bank write bursts -system.physmem.perBankWrBursts::4 4224 # Per bank write bursts +system.physmem.perBankWrBursts::4 4223 # Per bank write bursts system.physmem.perBankWrBursts::5 4224 # Per bank write bursts -system.physmem.perBankWrBursts::6 4174 # Per bank write bursts +system.physmem.perBankWrBursts::6 4173 # Per bank write bursts system.physmem.perBankWrBursts::7 4094 # Per bank write bursts -system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts +system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::9 4093 # Per bank write bursts system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4098 # Per bank write bursts -system.physmem.perBankWrBursts::13 4096 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4140 # Per bank write bursts +system.physmem.perBankWrBursts::12 4095 # Per bank write bursts +system.physmem.perBankWrBursts::13 4095 # Per bank write bursts +system.physmem.perBankWrBursts::14 4095 # Per bank write bursts +system.physmem.perBankWrBursts::15 4138 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 525654384500 # Total gap between requests +system.physmem.totGap 525647749500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291229 # Read request sizes (log2) +system.physmem.readPktSize::6 291235 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,9 +98,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290544 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -146,23 +146,23 @@ system.physmem.wrQLenPdf::12 1 # Wh system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4020 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4021 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -194,43 +194,43 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 102767 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 222.307005 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 147.372317 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 261.848294 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36138 35.16% 35.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 41898 40.77% 75.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13163 12.81% 88.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1012 0.98% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 489 0.48% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1030 1.00% 91.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 399 0.39% 91.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 484 0.47% 92.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8154 7.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 102767 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4019 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.497387 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.151985 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 506.429034 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4017 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 102644 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 222.570282 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 147.559533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 262.016403 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 36015 35.09% 35.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 41909 40.83% 75.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13148 12.81% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1006 0.98% 89.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 491 0.48% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1034 1.01% 91.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 399 0.39% 91.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 481 0.47% 92.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8161 7.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 102644 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.515182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.167653 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 506.604541 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4019 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.442399 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.422334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.830212 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3130 77.88% 77.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 889 22.12% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4019 # Writes before turning the bus around for reads -system.physmem.totQLat 15538679500 # Total ticks spent queuing -system.physmem.totMemAccLat 20992885750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1454455000 # Total ticks spent in databus transfers -system.physmem.avgQLat 53417.53 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.442509 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.422441 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.830286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3129 77.87% 77.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 889 22.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads +system.physmem.totQLat 15528676000 # Total ticks spent queuing +system.physmem.totMemAccLat 20983501000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1454620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 53377.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 72167.53 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 72127.09 # Average memory access latency per DRAM burst system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 8.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 8.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -238,67 +238,67 @@ system.physmem.busUtil 0.34 # Da system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.65 # Average write queue length when enqueuing -system.physmem.readRowHits 202495 # Number of row buffer hits during reads -system.physmem.writeRowHits 51707 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.23 # Row buffer hit rate for writes -system.physmem.avgGap 1471073.79 # Average gap between requests -system.physmem.pageHitRate 71.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 367124520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 195116130 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1040126640 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 173653740 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 28870255440.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 8266537290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634065440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 57360982710 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 51276223200 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 64953258915 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 214157919585 # Total energy per rank (pJ) -system.physmem_0.averagePower 407.411950 # Core power per rank (mW) -system.physmem_0.totalIdleTime 503225172750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3206676000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12282762000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 243901523000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 133531907000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 6939814000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 125791803500 # Time in different power states -system.physmem_1.actEnergy 366660420 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 194884635 # Energy for precharge commands per rank (pJ) +system.physmem.avgWrQLen 28.92 # Average write queue length when enqueuing +system.physmem.readRowHits 202546 # Number of row buffer hits during reads +system.physmem.writeRowHits 51789 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.62 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.35 # Row buffer hit rate for writes +system.physmem.avgGap 1471030.52 # Average gap between requests +system.physmem.pageHitRate 71.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 366410520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 194736630 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1040362260 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 173638080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 28886236080.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 8300918550 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634993280 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 57345491820 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 51305938080 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 64928910000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 214198815120 # Total energy per rank (pJ) +system.physmem_0.averagePower 407.494892 # Core power per rank (mW) +system.physmem_0.totalIdleTime 503139346250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3209706000 # Time in different power states +system.physmem_0.memoryStateTime::REF 12289528000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 243772297750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 133609273250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7009209500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 125757836000 # Time in different power states +system.physmem_1.actEnergy 366546180 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 194797350 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 171294300 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 28737493200.000008 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8178131430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1630074720 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 56926536120 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 51134645280 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 65306601210 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 213703234155 # Total energy per rank (pJ) -system.physmem_1.averagePower 406.546781 # Core power per rank (mW) -system.physmem_1.totalIdleTime 503430400500 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3200172000 # Time in different power states -system.physmem_1.memoryStateTime::REF 12226116000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 245428473250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 133163073250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 6797797000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 124838854000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 147261657 # Number of BP lookups -system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 89949365 # Number of BTB lookups -system.cpu.branchPred.BTBHits 63294627 # Number of BTB hits +system.physmem_1.writeEnergy 171226440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 28725815040.000008 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 8187694890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1628706720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 56919000150 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 51113801760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 65311053315 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 213675530385 # Total energy per rank (pJ) +system.physmem_1.averagePower 406.499389 # Core power per rank (mW) +system.physmem_1.totalIdleTime 503405920500 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3197022000 # Time in different power states +system.physmem_1.memoryStateTime::REF 12221338000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 245475081750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 133108808000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 6823284750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 124822316000 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 147257105 # Number of BP lookups +system.cpu.branchPred.condPredicted 98226689 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1384794 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 89640439 # Number of BTB lookups +system.cpu.branchPred.BTBHits 63297158 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. +system.cpu.branchPred.BTBHitPct 70.612280 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19276056 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1321 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 15995188 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 15989428 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5760 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -328,7 +328,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -358,7 +358,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -388,7 +388,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,16 +419,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1051308971 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1051295701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655085 # Number of instructions committed system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed -system.cpu.discardedOps 8621767 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 8620171 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.640991 # CPI: cycles per instruction -system.cpu.ipc 0.609388 # IPC: instructions per cycle +system.cpu.cpi 1.640970 # CPI: cycles per instruction +system.cpu.ipc 0.609396 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction @@ -468,30 +468,30 @@ system.cpu.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 788730744 # Class of committed instruction -system.cpu.tickCycles 955911046 # Number of cycles that the object actually ticked -system.cpu.idleCycles 95397925 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 955914808 # Number of cycles that the object actually ticked +system.cpu.idleCycles 95380893 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 778100 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.108689 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.107040 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378447440 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 850386500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.108689 # Average occupied blocks per requestor +system.cpu.dcache.tags.avg_refs 483.826867 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 850680500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.107040 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 970 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 759379166 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759379166 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 249618713 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249618713 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits @@ -500,10 +500,10 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378434445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378434445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378437929 # number of overall hits -system.cpu.dcache.overall_hits::total 378437929 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 378432478 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378432478 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378435962 # number of overall hits +system.cpu.dcache.overall_hits::total 378435962 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses @@ -514,16 +514,16 @@ system.cpu.dcache.demand_misses::cpu.data 850904 # n system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses system.cpu.dcache.overall_misses::total 851045 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37269485500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37269485500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10946218000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10946218000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48215703500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48215703500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48215703500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48215703500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37264745000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37264745000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10940214000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10940214000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48204959000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48204959000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48204959000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48204959000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250331905 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250331905 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) @@ -532,10 +532,10 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379285349 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379285349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379288974 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379288974 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379283382 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379283382 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379287007 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379287007 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002849 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002849 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses @@ -546,22 +546,22 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52257.296072 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 52257.296072 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79486.304752 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 79486.304752 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 56664.093129 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 56664.093129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 56654.705098 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 56654.705098 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52250.649194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52250.649194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79442.706518 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 79442.706518 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 56651.465970 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 56651.465970 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 56642.080031 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 56642.080031 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 88688 # number of writebacks -system.cpu.dcache.writebacks::total 88688 # number of writebacks +system.cpu.dcache.writebacks::writebacks 88684 # number of writebacks +system.cpu.dcache.writebacks::total 88684 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits @@ -580,16 +580,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782057 system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36547770500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36547770500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5489520000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5489520000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36543095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36543095500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5486426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5486426000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42037290500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 42037290500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42039092500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 42039092500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42029521500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42029521500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42031323500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42031323500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -600,206 +600,206 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51278.203680 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51278.203680 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79188.713540 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79188.713540 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51271.644440 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51271.644440 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79144.081244 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79144.081244 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53752.207959 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53752.207959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53744.959703 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53744.959703 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 24885 # number of replacements -system.cpu.icache.tags.tagsinuse 1711.889727 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 257789639 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 9678.241440 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53742.273901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53742.273901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53735.027410 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53735.027410 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 24889 # number of replacements +system.cpu.icache.tags.tagsinuse 1710.890314 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 257795451 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 26639 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 9677.369684 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1711.889727 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.835884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.835884 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 515659188 # Number of tag accesses -system.cpu.icache.tags.data_accesses 515659188 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 257789639 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 257789639 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 257789639 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 257789639 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 257789639 # number of overall hits -system.cpu.icache.overall_hits::total 257789639 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses -system.cpu.icache.overall_misses::total 26637 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 539890500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 539890500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 539890500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 539890500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 539890500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 539890500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 257816276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 257816276 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 257816276 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 257816276 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 257816276 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 257816276 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 1710.890314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835396 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 515670821 # Number of tag accesses +system.cpu.icache.tags.data_accesses 515670821 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 257795451 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 257795451 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 257795451 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 257795451 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 257795451 # number of overall hits +system.cpu.icache.overall_hits::total 257795451 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 26640 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 26640 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 26640 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 26640 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 26640 # number of overall misses +system.cpu.icache.overall_misses::total 26640 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 538801500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 538801500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 538801500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 538801500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 538801500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 538801500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 257822091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 257822091 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 257822091 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 257822091 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 257822091 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 257822091 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000103 # 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average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.543478 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136234.780929 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136234.780929 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 123229.261225 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 123229.261225 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -820,124 +820,124 @@ system.cpu.l2cache.overall_mshr_hits::cpu.data 26 system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2572 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2572 # number of ReadCleanReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291236 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291230 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4690699000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4690699000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 193386000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 193386000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28102659500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28102659500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 193386000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32793358500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 32986744500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 193386000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32793358500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 32986744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 291236 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4687605000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4687605000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192261000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192261000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28098015500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28098015500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192261000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32785620500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 32977881500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192261000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32785620500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 32977881500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096547 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.360062 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.360068 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.360062 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70973.339789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70973.339789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75364.770070 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75364.770070 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126262.662138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126262.662138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75364.770070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113603.908004 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113266.986574 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.360068 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70926.525548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70926.525548 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74751.555210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74751.555210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126241.797073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126241.797073 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1611825 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 803048 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 2036 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2021 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 2033 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2018 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 154786 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 882151 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 739513 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 154782 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 24889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 882157 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 26640 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78158 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78168 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 59033920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 258837 # Total snoops (count) +system.cpu.toL2Bus.pkt_count::total 2420660 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736320 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 59034112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 258839 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1067670 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.005005 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.070770 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 1067675 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.005002 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.070750 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 1062341 99.50% 99.50% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 5314 0.50% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 1062349 99.50% 99.50% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5311 0.50% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1067670 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 919482000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1067675 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 919485500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 39960496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 548029 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 256840 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 548040 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 256844 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 525654485500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 225138 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 225144 # Transaction distribution system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution -system.membus.trans_dist::CleanEvict 190702 # Transaction distribution +system.membus.trans_dist::CleanEvict 190707 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 225138 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839258 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 839258 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868928 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22868928 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 225144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839275 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 839275 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22869312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22869312 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 291229 # Request fanout histogram +system.membus.snoop_fanout::samples 291235 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 291229 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 291235 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 291229 # Request fanout histogram -system.membus.reqLayer0.occupancy 917205000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 291235 # Request fanout histogram +system.membus.reqLayer0.occupancy 917214500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1553500250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1553534250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index bcc6de449..1f99db17b 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.338999 # Number of seconds simulated -sim_ticks 338998876000 # Number of ticks simulated -final_tick 338998876000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.339069 # Number of seconds simulated +sim_ticks 339069355000 # Number of ticks simulated +final_tick 339069355000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210128 # Simulator instruction rate (inst/s) -host_op_rate 258696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 111189218 # Simulator tick rate (ticks/s) -host_mem_usage 277020 # Number of bytes of host memory used -host_seconds 3048.85 # Real time elapsed on the host +host_inst_rate 212003 # Simulator instruction rate (inst/s) +host_op_rate 261004 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 112204360 # Simulator tick rate (ticks/s) +host_mem_usage 277184 # Number of bytes of host memory used +host_seconds 3021.89 # Real time elapsed on the host sim_insts 640649299 # Number of instructions simulated sim_ops 788724958 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 268928 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48012032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12961152 # Number of bytes read from this memory -system.physmem.bytes_read::total 61242112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 268928 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 268928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244288 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244288 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4202 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750188 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202518 # Number of read requests responded to by this memory -system.physmem.num_reads::total 956908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66317 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66317 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 793301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 141628883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 38233613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 180655797 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 793301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 793301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 12520065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 12520065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 12520065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 793301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 141628883 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 38233613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 193175862 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 956909 # Number of read requests accepted -system.physmem.writeReqs 66317 # Number of write requests accepted -system.physmem.readBursts 956909 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66317 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61223936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18240 # Total number of bytes read from write queue -system.physmem.bytesWritten 4238080 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 61242176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244288 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 285 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 65 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 272000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 48065856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12979392 # Number of bytes read from this memory +system.physmem.bytes_read::total 61317248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 272000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 272000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4246400 # Number of bytes written to this memory +system.physmem.bytes_written::total 4246400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 4250 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 751029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202803 # Number of read requests responded to by this memory +system.physmem.num_reads::total 958082 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66350 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66350 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 802196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 141758184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 38279461 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 180839840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 802196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 802196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 12523692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 12523692 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 12523692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 802196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 141758184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 38279461 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193363532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 958083 # Number of read requests accepted +system.physmem.writeReqs 66350 # Number of write requests accepted +system.physmem.readBursts 958083 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66350 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 61296960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20352 # Total number of bytes read from write queue +system.physmem.bytesWritten 4240000 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 61317312 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4246400 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 318 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 71 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19928 # Per bank write bursts -system.physmem.perBankRdBursts::1 19580 # Per bank write bursts -system.physmem.perBankRdBursts::2 657267 # Per bank write bursts -system.physmem.perBankRdBursts::3 20958 # Per bank write bursts -system.physmem.perBankRdBursts::4 19729 # Per bank write bursts -system.physmem.perBankRdBursts::5 20737 # Per bank write bursts -system.physmem.perBankRdBursts::6 19560 # Per bank write bursts -system.physmem.perBankRdBursts::7 19988 # Per bank write bursts -system.physmem.perBankRdBursts::8 19522 # Per bank write bursts -system.physmem.perBankRdBursts::9 20089 # Per bank write bursts -system.physmem.perBankRdBursts::10 19525 # Per bank write bursts -system.physmem.perBankRdBursts::11 19708 # Per bank write bursts -system.physmem.perBankRdBursts::12 19661 # Per bank write bursts -system.physmem.perBankRdBursts::13 21032 # Per bank write bursts -system.physmem.perBankRdBursts::14 19553 # Per bank write bursts -system.physmem.perBankRdBursts::15 19787 # Per bank write bursts -system.physmem.perBankWrBursts::0 4255 # Per bank write bursts -system.physmem.perBankWrBursts::1 4105 # Per bank write bursts -system.physmem.perBankWrBursts::2 4143 # Per bank write bursts -system.physmem.perBankWrBursts::3 4152 # Per bank write bursts -system.physmem.perBankWrBursts::4 4244 # Per bank write bursts -system.physmem.perBankWrBursts::5 4226 # Per bank write bursts +system.physmem.perBankRdBursts::0 19910 # Per bank write bursts +system.physmem.perBankRdBursts::1 19573 # Per bank write bursts +system.physmem.perBankRdBursts::2 657828 # Per bank write bursts +system.physmem.perBankRdBursts::3 21032 # Per bank write bursts +system.physmem.perBankRdBursts::4 19718 # Per bank write bursts +system.physmem.perBankRdBursts::5 21045 # Per bank write bursts +system.physmem.perBankRdBursts::6 19700 # Per bank write bursts +system.physmem.perBankRdBursts::7 20038 # Per bank write bursts +system.physmem.perBankRdBursts::8 19491 # Per bank write bursts +system.physmem.perBankRdBursts::9 20101 # Per bank write bursts +system.physmem.perBankRdBursts::10 19540 # Per bank write bursts +system.physmem.perBankRdBursts::11 19692 # Per bank write bursts +system.physmem.perBankRdBursts::12 19618 # Per bank write bursts +system.physmem.perBankRdBursts::13 21105 # Per bank write bursts +system.physmem.perBankRdBursts::14 19493 # Per bank write bursts +system.physmem.perBankRdBursts::15 19881 # Per bank write bursts +system.physmem.perBankWrBursts::0 4272 # Per bank write bursts +system.physmem.perBankWrBursts::1 4107 # Per bank write bursts +system.physmem.perBankWrBursts::2 4147 # Per bank write bursts +system.physmem.perBankWrBursts::3 4153 # Per bank write bursts +system.physmem.perBankWrBursts::4 4251 # Per bank write bursts +system.physmem.perBankWrBursts::5 4229 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts -system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4096 # Per bank write bursts +system.physmem.perBankWrBursts::9 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4095 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4097 # Per bank write bursts -system.physmem.perBankWrBursts::13 4095 # Per bank write bursts -system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4152 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.perBankWrBursts::14 4095 # Per bank write bursts +system.physmem.perBankWrBursts::15 4151 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 338998865500 # Total gap between requests +system.physmem.totGap 339069344500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 956909 # Read request sizes (log2) +system.physmem.readPktSize::6 958083 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66317 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 764114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6701 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 10166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6863 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3709 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 2433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1574 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1088 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 644 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66350 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 765133 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 120601 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15570 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7738 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 9158 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10207 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 3672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 2435 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 666 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -149,47 +149,47 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3520 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5885 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 556 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3538 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4041 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 22 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 15 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 10 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see @@ -198,134 +198,137 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 195260 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 335.246789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.210032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 355.737014 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 64653 33.11% 33.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 60691 31.08% 64.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 15519 7.95% 72.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3195 1.64% 73.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3493 1.79% 75.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2388 1.22% 76.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2513 1.29% 78.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 34304 17.57% 95.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8504 4.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 195260 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3991 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 173.742922 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 35.179059 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1709.732000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 3971 99.50% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 9 0.23% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-12287 3 0.08% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-16383 3 0.08% 99.87% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-20479 1 0.03% 99.90% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::24576-28671 1 0.03% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-40959 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-49151 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3991 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3991 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.592333 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.512127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.873555 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3350 83.94% 83.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 21 0.53% 84.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 395 9.90% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 55 1.38% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 24 0.60% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.48% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 17 0.43% 97.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 26 0.65% 97.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 20 0.50% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 16 0.40% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 9 0.23% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 11 0.28% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 7 0.18% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 5 0.13% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.10% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 6 0.15% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 3 0.08% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3991 # Writes before turning the bus around for reads -system.physmem.totQLat 27417238749 # Total ticks spent queuing -system.physmem.totMemAccLat 45353938749 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4783120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28660.41 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 196319 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 333.816859 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.183939 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 355.380336 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 65406 33.32% 33.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 61086 31.12% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 15476 7.88% 72.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3179 1.62% 73.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3479 1.77% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2336 1.19% 76.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2511 1.28% 78.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 34323 17.48% 95.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8523 4.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 196319 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4003 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 214.941294 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 35.155298 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2727.024521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-4095 3978 99.38% 99.38% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-8191 12 0.30% 99.68% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-12287 3 0.07% 99.75% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-16383 4 0.10% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16384-20479 1 0.02% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-36863 1 0.02% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::36864-40959 1 0.02% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::69632-73727 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::126976-131071 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4003 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4003 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.550087 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.475287 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.816460 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3400 84.94% 84.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 19 0.47% 85.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 373 9.32% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 54 1.35% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 20 0.50% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 27 0.67% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 15 0.37% 97.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 21 0.52% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 14 0.35% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 14 0.35% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 14 0.35% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.15% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.17% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.15% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 3 0.07% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 4 0.10% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 2 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4003 # Writes before turning the bus around for reads +system.physmem.totQLat 27518767878 # Total ticks spent queuing +system.physmem.totMemAccLat 45476861628 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4788825000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28732.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47410.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 180.60 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47482.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 180.78 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 12.50 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 180.66 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 180.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 12.52 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.51 # Data bus utilization in percentage system.physmem.busUtilRead 1.41 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.10 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.35 # Average write queue length when enqueuing -system.physmem.readRowHits 804753 # Number of row buffer hits during reads -system.physmem.writeRowHits 22823 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 34.45 # Row buffer hit rate for writes -system.physmem.avgGap 331304.00 # Average gap between requests -system.physmem.pageHitRate 80.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 893206860 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 474750705 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 5695906440 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 174321900 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 27330582240.000008 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14459296590 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 677245920 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 138340780680 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 698740320 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 673162065.000000 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 189465949500 # Total energy per rank (pJ) -system.physmem_0.averagePower 558.898453 # Core power per rank (mW) -system.physmem_0.totalIdleTime 305423895331 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 532417778 # Time in different power states -system.physmem_0.memoryStateTime::REF 11568510000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 220427000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1819753036 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21474052891 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 303383715295 # Time in different power states -system.physmem_1.actEnergy 500999520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 266260995 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134381780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 171346500 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 25447939920.000004 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 7069016310 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1362680640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 70550856240 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 31070458080 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 25392894210 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 162967325295 # Total energy per rank (pJ) -system.physmem_1.averagePower 480.731167 # Core power per rank (mW) -system.physmem_1.totalIdleTime 319946801176 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 2603762514 # Time in different power states -system.physmem_1.memoryStateTime::REF 10820898000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 84317463250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 80912710040 # Time in different power states -system.physmem_1.memoryStateTime::ACT 5627391560 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 154716650636 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 174659469 # Number of BP lookups -system.cpu.branchPred.condPredicted 119114964 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 4015677 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 96720579 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67753891 # Number of BTB hits +system.physmem.avgWrQLen 25.37 # Average write queue length when enqueuing +system.physmem.readRowHits 804881 # Number of row buffer hits during reads +system.physmem.writeRowHits 22802 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.04 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 34.40 # Row buffer hit rate for writes +system.physmem.avgGap 330982.45 # Average gap between requests +system.physmem.pageHitRate 80.82 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 901474980 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 479122545 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 5703739020 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 174499380 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27325665120.000008 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 14491103160 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 673386240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 138371323560 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 679220160 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 661319340.000000 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 189506984115 # Total energy per rank (pJ) +system.physmem_0.averagePower 558.903308 # Core power per rank (mW) +system.physmem_0.totalIdleTime 305432505529 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 523884278 # Time in different power states +system.physmem_0.memoryStateTime::REF 11566244000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 219111500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1768844578 # Time in different power states +system.physmem_0.memoryStateTime::ACT 21546721193 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 303444549451 # Time in different power states +system.physmem_1.actEnergy 500335500 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 265908060 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134695940 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 171325620 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 25432573920.000004 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6980276430 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1364879040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 70621447890 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 30989177760 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 25472740305 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 162933984825 # Total energy per rank (pJ) +system.physmem_1.averagePower 480.532913 # Core power per rank (mW) +system.physmem_1.totalIdleTime 320205691246 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 2610959521 # Time in different power states +system.physmem_1.memoryStateTime::REF 10814464000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 84633345250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 80700935022 # Time in different power states +system.physmem_1.memoryStateTime::ACT 5438217483 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 154871433724 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 175312537 # Number of BP lookups +system.cpu.branchPred.condPredicted 119126010 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 4023429 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 95987051 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67762694 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.051164 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18782444 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1299597 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 16716760 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 16702354 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 14406 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 1279517 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 70.595662 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18784914 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1299715 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 16714738 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 16702890 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 11848 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 1279488 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -355,7 +358,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -385,7 +388,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -415,7 +418,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -446,134 +449,134 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 677997753 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 678138711 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 35007390 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 824275552 # Number of instructions fetch has processed -system.cpu.fetch.Branches 174659469 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 103238689 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 638483488 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8068049 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 35026134 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 824295259 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175312537 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103250498 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 638595633 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8083491 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2728 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 17 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 3169 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 247736654 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 13165 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 677531262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.500399 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.263726 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3109 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 247757876 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 12590 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 677669366 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.498301 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.263018 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 215511441 31.81% 31.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 148279019 21.89% 53.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72933920 10.76% 64.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 240806882 35.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 215620652 31.82% 31.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 148930568 21.98% 53.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72932404 10.76% 64.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 240185742 35.44% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 677531262 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.257611 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.215750 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 75755548 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 258011846 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 277771746 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61971111 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4021011 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 20808683 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13107 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 924572936 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 11806711 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4021011 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 118697379 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 157348847 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 212785 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 295131252 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 102119988 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 906539563 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6891328 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 27972681 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2218640 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 49279009 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 483149 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 980928941 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4318000809 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1001835244 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 34457090 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 677669366 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.258520 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.215526 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 75794919 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 258105460 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 277738151 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 62003234 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4027602 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 64856939 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 14426 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 924580293 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 10545635 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4027602 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 118744370 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 157469679 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 209680 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 295125429 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 102092606 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 906546743 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6881182 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 27980774 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2218296 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 49244088 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 491152 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 980952632 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4318034270 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1001843328 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 34457465 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 106150711 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 106174402 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 6852 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6840 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 138234074 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 271880895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 160585540 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 6163609 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 12157039 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 899825913 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 12585 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 860027802 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 9216351 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 111113540 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 244391790 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 431 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 677531262 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.269355 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.103879 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 6837 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 138250974 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 271864033 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 160594184 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 6150346 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12039275 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 899826395 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 12582 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 860048195 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 9222152 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 111114019 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 244270336 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 428 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 677669366 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.269127 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.103925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 215443123 31.80% 31.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 182412778 26.92% 58.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 173833847 25.66% 84.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 93421038 13.79% 98.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12418164 1.83% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2312 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 215576710 31.81% 31.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 182398349 26.92% 58.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 173866168 25.66% 84.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 93397486 13.78% 98.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12428213 1.83% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2440 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 677531262 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 677669366 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 66604023 24.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18144 0.01% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 24.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.23% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 132902314 47.88% 72.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 66436214 23.93% 96.05% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 5673709 2.04% 98.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 5298999 1.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 66592795 23.99% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18143 0.01% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 23.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636888 0.23% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 24.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 132895197 47.87% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 66486163 23.95% 96.04% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 5670687 2.04% 98.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 5308776 1.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413088657 48.03% 48.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5187663 0.60% 48.64% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413112342 48.03% 48.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5187450 0.60% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 48.64% # Type of FU issued @@ -596,91 +599,91 @@ system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.64% # Ty system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 48.64% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 637528 0.07% 48.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.71% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 3187674 0.37% 49.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 2550152 0.30% 49.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.37% 49.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 2550158 0.30% 49.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478195 1.33% 50.71% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478201 1.33% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.71% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 259646328 30.19% 80.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 153400482 17.84% 98.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 7019166 0.82% 99.55% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 3831957 0.45% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 259635092 30.19% 80.90% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 153408617 17.84% 98.74% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 7019173 0.82% 99.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 3831959 0.45% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 860027802 # Type of FU issued -system.cpu.iq.rate 1.268482 # Inst issue rate -system.cpu.iq.fu_busy_cnt 277570292 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.322746 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2621725269 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 980329256 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 820080739 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 62648240 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 30641595 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 24878674 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1100471505 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 37126589 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 13986954 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 860048195 # Type of FU issued +system.cpu.iq.rate 1.268248 # Inst issue rate +system.cpu.iq.fu_busy_cnt 277608649 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.322783 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2621941266 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 980329396 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820105906 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 62655291 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 30642249 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 24878687 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1100523479 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 37133365 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 13978556 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 19639957 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 122 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18816 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 31605044 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 19623095 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 150 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18653 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 31613688 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1918903 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17949 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 1918749 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18225 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4021011 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 10591594 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7946 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 899848641 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 4027602 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 10592950 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5943 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 899848973 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 271880895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 160585540 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 6845 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 969 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5082 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18816 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3295133 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3290188 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6585321 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 850172394 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 263373871 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9855408 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 271864033 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 160594184 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6842 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 932 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3107 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18653 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3297561 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3294434 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6591995 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 850188945 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 263367686 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9859250 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10143 # number of nop insts executed -system.cpu.iew.exec_refs 416062863 # number of memory reference insts executed -system.cpu.iew.exec_branches 143380865 # Number of branches executed -system.cpu.iew.exec_stores 152688992 # Number of stores executed -system.cpu.iew.exec_rate 1.253946 # Inst execution rate -system.cpu.iew.wb_sent 846295545 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 844959413 # cumulative count of insts written-back -system.cpu.iew.wb_producers 486195731 # num instructions producing a value -system.cpu.iew.wb_consumers 804663900 # num instructions consuming a value -system.cpu.iew.wb_rate 1.246257 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.604222 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 103166103 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 9996 # number of nop insts executed +system.cpu.iew.exec_refs 416059985 # number of memory reference insts executed +system.cpu.iew.exec_branches 143387028 # Number of branches executed +system.cpu.iew.exec_stores 152692299 # Number of stores executed +system.cpu.iew.exec_rate 1.253710 # Inst execution rate +system.cpu.iew.wb_sent 846316526 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 844984593 # cumulative count of insts written-back +system.cpu.iew.wb_producers 486213090 # num instructions producing a value +system.cpu.iew.wb_consumers 804713496 # num instructions consuming a value +system.cpu.iew.wb_rate 1.246035 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.604206 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 103170323 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 4002664 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 662950558 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.189727 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.047510 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 4009286 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 663080037 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.189495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.047357 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 372609039 56.20% 56.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 137243840 20.70% 76.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51342182 7.74% 84.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 28218977 4.26% 88.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 14379686 2.17% 91.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14774384 2.23% 93.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7871744 1.19% 94.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6561841 0.99% 95.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29948865 4.52% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 372743600 56.21% 56.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 137229465 20.70% 76.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51343947 7.74% 84.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 28225650 4.26% 88.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 14387181 2.17% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14772519 2.23% 93.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7871150 1.19% 94.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6554658 0.99% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29951867 4.52% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 662950558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 663080037 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654411 # Number of instructions committed system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -730,82 +733,82 @@ system.cpu.commit.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730070 # Class of committed instruction -system.cpu.commit.bw_lim_events 29948865 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 1524889115 # The number of ROB reads -system.cpu.rob.rob_writes 1798376442 # The number of ROB writes -system.cpu.timesIdled 10544 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 466491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 29951867 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 1525019812 # The number of ROB reads +system.cpu.rob.rob_writes 1798395927 # The number of ROB writes +system.cpu.timesIdled 10540 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 469345 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649299 # Number of Instructions Simulated system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.058298 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.058298 # CPI: Total CPI of All Threads -system.cpu.ipc 0.944914 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.944914 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 868460616 # number of integer regfile reads -system.cpu.int_regfile_writes 500698081 # number of integer regfile writes -system.cpu.fp_regfile_reads 30616065 # number of floating regfile reads -system.cpu.fp_regfile_writes 22959495 # number of floating regfile writes -system.cpu.cc_regfile_reads 3322380162 # number of cc regfile reads -system.cpu.cc_regfile_writes 369206587 # number of cc regfile writes -system.cpu.misc_regfile_reads 606831817 # number of misc regfile reads +system.cpu.cpi 1.058518 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.058518 # CPI: Total CPI of All Threads +system.cpu.ipc 0.944717 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.944717 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 868485327 # number of integer regfile reads +system.cpu.int_regfile_writes 500716513 # number of integer regfile writes +system.cpu.fp_regfile_reads 30616072 # number of floating regfile reads +system.cpu.fp_regfile_writes 22959512 # number of floating regfile writes +system.cpu.cc_regfile_reads 3322428373 # number of cc regfile reads +system.cpu.cc_regfile_writes 369236255 # number of cc regfile writes +system.cpu.misc_regfile_reads 606835918 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 2756456 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.910987 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 371049565 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756968 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 134.586098 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 285993000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.910987 # Average occupied blocks per requestor +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 2756526 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.910931 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 371056816 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2757038 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 134.585311 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 286323500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.910931 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999826 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 175 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 176 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 751745414 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 751745414 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 243126159 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 243126159 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127907378 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127907378 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 751754868 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 751754868 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 243133490 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 243133490 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127906319 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127906319 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 3157 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 3157 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 371033537 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 371033537 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 371036694 # number of overall hits -system.cpu.dcache.overall_hits::total 371036694 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2401303 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2401303 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1044099 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1044099 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 371039809 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 371039809 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 371042966 # number of overall hits +system.cpu.dcache.overall_hits::total 371042966 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2398664 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2398664 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1045158 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1045158 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3445402 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3445402 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3446049 # number of overall misses -system.cpu.dcache.overall_misses::total 3446049 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 80431299000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 80431299000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9946595850 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9946595850 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 3443822 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3443822 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3444469 # number of overall misses +system.cpu.dcache.overall_misses::total 3444469 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80554008500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80554008500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9982772350 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9982772350 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90377894850 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90377894850 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90377894850 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90377894850 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 245527462 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 245527462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 90536780850 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 90536780850 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 90536780850 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 90536780850 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 245532154 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 245532154 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3804 # number of SoftPFReq accesses(hits+misses) @@ -814,469 +817,470 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5741 system.cpu.dcache.LoadLockedReq_accesses::total 5741 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 374478939 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 374478939 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 374482743 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 374482743 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009780 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008097 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.008097 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 374483631 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 374483631 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 374487435 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 374487435 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009769 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009769 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008105 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.170084 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000348 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000348 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009201 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009201 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009202 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009202 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33494.856334 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 33494.856334 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9526.487287 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9526.487287 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009196 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009196 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009198 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009198 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33582.864670 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33582.864670 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9551.448059 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9551.448059 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 70000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 70000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26231.451323 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26231.451323 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26226.526335 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26226.526335 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26289.622649 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26289.622649 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26284.684475 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26284.684475 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 336970 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 344610 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 4742 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 4869 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.060734 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 2756456 # number of writebacks -system.cpu.dcache.writebacks::total 2756456 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 365826 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 365826 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 323069 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 323069 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 334 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 113 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 497454087 # Number of tag accesses -system.cpu.icache.tags.data_accesses 497454087 # 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average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8176.443791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8176.443791 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8176.443791 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 85075 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 747 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2929 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 497497160 # Number of tag accesses +system.cpu.icache.tags.data_accesses 497497160 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 245773612 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 245773612 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 245773612 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 245773612 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 245773612 # number of overall hits +system.cpu.icache.overall_hits::total 245773612 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1984230 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1984230 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1984230 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1984230 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1984230 # number of overall misses +system.cpu.icache.overall_misses::total 1984230 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16225163428 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16225163428 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16225163428 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16225163428 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16225163428 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16225163428 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 247757842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 247757842 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 247757842 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 247757842 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 247757842 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 247757842 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008009 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008009 # 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number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 219 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3239 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.045749 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 106.714286 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 1980154 # number of writebacks -system.cpu.icache.writebacks::total 1980154 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3028 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3028 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3028 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3028 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3028 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1551 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3686 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10031 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.026245 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 145605931 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 145605931 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 735798 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 735798 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 3358223 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 407 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1553 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3714 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 9969 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.028076 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.960510 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 145611380 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 145611380 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 735645 # 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mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.202000 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100070.884613 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15917.127072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15917.127072 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 99371.272727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 99371.272727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77203.426124 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77203.426124 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79056.165558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79056.165558 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79082.870819 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77203.426124 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79093.400588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100070.884613 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83526.367856 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9474606 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 4736642 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 643287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 98 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 97 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.202223 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 100271.311655 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15152.597403 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15152.597403 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100987.743331 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100987.743331 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 77019.877676 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 77019.877676 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79090.667279 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79090.667279 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79119.223996 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77019.877676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 79131.106788 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 100271.311655 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83598.193029 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9476008 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 4737217 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 644846 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 94 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 93 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 4016964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 802115 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 4000812 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 230803 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 255056 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 181 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720849 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1980847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036119 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5941666 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8270754 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 14212420 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253492416 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352859136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 606351552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 552356 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 4255808 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 5290172 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.121625 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.326853 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 4017663 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 801995 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 4001539 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 231013 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 255559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 720851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720851 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1981478 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 2036187 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5943305 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8271218 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 14214523 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 253556928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 352868096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 606425024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 553229 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 4266048 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 5291746 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.121883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.327151 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 4646755 87.84% 87.84% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 643416 12.16% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 4646773 87.81% 87.81% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 644972 12.19% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5290172 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 9473913000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5291746 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 9475188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2971268997 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2972215996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4135554476 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4135722477 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 1254210 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 939897 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 1255754 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 941197 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 338998876000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 955532 # Transaction distribution -system.membus.trans_dist::WritebackDirty 66317 # Transaction distribution -system.membus.trans_dist::CleanEvict 230803 # Transaction distribution -system.membus.trans_dist::UpgradeReq 181 # Transaction distribution -system.membus.trans_dist::ReadExReq 1375 # Transaction distribution -system.membus.trans_dist::ReadExResp 1375 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 955534 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2211117 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 2211117 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65486336 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 65486336 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 339069355000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 956694 # Transaction distribution +system.membus.trans_dist::WritebackDirty 66350 # Transaction distribution +system.membus.trans_dist::CleanEvict 231013 # Transaction distribution +system.membus.trans_dist::UpgradeReq 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 1387 # Transaction distribution +system.membus.trans_dist::ReadExResp 1387 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 956696 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2213835 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 2213835 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 65563584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 65563584 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 957090 # Request fanout histogram +system.membus.snoop_fanout::samples 958391 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 957090 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 958391 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 957090 # Request fanout histogram -system.membus.reqLayer0.occupancy 1757256327 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 958391 # Request fanout histogram +system.membus.reqLayer0.occupancy 1760245062 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 5028523066 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5035040414 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index 35c099c69..4f45fd20e 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,80 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.060132 # Number of seconds simulated -sim_ticks 60131512500 # Number of ticks simulated -final_tick 60131512500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.060161 # Number of seconds simulated +sim_ticks 60161166500 # Number of ticks simulated +final_tick 60161166500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 320494 # Simulator instruction rate (inst/s) -host_op_rate 409865 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 271758284 # Simulator tick rate (ticks/s) -host_mem_usage 281048 # Number of bytes of host memory used -host_seconds 221.27 # Real time elapsed on the host +host_inst_rate 318648 # Simulator instruction rate (inst/s) +host_op_rate 407504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 270326146 # Simulator tick rate (ticks/s) +host_mem_usage 281460 # Number of bytes of host memory used +host_seconds 222.55 # Real time elapsed on the host sim_insts 70915150 # Number of instructions simulated sim_ops 90690106 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory -system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 286272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7938560 # Number of bytes read from this memory +system.physmem.bytes_read::total 8224832 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 286272 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 286272 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 124040 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128513 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 4761829 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 132021026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 136782856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 4761829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 4761829 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92120217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92120217 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92120217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 4761829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 132021026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 228903073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128515 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 4758418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 131954888 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 136713307 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 4758418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 4758418 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 92074810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 92074810 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 92074810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 4758418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 131954888 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 228788117 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128513 # Number of read requests accepted system.physmem.writeReqs 86552 # Number of write requests accepted -system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128513 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue -system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side +system.physmem.bytesWritten 5537792 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8224832 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8086 # Per bank write bursts -system.physmem.perBankRdBursts::1 8335 # Per bank write bursts +system.physmem.perBankRdBursts::1 8337 # Per bank write bursts system.physmem.perBankRdBursts::2 8257 # Per bank write bursts system.physmem.perBankRdBursts::3 8155 # Per bank write bursts -system.physmem.perBankRdBursts::4 8301 # Per bank write bursts -system.physmem.perBankRdBursts::5 8413 # Per bank write bursts -system.physmem.perBankRdBursts::6 8070 # Per bank write bursts +system.physmem.perBankRdBursts::4 8300 # Per bank write bursts +system.physmem.perBankRdBursts::5 8411 # Per bank write bursts +system.physmem.perBankRdBursts::6 8071 # Per bank write bursts system.physmem.perBankRdBursts::7 7917 # Per bank write bursts system.physmem.perBankRdBursts::8 8054 # Per bank write bursts -system.physmem.perBankRdBursts::9 7613 # Per bank write bursts +system.physmem.perBankRdBursts::9 7612 # Per bank write bursts system.physmem.perBankRdBursts::10 7771 # Per bank write bursts -system.physmem.perBankRdBursts::11 7825 # Per bank write bursts +system.physmem.perBankRdBursts::11 7824 # Per bank write bursts system.physmem.perBankRdBursts::12 7888 # Per bank write bursts -system.physmem.perBankRdBursts::13 7870 # Per bank write bursts -system.physmem.perBankRdBursts::14 7981 # Per bank write bursts -system.physmem.perBankRdBursts::15 7974 # Per bank write bursts -system.physmem.perBankWrBursts::0 5400 # Per bank write bursts +system.physmem.perBankRdBursts::13 7869 # Per bank write bursts +system.physmem.perBankRdBursts::14 7983 # Per bank write bursts +system.physmem.perBankRdBursts::15 7973 # Per bank write bursts +system.physmem.perBankWrBursts::0 5399 # Per bank write bursts system.physmem.perBankWrBursts::1 5549 # Per bank write bursts -system.physmem.perBankWrBursts::2 5475 # Per bank write bursts +system.physmem.perBankWrBursts::2 5478 # Per bank write bursts system.physmem.perBankWrBursts::3 5349 # Per bank write bursts system.physmem.perBankWrBursts::4 5387 # Per bank write bursts -system.physmem.perBankWrBursts::5 5586 # Per bank write bursts +system.physmem.perBankWrBursts::5 5588 # Per bank write bursts system.physmem.perBankWrBursts::6 5325 # Per bank write bursts system.physmem.perBankWrBursts::7 5260 # Per bank write bursts system.physmem.perBankWrBursts::8 5187 # Per bank write bursts -system.physmem.perBankWrBursts::9 5135 # Per bank write bursts +system.physmem.perBankWrBursts::9 5136 # Per bank write bursts system.physmem.perBankWrBursts::10 5306 # Per bank write bursts system.physmem.perBankWrBursts::11 5279 # Per bank write bursts system.physmem.perBankWrBursts::12 5541 # Per bank write bursts @@ -83,14 +83,14 @@ system.physmem.perBankWrBursts::14 5706 # Pe system.physmem.perBankWrBursts::15 5441 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 60131481000 # Total gap between requests +system.physmem.totGap 60161135000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128515 # Read request sizes (log2) +system.physmem.readPktSize::6 128513 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,11 +98,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 86552 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 116119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 12356 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -145,28 +145,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5355 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -194,115 +194,115 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 258.799568 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.901911 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8565 26.06% 26.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 6426 19.55% 45.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3391 10.32% 55.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2471 7.52% 63.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1617 4.92% 75.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1341 4.08% 79.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1209 3.68% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 418.627483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 258.357746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 362.584215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8602 26.17% 26.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6385 19.42% 45.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3434 10.45% 56.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2432 7.40% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2215 6.74% 70.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1621 4.93% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1317 4.01% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1216 3.70% 82.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5649 17.19% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32871 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5351 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.014390 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 17.652764 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 347.251849 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5349 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads -system.physmem.totQLat 3049168000 # Total ticks spent queuing -system.physmem.totMemAccLat 5458730500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23727.09 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5351 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5351 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.170435 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.160762 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.581098 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4912 91.80% 91.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 3 0.06% 91.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 408 7.62% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 22 0.41% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 5 0.09% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5351 # Writes before turning the bus around for reads +system.physmem.totQLat 3055484500 # Total ticks spent queuing +system.physmem.totMemAccLat 5465009500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23776.61 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 42477.09 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42526.61 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 136.71 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 92.05 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 136.71 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 92.07 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.79 # Data bus utilization in percentage system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing -system.physmem.readRowHits 112228 # Number of row buffer hits during reads -system.physmem.writeRowHits 69923 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes -system.physmem.avgGap 279594.18 # Average gap between requests +system.physmem.avgWrQLen 23.51 # Average write queue length when enqueuing +system.physmem.readRowHits 112270 # Number of row buffer hits during reads +system.physmem.writeRowHits 69886 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.36 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.74 # Row buffer hit rate for writes +system.physmem.avgGap 279734.66 # Average gap between requests system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 123657660 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 65710425 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2502199440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2202561510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 166933440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 5874746040 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 2984525760 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 8651084625 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 23265974460 # Total energy per rank (pJ) -system.physmem_0.averagePower 386.918165 # Core power per rank (mW) -system.physmem_0.totalIdleTime 54864943500 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 285874500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1063428000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34209724750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 7772192000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 3916970750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 12883322500 # Time in different power states -system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2186669910 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 154102560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 5325095040 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 3204580800 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 8848579860 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23042291445 # Total energy per rank (pJ) -system.physmem_1.averagePower 383.198268 # Core power per rank (mW) -system.physmem_1.totalIdleTime 54933017000 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 256278500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 34910026000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 8345277500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 3889148250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 11677774250 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 14827796 # Number of BP lookups -system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9662877 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits +system.physmem_0.writeEnergy 226208700 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2513877600.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2171898930 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 163742880 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 5875439160 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 3027961440 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 8657105625 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 23294071200 # Total energy per rank (pJ) +system.physmem_0.averagePower 387.194467 # Core power per rank (mW) +system.physmem_0.totalIdleTime 54970200750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 277627750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1068464000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34200521750 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 7885291750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 3844571250 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 12884690000 # Time in different power states +system.physmem_1.actEnergy 111105540 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 59035020 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 449634360 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 225467460 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2466550320.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2149128000 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 155904480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 5311061070 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 3203698560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 8880552330 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23012901840 # Total energy per rank (pJ) +system.physmem_1.averagePower 382.520865 # Core power per rank (mW) +system.physmem_1.totalIdleTime 55040293250 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 259491500 # Time in different power states +system.physmem_1.memoryStateTime::REF 1048576000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 35050414500 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 8342978750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 3812745000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 11646960750 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 14829931 # Number of BP lookups +system.cpu.branchPred.condPredicted 9922625 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 344341 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9711925 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6581090 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 68.011846 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1720082 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 67.762982 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1720914 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 175731 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 158482 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 17249 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 24894 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -332,7 +332,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -362,7 +362,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -392,7 +392,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -423,16 +423,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 120263025 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 120322333 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915150 # Number of instructions committed system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1183243 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.695872 # CPI: cycles per instruction -system.cpu.ipc 0.589667 # IPC: instructions per cycle +system.cpu.cpi 1.696708 # CPI: cycles per instruction +system.cpu.ipc 0.589376 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction @@ -472,338 +472,338 @@ system.cpu.op_class_0::FloatMemWrite 32 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 90690106 # Class of committed instruction -system.cpu.tickCycles 98355658 # Number of cycles that the object actually ticked -system.cpu.idleCycles 21907367 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 156451 # number of replacements -system.cpu.dcache.tags.tagsinuse 4067.127626 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42637298 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.575177 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127626 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy +system.cpu.tickCycles 98402849 # Number of cycles that the object actually ticked +system.cpu.idleCycles 21919484 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 156448 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.144261 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42640706 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.601368 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 880402500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.144261 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.992955 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.992955 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3045 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86034719 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86034719 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 22880155 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22880155 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 86041472 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86041472 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 22883524 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22883524 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19642139 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19642139 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83205 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83205 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42522297 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42522297 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42605460 # number of overall hits -system.cpu.dcache.overall_hits::total 42605460 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses -system.cpu.dcache.overall_misses::total 299788 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839905000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1839905000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545313000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18545313000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20385218000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20385218000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20385218000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20385218000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22927401 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22927401 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42525663 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42525663 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42608868 # number of overall hits +system.cpu.dcache.overall_hits::total 42608868 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 47232 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 47232 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 207762 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 207762 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 44764 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 44764 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 254994 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 254994 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 299758 # number of overall misses +system.cpu.dcache.overall_misses::total 299758 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1840606500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1840606500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18547852000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18547852000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20388458500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20388458500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20388458500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20388458500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22930756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22930756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 127969 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 127969 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42777302 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42777302 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42905248 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42905248 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 42780657 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42780657 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42908626 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42908626 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002060 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002060 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38943.085129 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38943.085129 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.584249 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.584249 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.463912 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 79940.463912 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.779137 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67998.779137 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349803 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.349803 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005960 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005960 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38969.480437 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 38969.480437 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89274.516033 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 89274.516033 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79956.620548 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79956.620548 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68016.394892 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68016.394892 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks -system.cpu.dcache.writebacks::total 128145 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773861500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 773861500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479489000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479489000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253350500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10253350500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12150126500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12150126500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128143 # number of writebacks +system.cpu.dcache.writebacks::total 128143 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17700 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 17700 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100723 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 100723 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 118423 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 118423 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 118423 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 118423 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29532 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 29532 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107039 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107039 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23973 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 23973 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 136571 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 124040 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128514 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8250600500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8250600500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 448924000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 448924000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029137000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029137000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 448924000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10279737500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10728661500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 448924000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10279737500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10728661500 # number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.207219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.207219 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99820.223464 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99820.223464 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93428.788437 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93428.788437 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99820.223464 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82841.999823 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83433.191198 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955895 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098065 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405981 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405981 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.623349 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098065 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772623 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.623349 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80636.842980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80636.842980 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 100340.634779 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 100340.634779 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93413.912163 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93413.912163 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 100340.634779 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82874.375202 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83482.433820 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 406195 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 200065 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7850 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 97176 # Total snoops (count) +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 99127 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 214695 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 43580 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 38926 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 45623 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 53505 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134825 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 612361 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5708928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18475968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 24184896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 97173 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 303340 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.037578 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.190694 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 291971 96.25% 96.25% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11339 3.74% 99.99% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 303340 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 374820500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68448469 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240848435 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 222299 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 93862 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 60131512500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 26198 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 60161166500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 26195 # Transaction distribution system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution -system.membus.trans_dist::CleanEvict 7237 # Transaction distribution -system.membus.trans_dist::ReadExReq 102317 # Transaction distribution -system.membus.trans_dist::ReadExResp 102317 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::CleanEvict 7234 # Transaction distribution +system.membus.trans_dist::ReadExReq 102318 # Transaction distribution +system.membus.trans_dist::ReadExResp 102318 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 26195 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 350812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13764160 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 128515 # Request fanout histogram +system.membus.snoop_fanout::samples 128513 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 128513 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 128515 # Request fanout histogram -system.membus.reqLayer0.occupancy 588249500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 128513 # Request fanout histogram +system.membus.reqLayer0.occupancy 588234000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 677382500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 677366750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index ad340b529..79d31fb69 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.038007 # Number of seconds simulated -sim_ticks 38007342000 # Number of ticks simulated -final_tick 38007342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.037944 # Number of seconds simulated +sim_ticks 37944194500 # Number of ticks simulated +final_tick 37944194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 224949 # Simulator instruction rate (inst/s) -host_op_rate 287684 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120575368 # Simulator tick rate (ticks/s) -host_mem_usage 283980 # Number of bytes of host memory used -host_seconds 315.22 # Real time elapsed on the host +host_inst_rate 220724 # Simulator instruction rate (inst/s) +host_op_rate 282280 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 118113932 # Simulator tick rate (ticks/s) +host_mem_usage 283128 # Number of bytes of host memory used +host_seconds 321.25 # Real time elapsed on the host sim_insts 70907652 # Number of instructions simulated sim_ops 90682607 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 2373952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5705216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6169536 # Number of bytes read from this memory -system.physmem.bytes_read::total 14248704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 2373952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 2373952 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6224192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6224192 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 37093 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 89144 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96399 # Number of read requests responded to by this memory -system.physmem.num_reads::total 222636 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97253 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97253 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 62460353 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 150108261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 162324848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 374893461 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 62460353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 62460353 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 163762886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 163762886 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 163762886 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 62460353 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 150108261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 162324848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 538656347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 222637 # Number of read requests accepted -system.physmem.writeReqs 97253 # Number of write requests accepted -system.physmem.readBursts 222637 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97253 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 14240000 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue -system.physmem.bytesWritten 6222848 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 14248768 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6224192 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 2366464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5687552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6178176 # Number of bytes read from this memory +system.physmem.bytes_read::total 14232192 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 2366464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 2366464 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6224000 # Number of bytes written to this memory +system.physmem.bytes_written::total 6224000 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 36976 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 88868 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96534 # Number of read requests responded to by this memory +system.physmem.num_reads::total 222378 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97250 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97250 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 62366958 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 149892548 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 162822695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 375082201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 62366958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 62366958 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 164030363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 164030363 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 164030363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 62366958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 149892548 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 162822695 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 539112564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 222379 # Number of read requests accepted +system.physmem.writeReqs 97250 # Number of write requests accepted +system.physmem.readBursts 222379 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97250 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 14222400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue +system.physmem.bytesWritten 6222336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 14232256 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6224000 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9656 # Per bank write bursts -system.physmem.perBankRdBursts::1 9952 # Per bank write bursts -system.physmem.perBankRdBursts::2 12608 # Per bank write bursts -system.physmem.perBankRdBursts::3 25349 # Per bank write bursts -system.physmem.perBankRdBursts::4 17405 # Per bank write bursts -system.physmem.perBankRdBursts::5 22083 # Per bank write bursts -system.physmem.perBankRdBursts::6 11752 # Per bank write bursts -system.physmem.perBankRdBursts::7 14068 # Per bank write bursts -system.physmem.perBankRdBursts::8 11731 # Per bank write bursts -system.physmem.perBankRdBursts::9 15466 # Per bank write bursts -system.physmem.perBankRdBursts::10 11740 # Per bank write bursts -system.physmem.perBankRdBursts::11 11331 # Per bank write bursts -system.physmem.perBankRdBursts::12 9464 # Per bank write bursts -system.physmem.perBankRdBursts::13 9568 # Per bank write bursts -system.physmem.perBankRdBursts::14 9844 # Per bank write bursts -system.physmem.perBankRdBursts::15 20483 # Per bank write bursts -system.physmem.perBankWrBursts::0 5965 # Per bank write bursts -system.physmem.perBankWrBursts::1 6210 # Per bank write bursts -system.physmem.perBankWrBursts::2 6157 # Per bank write bursts -system.physmem.perBankWrBursts::3 6128 # Per bank write bursts -system.physmem.perBankWrBursts::4 6115 # Per bank write bursts -system.physmem.perBankWrBursts::5 6243 # Per bank write bursts -system.physmem.perBankWrBursts::6 6020 # Per bank write bursts -system.physmem.perBankWrBursts::7 5952 # Per bank write bursts -system.physmem.perBankWrBursts::8 5952 # Per bank write bursts -system.physmem.perBankWrBursts::9 6130 # Per bank write bursts -system.physmem.perBankWrBursts::10 6213 # Per bank write bursts -system.physmem.perBankWrBursts::11 5918 # Per bank write bursts -system.physmem.perBankWrBursts::12 6006 # Per bank write bursts -system.physmem.perBankWrBursts::13 6051 # Per bank write bursts -system.physmem.perBankWrBursts::14 6145 # Per bank write bursts -system.physmem.perBankWrBursts::15 6027 # Per bank write bursts +system.physmem.perBankRdBursts::0 9631 # Per bank write bursts +system.physmem.perBankRdBursts::1 9947 # Per bank write bursts +system.physmem.perBankRdBursts::2 12518 # Per bank write bursts +system.physmem.perBankRdBursts::3 24674 # Per bank write bursts +system.physmem.perBankRdBursts::4 17362 # Per bank write bursts +system.physmem.perBankRdBursts::5 22065 # Per bank write bursts +system.physmem.perBankRdBursts::6 11751 # Per bank write bursts +system.physmem.perBankRdBursts::7 14087 # Per bank write bursts +system.physmem.perBankRdBursts::8 11655 # Per bank write bursts +system.physmem.perBankRdBursts::9 16110 # Per bank write bursts +system.physmem.perBankRdBursts::10 11699 # Per bank write bursts +system.physmem.perBankRdBursts::11 11328 # Per bank write bursts +system.physmem.perBankRdBursts::12 9447 # Per bank write bursts +system.physmem.perBankRdBursts::13 9546 # Per bank write bursts +system.physmem.perBankRdBursts::14 9858 # Per bank write bursts +system.physmem.perBankRdBursts::15 20547 # Per bank write bursts +system.physmem.perBankWrBursts::0 5941 # Per bank write bursts +system.physmem.perBankWrBursts::1 6221 # Per bank write bursts +system.physmem.perBankWrBursts::2 6116 # Per bank write bursts +system.physmem.perBankWrBursts::3 6136 # Per bank write bursts +system.physmem.perBankWrBursts::4 6032 # Per bank write bursts +system.physmem.perBankWrBursts::5 6294 # Per bank write bursts +system.physmem.perBankWrBursts::6 6000 # Per bank write bursts +system.physmem.perBankWrBursts::7 5967 # Per bank write bursts +system.physmem.perBankWrBursts::8 5964 # Per bank write bursts +system.physmem.perBankWrBursts::9 6073 # Per bank write bursts +system.physmem.perBankWrBursts::10 6219 # Per bank write bursts +system.physmem.perBankWrBursts::11 5919 # Per bank write bursts +system.physmem.perBankWrBursts::12 6077 # Per bank write bursts +system.physmem.perBankWrBursts::13 6073 # Per bank write bursts +system.physmem.perBankWrBursts::14 6160 # Per bank write bursts +system.physmem.perBankWrBursts::15 6032 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 38007330500 # Total gap between requests +system.physmem.totGap 37944183500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 222637 # Read request sizes (log2) +system.physmem.readPktSize::6 222379 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97253 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 112108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 59931 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 10934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5238 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4622 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 42 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97250 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 111691 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15678 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 47 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -149,36 +149,36 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1871 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6446 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7735 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7923 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 245 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see @@ -198,119 +198,119 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 132899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 153.968593 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.497917 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 209.528989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 82983 62.44% 62.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 32243 24.26% 86.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6367 4.79% 91.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2726 2.05% 93.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1184 0.89% 94.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1005 0.76% 95.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 875 0.66% 95.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 807 0.61% 96.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4709 3.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 132899 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 37.820840 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 210.672420 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5878 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 132661 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 154.093818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.620444 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 209.524421 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 82661 62.31% 62.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 32331 24.37% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6343 4.78% 91.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2828 2.13% 93.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1153 0.87% 94.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1000 0.75% 95.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 785 0.59% 95.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 836 0.63% 96.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4724 3.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 132661 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5873 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 37.833986 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 211.191475 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5868 99.91% 99.91% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5882 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.528392 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.490234 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.186972 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4697 79.85% 79.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 46 0.78% 80.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 744 12.65% 93.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 191 3.25% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 91 1.55% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 73 1.24% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.34% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 15 0.26% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5882 # Writes before turning the bus around for reads -system.physmem.totQLat 8329547257 # Total ticks spent queuing -system.physmem.totMemAccLat 12501422257 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1112500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37436.00 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4999.98 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56185.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 374.66 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 163.73 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 374.90 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 163.76 # Average system write bandwidth in MiByte/s +system.physmem.rdPerTurnAround::total 5873 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.554401 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.514141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.221324 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4642 79.04% 79.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 60 1.02% 80.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 721 12.28% 92.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 237 4.04% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 117 1.99% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 0.85% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 21 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.17% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 9 0.15% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads +system.physmem.totQLat 8400725955 # Total ticks spent queuing +system.physmem.totMemAccLat 12567444705 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1111125000 # Total ticks spent in databus transfers +system.physmem.avgQLat 37802.79 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 56552.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 163.99 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 375.08 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 164.03 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.21 # Data bus utilization in percentage system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.63 # Average write queue length when enqueuing -system.physmem.readRowHits 157173 # Number of row buffer hits during reads -system.physmem.writeRowHits 29653 # Number of row buffer hits during writes -system.physmem.readRowHitRate 70.64 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 30.49 # Row buffer hit rate for writes -system.physmem.avgGap 118813.75 # Average gap between requests -system.physmem.pageHitRate 58.43 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 507596880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 269771370 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 877313220 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 254683800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3009892080.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2962459860 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75632160 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 13054365150 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 948417120 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 77983215 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 22038660255 # Total energy per rank (pJ) -system.physmem_0.averagePower 579.852702 # Core power per rank (mW) -system.physmem_0.totalIdleTime 31313307761 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 43781047 # Time in different power states -system.physmem_0.memoryStateTime::REF 1273526000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 214718250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 2469720434 # Time in different power states -system.physmem_0.memoryStateTime::ACT 5376727192 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 28628869077 # Time in different power states -system.physmem_1.actEnergy 441337680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 234557565 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 711336780 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 252841140 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2899256880.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2760551040 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 73978560 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 11934955830 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1428119040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 493845795 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 21231004530 # Total energy per rank (pJ) -system.physmem_1.averagePower 558.602674 # Core power per rank (mW) -system.physmem_1.totalIdleTime 31760586804 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 51273339 # Time in different power states -system.physmem_1.memoryStateTime::REF 1226918000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 1868150750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3718457459 # Time in different power states -system.physmem_1.memoryStateTime::ACT 4968563857 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 26173978595 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 17074531 # Number of BP lookups -system.cpu.branchPred.condPredicted 11460402 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 598628 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9274722 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7374340 # Number of BTB hits +system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing +system.physmem.readRowHits 156951 # Number of row buffer hits during reads +system.physmem.writeRowHits 29827 # Number of row buffer hits during writes +system.physmem.readRowHitRate 70.63 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 30.67 # Row buffer hit rate for writes +system.physmem.avgGap 118713.21 # Average gap between requests +system.physmem.pageHitRate 58.46 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 506618700 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 269259045 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 871329900 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 254250540 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3004974960.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2939010630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75129120 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12925802790 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 1053663840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 77310705 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 21977801430 # Total energy per rank (pJ) +system.physmem_0.averagePower 579.213801 # Core power per rank (mW) +system.physmem_0.totalIdleTime 31303061618 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 43527335 # Time in different power states +system.physmem_0.memoryStateTime::REF 1271434000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 212368250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 2743799817 # Time in different power states +system.physmem_0.memoryStateTime::ACT 5326073297 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 28346991801 # Time in different power states +system.physmem_1.actEnergy 440652240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 234189450 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 715349460 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 253258740 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2887578720.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2772991290 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 73095360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 11918051910 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1378656480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 511952955 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 21185918985 # Total energy per rank (pJ) +system.physmem_1.averagePower 558.344142 # Core power per rank (mW) +system.physmem_1.totalIdleTime 31672221792 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 50102341 # Time in different power states +system.physmem_1.memoryStateTime::REF 1221978000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 1946071250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3589983863 # Time in different power states +system.physmem_1.memoryStateTime::ACT 4999892367 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 26136166679 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 17059712 # Number of BP lookups +system.cpu.branchPred.condPredicted 11436495 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 610883 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9177884 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7343978 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 79.510092 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1855435 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101567 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 233050 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 195925 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 37125 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 22231 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 80.018205 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1859096 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101568 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 235599 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 198019 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 37580 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 22235 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -400,7 +400,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -431,241 +431,241 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 76014685 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 75888390 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5565404 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87125388 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17074531 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9425700 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 66120510 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1223729 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 11256 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 48 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 32224 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22440736 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 69274 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 72341306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.522198 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.331033 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 5573583 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 87028801 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17059712 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9401093 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 65975948 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1248205 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 11552 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 20 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 32118 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22429818 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 69336 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 72217323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.523317 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.330813 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 27150688 37.53% 37.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8169627 11.29% 48.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9114831 12.60% 61.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27906160 38.58% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 27066857 37.48% 37.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8167411 11.31% 48.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9106696 12.61% 61.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27876359 38.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 72341306 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.224621 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.146165 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8942287 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 26299816 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30976482 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5677371 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 445350 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3133946 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168438 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 100318297 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2804928 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 445350 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13582767 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 11480611 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 882043 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 31792045 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14158490 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 98346425 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 855389 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4229008 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 68182 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4663621 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5443965 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103273055 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 453619684 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 114297516 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 686 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 72217323 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.224800 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.146800 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8951903 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 26171728 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30965562 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5674558 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 453572 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6946604 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 172649 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 100221832 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2852875 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 453572 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13609160 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 11386876 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 864961 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 31760902 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14141852 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 98228803 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 864073 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 4236637 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 68346 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4658326 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5438830 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103135317 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 453117590 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 114171014 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 768 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9643686 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18991 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19021 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12815345 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24159121 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21761593 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1442839 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2330212 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 97411129 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34857 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94489103 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 595557 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6763379 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 17995254 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1071 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 72341306 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.306157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.170975 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9505948 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 19046 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 19073 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12792135 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24137829 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21734716 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1433415 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2312086 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 97293576 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34871 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94397579 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 595173 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6645840 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 17792691 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1085 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 72217323 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.307132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.170641 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24199109 33.45% 33.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17470195 24.15% 57.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17034708 23.55% 81.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11601119 16.04% 97.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2034740 2.81% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1435 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24111122 33.39% 33.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17469676 24.19% 57.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17013658 23.56% 81.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11592271 16.05% 97.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2029206 2.81% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1390 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 72341306 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 72217323 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6739464 22.68% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 40 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11065982 37.24% 59.92% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 11909373 40.08% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 33 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6732689 22.67% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 34 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11048676 37.21% 59.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 11914326 40.12% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 49 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49308872 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 86547 0.09% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 32 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 13 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.28% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23960981 25.36% 77.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21132544 22.37% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 62 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49269666 52.19% 52.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 86409 0.09% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23933468 25.35% 77.64% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21107870 22.36% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 70 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94489103 # Type of FU issued -system.cpu.iq.rate 1.243037 # Inst issue rate -system.cpu.iq.fu_busy_cnt 29714913 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.314480 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 291629642 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 104220574 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93205627 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 340 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 544 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 99 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124203819 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 197 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1369166 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 94397579 # Type of FU issued +system.cpu.iq.rate 1.243900 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29695795 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.314582 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 291303077 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 103985333 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93134762 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 690 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 124093153 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1368431 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1292859 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2033 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11913 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1205855 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1271567 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1549 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11881 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1178978 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 148706 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 187344 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 147641 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 185447 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 445350 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 625818 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1199933 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97461708 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 453572 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 612952 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1120138 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97344492 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24159121 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21761593 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18937 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1609 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1195657 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11913 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 250763 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 222991 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 473754 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93695211 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23697676 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 793892 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24137829 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21734716 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18951 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1593 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1115880 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11881 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 249751 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 231660 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 481411 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93615083 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23674361 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 782496 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15722 # number of nop insts executed -system.cpu.iew.exec_refs 44622526 # number of memory reference insts executed -system.cpu.iew.exec_branches 14207940 # Number of branches executed -system.cpu.iew.exec_stores 20924850 # Number of stores executed -system.cpu.iew.exec_rate 1.232594 # Inst execution rate -system.cpu.iew.wb_sent 93313259 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93205726 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44957522 # num instructions producing a value -system.cpu.iew.wb_consumers 76634731 # num instructions consuming a value -system.cpu.iew.wb_rate 1.226154 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.586647 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 5905401 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 16045 # number of nop insts executed +system.cpu.iew.exec_refs 44580255 # number of memory reference insts executed +system.cpu.iew.exec_branches 14200394 # Number of branches executed +system.cpu.iew.exec_stores 20905894 # Number of stores executed +system.cpu.iew.exec_rate 1.233589 # Inst execution rate +system.cpu.iew.wb_sent 93237318 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93134858 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44916796 # num instructions producing a value +system.cpu.iew.wb_consumers 76568590 # num instructions consuming a value +system.cpu.iew.wb_rate 1.227261 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.586622 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 5786029 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 432114 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 71383083 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.270443 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.106463 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 440353 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 71261477 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.272611 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.107279 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 37916370 53.12% 53.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16693361 23.39% 76.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4299601 6.02% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4172974 5.85% 88.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1943479 2.72% 91.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1233650 1.73% 92.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 737671 1.03% 93.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 579334 0.81% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3806643 5.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 37792643 53.03% 53.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16691471 23.42% 76.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4304606 6.04% 82.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4169247 5.85% 88.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1943443 2.73% 91.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1235947 1.73% 92.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 743394 1.04% 93.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579944 0.81% 94.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3800782 5.33% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 71383083 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 71261477 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913204 # Number of instructions committed system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -715,552 +715,552 @@ system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction -system.cpu.commit.bw_lim_events 3806643 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 164144701 # The number of ROB reads -system.cpu.rob.rob_writes 194146843 # The number of ROB writes -system.cpu.timesIdled 54077 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3673379 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3800782 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 163909584 # The number of ROB reads +system.cpu.rob.rob_writes 193905843 # The number of ROB writes +system.cpu.timesIdled 54309 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3671067 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907652 # Number of Instructions Simulated system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.072024 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.072024 # CPI: Total CPI of All Threads -system.cpu.ipc 0.932815 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.932815 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 101986551 # number of integer regfile reads -system.cpu.int_regfile_writes 56614441 # number of integer regfile writes -system.cpu.fp_regfile_reads 62 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes -system.cpu.cc_regfile_reads 345121100 # number of cc regfile reads -system.cpu.cc_regfile_writes 38758964 # number of cc regfile writes -system.cpu.misc_regfile_reads 44102244 # number of misc regfile reads +system.cpu.cpi 1.070243 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.070243 # CPI: Total CPI of All Threads +system.cpu.ipc 0.934368 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.934368 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 101911048 # number of integer regfile reads +system.cpu.int_regfile_writes 56566498 # number of integer regfile writes +system.cpu.fp_regfile_reads 60 # number of floating regfile reads +system.cpu.fp_regfile_writes 50 # number of floating regfile writes +system.cpu.cc_regfile_reads 344842465 # number of cc regfile reads +system.cpu.cc_regfile_writes 38739142 # number of cc regfile writes +system.cpu.misc_regfile_reads 44068796 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 484796 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.868688 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40338903 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485308 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.120210 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 154723500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.868688 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997790 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997790 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 484861 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.868864 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40324171 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485373 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.078727 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 154340500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.868864 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84466908 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84466908 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 21416602 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21416602 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18830761 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18830761 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60264 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60264 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 15306 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 15306 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 84436477 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84436477 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 21401665 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21401665 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18831129 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18831129 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60098 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60098 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 15305 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 15305 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40247363 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40247363 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40307627 # number of overall hits -system.cpu.dcache.overall_hits::total 40307627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 563583 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 563583 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1019140 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1019140 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 68608 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 68608 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 617 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 617 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1582723 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1582723 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1651331 # number of overall misses -system.cpu.dcache.overall_misses::total 1651331 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14467064000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14467064000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14294982430 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14294982430 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6393500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6393500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28762046430 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28762046430 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28762046430 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28762046430 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 21980185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 21980185 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40232794 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40232794 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40292892 # number of overall hits +system.cpu.dcache.overall_hits::total 40292892 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 563103 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 563103 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1018772 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1018772 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 68943 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 68943 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1581875 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1581875 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1650818 # number of overall misses +system.cpu.dcache.overall_misses::total 1650818 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14421291500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14421291500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14222478926 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14222478926 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5900000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5900000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28643770426 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28643770426 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28643770426 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28643770426 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 21964768 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 21964768 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128872 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128872 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 129041 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 129041 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41830086 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41830086 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41958958 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41958958 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025641 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.025641 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051342 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051342 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.532373 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.532373 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038749 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038749 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037837 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037837 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.039356 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.039356 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25669.801964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25669.801964 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14026.514934 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14026.514934 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10362.236629 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10362.236629 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18172.508032 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18172.508032 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17417.493180 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17417.493180 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2976739 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 131356 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.800000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.661614 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 484796 # number of writebacks -system.cpu.dcache.writebacks::total 484796 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 264511 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 264511 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870576 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 870576 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 617 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 617 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1135087 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1135087 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1135087 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1135087 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299072 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299072 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148564 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148564 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37686 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37686 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 447636 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 447636 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485322 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485322 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7113004000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7113004000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2350412971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2350412971 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001432500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2001432500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9463416971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9463416971 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11464849471 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11464849471 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013606 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013606 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007484 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292430 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292430 # 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Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.336563 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996751 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996751 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu.dcache.demand_accesses::cpu.data 41814669 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41814669 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41943710 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41943710 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025637 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025637 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051324 # 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average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13960.414034 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 13960.414034 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9546.925566 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9546.925566 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18107.480317 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18107.480317 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17351.258846 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17351.258846 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 104 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2957939 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 15 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 131286 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.933333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 22.530498 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 484861 # number of writebacks +system.cpu.dcache.writebacks::total 484861 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263994 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 263994 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 870189 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 870189 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1134183 # 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mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23737.577271 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23737.577271 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15719.641339 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15719.641339 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53095.317681 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53095.317681 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21076.531341 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21076.531341 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23563.100102 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23563.100102 # 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Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 332 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 333 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45207041 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45207041 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 22103280 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22103280 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22103280 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22103280 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22103280 # number of overall hits -system.cpu.icache.overall_hits::total 22103280 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 337250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 337250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 337250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 337250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 337250 # number of overall misses -system.cpu.icache.overall_misses::total 337250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5803062852 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5803062852 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5803062852 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5803062852 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5803062852 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5803062852 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22440530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22440530 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22440530 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22440530 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22440530 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22440530 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015029 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015029 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015029 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015029 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015029 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17207.006233 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17207.006233 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17207.006233 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17207.006233 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17207.006233 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 559762 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 94 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 25894 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.617440 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 325456 # number of writebacks -system.cpu.icache.writebacks::total 325456 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 11268 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 11268 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 11268 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5371171413 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5371171413 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5371171413 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5371171413 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014526 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014526 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16476.895697 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16476.895697 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16476.895697 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16476.895697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16476.895697 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16476.895697 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 822258 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 825535 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2876 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2921107000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7132823500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10309951422 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20363881922 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.056940 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.056940 # 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average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78729.592387 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79664.569984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79664.569984 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79861.016493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78729.592387 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80331.817060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 88935.087621 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84186.597194 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 1621556 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 810285 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80433 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 18616 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18570 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 46 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 662693 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 357682 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 549823 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 28326 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 146207 # Transaction distribution +system.cpu.l2cache.overall_mshr_miss_rate::total 0.297026 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89620.579120 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15464.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15464.285714 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87021.110573 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87021.110573 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78997.944668 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78997.944668 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79570.072703 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79570.072703 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79891.378283 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78997.944668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84537.774963 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 1620984 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 810002 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80349 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 18528 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18483 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 45 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 662386 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 357113 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 550103 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 28134 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 146171 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 14 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148596 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 325982 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 336712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 977404 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455440 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 2432844 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41691008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62086656 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 103777664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 271801 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 6225152 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 1083090 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.091523 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.288499 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148617 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 325631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 336756 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976352 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455635 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 2431987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41646144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62094976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 103741120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 271569 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 6224896 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 1082573 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091409 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288334 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 984008 90.85% 90.85% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 99036 9.14% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 46 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 983661 90.86% 90.86% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 98867 9.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 45 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1083090 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 1621030000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 1082573 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 1620458000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 489099244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 488577734 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 728047842 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 728149334 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 348230 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 205331 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 347777 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 205067 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 38007342000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 214175 # Transaction distribution -system.membus.trans_dist::WritebackDirty 97253 # Transaction distribution -system.membus.trans_dist::CleanEvict 28326 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 214112 # Transaction distribution +system.membus.trans_dist::WritebackDirty 97250 # Transaction distribution +system.membus.trans_dist::CleanEvict 28134 # Transaction distribution system.membus.trans_dist::UpgradeReq 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 8461 # Transaction distribution -system.membus.trans_dist::ReadExResp 8461 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 214176 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570866 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 570866 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20472896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20472896 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8266 # Transaction distribution +system.membus.trans_dist::ReadExResp 8266 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 214113 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570155 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 570155 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20456192 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 222651 # Request fanout histogram +system.membus.snoop_fanout::samples 222393 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 222651 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 222393 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 222651 # Request fanout histogram -system.membus.reqLayer0.occupancy 835869990 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 222393 # Request fanout histogram +system.membus.reqLayer0.occupancy 835299244 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1175713686 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1174434906 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index c13f099b6..fe9262960 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.150228 # Number of seconds simulated -sim_ticks 1150227786500 # Number of ticks simulated -final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.150356 # Number of seconds simulated +sim_ticks 1150356296500 # Number of ticks simulated +final_tick 1150356296500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 394229 # Simulator instruction rate (inst/s) -host_op_rate 424722 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 293579950 # Simulator tick rate (ticks/s) -host_mem_usage 273524 # Number of bytes of host memory used -host_seconds 3917.94 # Real time elapsed on the host +host_inst_rate 374766 # Simulator instruction rate (inst/s) +host_op_rate 403753 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 279117141 # Simulator tick rate (ticks/s) +host_mem_usage 273688 # Number of bytes of host memory used +host_seconds 4121.41 # Real time elapsed on the host sim_insts 1544563088 # Number of instructions simulated sim_ops 1664032481 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory -system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 132097728 # Number of bytes read from this memory +system.physmem.bytes_read::total 132147968 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory -system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 67851072 # Number of bytes written to this memory +system.physmem.bytes_written::total 67851072 # Number of bytes written to this memory system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2064767 # Number of read requests accepted -system.physmem.writeReqs 1060156 # Number of write requests accepted -system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue -system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 67849984 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1300 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::cpu.data 2064027 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2064812 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1060173 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1060173 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 43673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 114832012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 114875685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 43673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 43673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 58982658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 58982658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 58982658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 43673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 114832012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 173858343 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2064812 # Number of read requests accepted +system.physmem.writeReqs 1060173 # Number of write requests accepted +system.physmem.readBursts 2064812 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1060173 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 132064448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 83520 # Total number of bytes read from write queue +system.physmem.bytesWritten 67849344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132147968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 67851072 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1305 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 128524 # Per bank write bursts -system.physmem.perBankRdBursts::1 125801 # Per bank write bursts -system.physmem.perBankRdBursts::2 122666 # Per bank write bursts -system.physmem.perBankRdBursts::3 124575 # Per bank write bursts -system.physmem.perBankRdBursts::4 123572 # Per bank write bursts -system.physmem.perBankRdBursts::5 123680 # Per bank write bursts -system.physmem.perBankRdBursts::6 124357 # Per bank write bursts +system.physmem.perBankRdBursts::0 128530 # Per bank write bursts +system.physmem.perBankRdBursts::1 125798 # Per bank write bursts +system.physmem.perBankRdBursts::2 122667 # Per bank write bursts +system.physmem.perBankRdBursts::3 124564 # Per bank write bursts +system.physmem.perBankRdBursts::4 123583 # Per bank write bursts +system.physmem.perBankRdBursts::5 123689 # Per bank write bursts +system.physmem.perBankRdBursts::6 124368 # Per bank write bursts system.physmem.perBankRdBursts::7 124965 # Per bank write bursts -system.physmem.perBankRdBursts::8 132488 # Per bank write bursts -system.physmem.perBankRdBursts::9 134781 # Per bank write bursts -system.physmem.perBankRdBursts::10 133246 # Per bank write bursts +system.physmem.perBankRdBursts::8 132503 # Per bank write bursts +system.physmem.perBankRdBursts::9 134776 # Per bank write bursts +system.physmem.perBankRdBursts::10 133237 # Per bank write bursts system.physmem.perBankRdBursts::11 134508 # Per bank write bursts -system.physmem.perBankRdBursts::12 134523 # Per bank write bursts -system.physmem.perBankRdBursts::13 134597 # Per bank write bursts -system.physmem.perBankRdBursts::14 130537 # Per bank write bursts -system.physmem.perBankRdBursts::15 130647 # Per bank write bursts -system.physmem.perBankWrBursts::0 66781 # Per bank write bursts -system.physmem.perBankWrBursts::1 64940 # Per bank write bursts -system.physmem.perBankWrBursts::2 63173 # Per bank write bursts -system.physmem.perBankWrBursts::3 63584 # Per bank write bursts -system.physmem.perBankWrBursts::4 63558 # Per bank write bursts -system.physmem.perBankWrBursts::5 63644 # Per bank write bursts -system.physmem.perBankWrBursts::6 65047 # Per bank write bursts -system.physmem.perBankWrBursts::7 66059 # Per bank write bursts -system.physmem.perBankWrBursts::8 67975 # Per bank write bursts -system.physmem.perBankWrBursts::9 68435 # Per bank write bursts -system.physmem.perBankWrBursts::10 68155 # Per bank write bursts -system.physmem.perBankWrBursts::11 68585 # Per bank write bursts -system.physmem.perBankWrBursts::12 68036 # Per bank write bursts -system.physmem.perBankWrBursts::13 68532 # Per bank write bursts -system.physmem.perBankWrBursts::14 67159 # Per bank write bursts +system.physmem.perBankRdBursts::12 134521 # Per bank write bursts +system.physmem.perBankRdBursts::13 134606 # Per bank write bursts +system.physmem.perBankRdBursts::14 130538 # Per bank write bursts +system.physmem.perBankRdBursts::15 130654 # Per bank write bursts +system.physmem.perBankWrBursts::0 66782 # Per bank write bursts +system.physmem.perBankWrBursts::1 64941 # Per bank write bursts +system.physmem.perBankWrBursts::2 63176 # Per bank write bursts +system.physmem.perBankWrBursts::3 63581 # Per bank write bursts +system.physmem.perBankWrBursts::4 63564 # Per bank write bursts +system.physmem.perBankWrBursts::5 63647 # Per bank write bursts +system.physmem.perBankWrBursts::6 65050 # Per bank write bursts +system.physmem.perBankWrBursts::7 66062 # Per bank write bursts +system.physmem.perBankWrBursts::8 67977 # Per bank write bursts +system.physmem.perBankWrBursts::9 68434 # Per bank write bursts +system.physmem.perBankWrBursts::10 68153 # Per bank write bursts +system.physmem.perBankWrBursts::11 68587 # Per bank write bursts +system.physmem.perBankWrBursts::12 68034 # Per bank write bursts +system.physmem.perBankWrBursts::13 68534 # Per bank write bursts +system.physmem.perBankWrBursts::14 67158 # Per bank write bursts system.physmem.perBankWrBursts::15 66466 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1150227685500 # Total gap between requests +system.physmem.totGap 1150356195500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2064767 # Read request sizes (log2) +system.physmem.readPktSize::6 2064812 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1060156 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1060173 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1919552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 143941 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -145,26 +145,26 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 32043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 57354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 62496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 62733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 62829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 62687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 62667 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 62549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 62604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 62637 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 62796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 62454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 62359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see @@ -194,122 +194,122 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 1927714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.704114 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.833686 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 125.867792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1497696 77.69% 77.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 310699 16.12% 93.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52184 2.71% 96.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20631 1.07% 97.59% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::640-767 7807 0.40% 98.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5185 0.27% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5186 0.27% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15252 0.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1927714 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 62200 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.128826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 23.842942 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 148.982645 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 62161 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 4 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads -system.physmem.totQLat 59946131250 # Total ticks spent queuing -system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 62200 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 62200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.044148 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.013066 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.029999 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 29988 48.21% 48.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1141 1.83% 50.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 29436 47.32% 97.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1609 2.59% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 24 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 62200 # Writes before turning the bus around for reads +system.physmem.totQLat 60011294750 # Total ticks spent queuing +system.physmem.totMemAccLat 98702051000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10317535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29082.19 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47832.19 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 114.80 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 58.98 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 114.88 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 58.98 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 1.36 # Data bus utilization in percentage system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing -system.physmem.readRowHits 775435 # Number of row buffer hits during reads -system.physmem.writeRowHits 420473 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes -system.physmem.avgGap 368081.93 # Average gap between requests +system.physmem.avgWrQLen 24.14 # Average write queue length when enqueuing +system.physmem.readRowHits 775182 # Number of row buffer hits during reads +system.physmem.writeRowHits 420747 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.57 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 39.69 # Row buffer hit rate for writes +system.physmem.avgGap 368115.75 # Average gap between requests system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ) -system.physmem_0.averagePower 468.679083 # Core power per rank (mW) -system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states -system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states -system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 6705024060 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3563778240 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7126890960 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 2697711660 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 71598184320.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47589199680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2602904160 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 242927855970 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 71960703840 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 82354339920 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 539151608970 # Total energy per rank (pJ) +system.physmem_0.averagePower 468.682274 # Core power per rank (mW) +system.physmem_0.totalIdleTime 1039160467250 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 3513710000 # Time in different power states +system.physmem_0.memoryStateTime::REF 30352766000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 319025802500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 187397997250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 77329050000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 532736970750 # Time in different power states +system.physmem_1.actEnergy 7058925300 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3751896390 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7606549020 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ) -system.physmem_1.averagePower 469.746535 # Core power per rank (mW) -system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states -system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states -system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 240019900 # Number of BP lookups -system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits +system.physmem_1.refreshEnergy 71153184960.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 47703954360 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2452947360 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 248582355720 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 68636874240 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 80784488595 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 540590019675 # Total energy per rank (pJ) +system.physmem_1.averagePower 469.932679 # Core power per rank (mW) +system.physmem_1.totalIdleTime 1039304472000 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 3115835000 # Time in different power states +system.physmem_1.memoryStateTime::REF 30156708000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 315425606000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 178743425250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 77779220750 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 545135501500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 240030332 # Number of BP lookups +system.cpu.branchPred.condPredicted 186613747 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14536765 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132238924 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122337864 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.512749 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15662658 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectLookups 538 # Number of indirect predictor lookups. system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. +system.cpu.branchPred.indirectMisses 306 # Number of indirect misses. system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -339,7 +339,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -369,7 +369,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -399,7 +399,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -430,16 +430,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 2300455573 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 2300712593 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563088 # Number of instructions committed system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed -system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 41389188 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.489389 # CPI: cycles per instruction -system.cpu.ipc 0.671416 # IPC: instructions per cycle +system.cpu.cpi 1.489556 # CPI: cycles per instruction +system.cpu.ipc 0.671341 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction @@ -479,16 +479,16 @@ system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 1664032481 # Class of committed instruction -system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked -system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 9220107 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. +system.cpu.tickCycles 1845105384 # Number of cycles that the object actually ticked +system.cpu.idleCycles 455607209 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 9220185 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.806447 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624504262 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9224281 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.702216 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.806447 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -497,43 +497,43 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1277413521 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1277413521 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 454174952 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 454174952 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170329187 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170329187 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits -system.cpu.dcache.overall_hits::total 624493045 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 624504139 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624504139 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624504140 # number of overall hits +system.cpu.dcache.overall_hits::total 624504140 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7333496 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7333496 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2256860 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2256860 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses -system.cpu.dcache.overall_misses::total 9590308 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9590356 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9590356 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9590358 # number of overall misses +system.cpu.dcache.overall_misses::total 9590358 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 208281810000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 208281810000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 119887020500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 119887020500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 328168830500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 328168830500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 328168830500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 328168830500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461508448 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461508448 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) @@ -542,64 +542,64 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 634094495 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 634094495 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 634094498 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 634094498 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.015124 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015124 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015124 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015124 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28401.435005 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28401.435005 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53121.159709 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53121.159709 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34218.628641 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34218.628641 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34218.621505 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34218.621505 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks -system.cpu.dcache.writebacks::total 3670055 # number of writebacks +system.cpu.dcache.writebacks::writebacks 3670078 # number of writebacks +system.cpu.dcache.writebacks::total 3670078 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366027 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 366027 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366076 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366076 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366076 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366076 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333447 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333447 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890833 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890833 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 9224280 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9224280 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9224281 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9224281 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200943921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 200943921500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92449770000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92449770000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293393691500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 293393691500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293393772500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 293393772500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses @@ -610,70 +610,70 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27401.019125 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27401.019125 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48893.672789 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48893.672789 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31806.676673 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31806.676673 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31806.682006 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31806.682006 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 33 # number of replacements -system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 660.481453 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466324528 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 567304.778589 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 660.481453 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322501 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322501 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits -system.cpu.icache.overall_hits::total 466274758 # number of overall hits +system.cpu.icache.tags.tag_accesses 932651522 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932651522 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 466324528 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466324528 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466324528 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466324528 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466324528 # number of overall hits +system.cpu.icache.overall_hits::total 466324528 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses system.cpu.icache.overall_misses::total 822 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 74803000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 74803000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 74803000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 75338000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 75338000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 75338000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 75338000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 75338000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 75338000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466325350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466325350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466325350 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466325350 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466325350 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466325350 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 91001.216545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 91001.216545 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 91001.216545 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91652.068127 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 91652.068127 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 91652.068127 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 91652.068127 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 91652.068127 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -688,38 +688,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 822 system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73981000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 73981000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73981000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 73981000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73981000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 73981000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 74516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 74516000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 74516000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74516000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 74516000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90001.216545 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90001.216545 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 2032334 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31895.837315 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks. +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90652.068127 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90652.068127 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90652.068127 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 90652.068127 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 2032379 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31895.934748 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 16378358 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2065147 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.930844 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 10.372175 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535649 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.929491 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 10.372068 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.532774 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31860.029906 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.972288 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.973384 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.972291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.973387 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 831 # Occupied blocks per task id @@ -727,227 +727,227 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2946 system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7191 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 149613670 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 149613670 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 3670055 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 3670055 # number of WritebackDirty hits +system.cpu.l2cache.tags.tag_accesses 149614963 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 149614963 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 3670078 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 3670078 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1078511 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1078511 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1078495 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1078495 # number of ReadExReq hits system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits system.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081704 # number of ReadSharedReq hits -system.cpu.l2cache.ReadSharedReq_hits::total 6081704 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081752 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 6081752 # number of ReadSharedReq hits system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7160215 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7160252 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7160247 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7160284 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7160215 # number of overall hits -system.cpu.l2cache.overall_hits::total 7160252 # number of overall hits -system.cpu.l2cache.ReadExReq_misses::cpu.data 812323 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 812323 # number of ReadExReq misses +system.cpu.l2cache.overall_hits::cpu.data 7160247 # number of overall hits +system.cpu.l2cache.overall_hits::total 7160284 # number of overall hits +system.cpu.l2cache.ReadExReq_misses::cpu.data 812338 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 812338 # number of ReadExReq misses system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses system.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251665 # number of ReadSharedReq misses -system.cpu.l2cache.ReadSharedReq_misses::total 1251665 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251696 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 1251696 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.inst 785 # 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number of overall MSHR miss cycles system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429619 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429619 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170682 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170682 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.223825 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223760 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.223825 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86346.202566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86346.202566 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82819.108280 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82819.108280 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90729.203101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90729.203101 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82819.108280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 89004.187930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 89001.836487 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18445321 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220230 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 7334270 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 4730251 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 6522313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890833 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890833 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333448 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668513 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27670190 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668747 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 27670424 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825232512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 825287232 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2032334 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 67849984 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11257359 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825238976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 825293696 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2032379 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 67851072 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11257482 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 0.000271 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0.016506 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 11254309 99.97% 99.97% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 11254432 99.97% 99.97% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 3044 0.03% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11257359 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 12892670500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11257482 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 12892771500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13836424993 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 4095962 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 2031307 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 1252444 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution -system.membus.trans_dist::CleanEvict 970949 # Transaction distribution -system.membus.trans_dist::ReadExReq 812323 # Transaction distribution -system.membus.trans_dist::ReadExResp 812323 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 199995072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 1150356296500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 1252474 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1060173 # Transaction distribution +system.membus.trans_dist::CleanEvict 970977 # Transaction distribution +system.membus.trans_dist::ReadExReq 812338 # Transaction distribution +system.membus.trans_dist::ReadExResp 812338 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 1252474 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160774 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6160774 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199999040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 199999040 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 2064767 # Request fanout histogram +system.membus.snoop_fanout::samples 2064812 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2064812 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2064767 # Request fanout histogram -system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2064812 # Request fanout histogram +system.membus.reqLayer0.occupancy 8805297000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 11285202500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 413bb751f..2fc5a813e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.787540 # Number of seconds simulated -sim_ticks 787540181500 # Number of ticks simulated -final_tick 787540181500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.787836 # Number of seconds simulated +sim_ticks 787835965500 # Number of ticks simulated +final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 265954 # Simulator instruction rate (inst/s) -host_op_rate 286525 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 135604104 # Simulator tick rate (ticks/s) -host_mem_usage 328428 # Number of bytes of host memory used -host_seconds 5807.64 # Real time elapsed on the host +host_inst_rate 263266 # Simulator instruction rate (inst/s) +host_op_rate 283629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 134283963 # Simulator tick rate (ticks/s) +host_mem_usage 329624 # Number of bytes of host memory used +host_seconds 5866.94 # Real time elapsed on the host sim_insts 1544563024 # Number of instructions simulated sim_ops 1664032416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 236130432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63765312 # Number of bytes read from this memory -system.physmem.bytes_read::total 299960832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104600704 # Number of bytes written to this memory -system.physmem.bytes_written::total 104600704 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3689538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 996333 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4686888 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1634386 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1634386 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 82647 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 299832869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 80967693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 380883210 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 82647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 82647 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 132819514 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 132819514 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 132819514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 82647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 299832869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 80967693 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 513702723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4686888 # Number of read requests accepted -system.physmem.writeReqs 1634386 # Number of write requests accepted -system.physmem.readBursts 4686888 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1634386 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 299458048 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 502784 # Total number of bytes read from write queue -system.physmem.bytesWritten 104597376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 299960832 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104600704 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7856 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one +system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 65344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 236015808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63804544 # Number of bytes read from this memory +system.physmem.bytes_read::total 299885696 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 65344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 65344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104593152 # Number of bytes written to this memory +system.physmem.bytes_written::total 104593152 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3687747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 996946 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4685714 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1634268 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1634268 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 82941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 299574808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 80987092 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 380644841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 82941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 82941 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 132760062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 132760062 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 132760062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 82941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 299574808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 80987092 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 513404904 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4685714 # Number of read requests accepted +system.physmem.writeReqs 1634268 # Number of write requests accepted +system.physmem.readBursts 4685714 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1634268 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 299374336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 511360 # Total number of bytes read from write queue +system.physmem.bytesWritten 104589440 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 299885696 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104593152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7990 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 28 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 302302 # Per bank write bursts -system.physmem.perBankRdBursts::1 301952 # Per bank write bursts -system.physmem.perBankRdBursts::2 285792 # Per bank write bursts -system.physmem.perBankRdBursts::3 288384 # Per bank write bursts -system.physmem.perBankRdBursts::4 288196 # Per bank write bursts -system.physmem.perBankRdBursts::5 285903 # Per bank write bursts -system.physmem.perBankRdBursts::6 281854 # Per bank write bursts -system.physmem.perBankRdBursts::7 277846 # Per bank write bursts -system.physmem.perBankRdBursts::8 294690 # Per bank write bursts -system.physmem.perBankRdBursts::9 300083 # Per bank write bursts -system.physmem.perBankRdBursts::10 291836 # Per bank write bursts -system.physmem.perBankRdBursts::11 298648 # Per bank write bursts -system.physmem.perBankRdBursts::12 299589 # Per bank write bursts -system.physmem.perBankRdBursts::13 298339 # Per bank write bursts -system.physmem.perBankRdBursts::14 293778 # Per bank write bursts -system.physmem.perBankRdBursts::15 289840 # Per bank write bursts -system.physmem.perBankWrBursts::0 103932 # Per bank write bursts -system.physmem.perBankWrBursts::1 101641 # Per bank write bursts -system.physmem.perBankWrBursts::2 99135 # Per bank write bursts -system.physmem.perBankWrBursts::3 99721 # Per bank write bursts -system.physmem.perBankWrBursts::4 98850 # Per bank write bursts -system.physmem.perBankWrBursts::5 98703 # Per bank write bursts -system.physmem.perBankWrBursts::6 102612 # Per bank write bursts -system.physmem.perBankWrBursts::7 104045 # Per bank write bursts -system.physmem.perBankWrBursts::8 105476 # Per bank write bursts -system.physmem.perBankWrBursts::9 104249 # Per bank write bursts -system.physmem.perBankWrBursts::10 101862 # Per bank write bursts -system.physmem.perBankWrBursts::11 102612 # Per bank write bursts -system.physmem.perBankWrBursts::12 102593 # Per bank write bursts -system.physmem.perBankWrBursts::13 102283 # Per bank write bursts -system.physmem.perBankWrBursts::14 104155 # Per bank write bursts -system.physmem.perBankWrBursts::15 102465 # Per bank write bursts +system.physmem.perBankRdBursts::0 301500 # Per bank write bursts +system.physmem.perBankRdBursts::1 301960 # Per bank write bursts +system.physmem.perBankRdBursts::2 285447 # Per bank write bursts +system.physmem.perBankRdBursts::3 288137 # Per bank write bursts +system.physmem.perBankRdBursts::4 288946 # Per bank write bursts +system.physmem.perBankRdBursts::5 285921 # Per bank write bursts +system.physmem.perBankRdBursts::6 281288 # Per bank write bursts +system.physmem.perBankRdBursts::7 278400 # Per bank write bursts +system.physmem.perBankRdBursts::8 294011 # Per bank write bursts +system.physmem.perBankRdBursts::9 300115 # Per bank write bursts +system.physmem.perBankRdBursts::10 292046 # Per bank write bursts +system.physmem.perBankRdBursts::11 297684 # Per bank write bursts +system.physmem.perBankRdBursts::12 299531 # Per bank write bursts +system.physmem.perBankRdBursts::13 298464 # Per bank write bursts +system.physmem.perBankRdBursts::14 294115 # Per bank write bursts +system.physmem.perBankRdBursts::15 290159 # Per bank write bursts +system.physmem.perBankWrBursts::0 103775 # Per bank write bursts +system.physmem.perBankWrBursts::1 101738 # Per bank write bursts +system.physmem.perBankWrBursts::2 99347 # Per bank write bursts +system.physmem.perBankWrBursts::3 99748 # Per bank write bursts +system.physmem.perBankWrBursts::4 99113 # Per bank write bursts +system.physmem.perBankWrBursts::5 98946 # Per bank write bursts +system.physmem.perBankWrBursts::6 102275 # Per bank write bursts +system.physmem.perBankWrBursts::7 103989 # Per bank write bursts +system.physmem.perBankWrBursts::8 105110 # Per bank write bursts +system.physmem.perBankWrBursts::9 104316 # Per bank write bursts +system.physmem.perBankWrBursts::10 101973 # Per bank write bursts +system.physmem.perBankWrBursts::11 102390 # Per bank write bursts +system.physmem.perBankWrBursts::12 102662 # Per bank write bursts +system.physmem.perBankWrBursts::13 102242 # Per bank write bursts +system.physmem.perBankWrBursts::14 104082 # Per bank write bursts +system.physmem.perBankWrBursts::15 102504 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 787540140500 # Total gap between requests +system.physmem.totGap 787835924500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4686888 # Read request sizes (log2) +system.physmem.readPktSize::6 4685714 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1634386 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2728191 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1051856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 328268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 233236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 157524 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 89904 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 39917 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 24410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4434 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1760 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 828 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1634268 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2727826 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1050681 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 326941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 233426 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 158423 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 90275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 17994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1780 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 895 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -149,42 +149,42 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 24307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 26803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 73031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 93506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 99632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 105756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 106392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 107277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 108481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 109650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 110259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 109107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 24253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 26721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 72860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 84494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 104977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 109635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 109963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 109142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 102277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 4710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see @@ -198,132 +198,134 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4260550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.836056 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.812158 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 102.756680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3400540 79.81% 79.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 663329 15.57% 95.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94665 2.22% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 34624 0.81% 98.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22478 0.53% 98.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12365 0.29% 99.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7339 0.17% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5272 0.12% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19938 0.47% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4260550 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 97975 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.757050 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 99.440701 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 95549 97.52% 97.52% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 1198 1.22% 98.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 700 0.71% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-1023 381 0.39% 99.85% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1279 109 0.11% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1535 28 0.03% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3328-3583 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4259361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.841028 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.814946 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 102.698820 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4259361 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98005 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.729004 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 99.044358 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 95588 97.53% 97.53% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 1180 1.20% 98.74% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 706 0.72% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-1023 397 0.41% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1279 101 0.10% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1791 5 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-2303 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 97975 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 97975 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.681133 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.640632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.211305 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 70258 71.71% 71.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1952 1.99% 73.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 17579 17.94% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 5262 5.37% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1746 1.78% 98.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 657 0.67% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 283 0.29% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 119 0.12% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 69 0.07% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 29 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 11 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 97975 # Writes before turning the bus around for reads -system.physmem.totQLat 162188930459 # Total ticks spent queuing -system.physmem.totMemAccLat 249920780459 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23395160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34662.92 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 98005 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.674761 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.634865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.202481 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 70360 71.79% 71.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1982 2.02% 73.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 17660 18.02% 91.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 5209 5.32% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 1729 1.76% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 596 0.61% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 225 0.23% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 114 0.12% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 71 0.07% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 31 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 17 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98005 # Writes before turning the bus around for reads +system.physmem.totQLat 162836208305 # Total ticks spent queuing +system.physmem.totMemAccLat 250543533305 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23388620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34810.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53412.92 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 380.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 132.82 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 380.88 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 132.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53560.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 380.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 132.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 4.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.99 # Average write queue length when enqueuing -system.physmem.readRowHits 1713351 # Number of row buffer hits during reads -system.physmem.writeRowHits 339452 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 20.77 # Row buffer hit rate for writes -system.physmem.avgGap 124585.67 # Average gap between requests +system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing +system.physmem.readRowHits 1712017 # Number of row buffer hits during reads +system.physmem.writeRowHits 340548 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 20.84 # Row buffer hit rate for writes +system.physmem.avgGap 124657.94 # Average gap between requests system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 15118214580 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8035491255 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16509315060 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 4221095580 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 59433229440.000015 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64449448560 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1619596800 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 222781261830 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 36127794240 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 16128721335 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 444435904680 # Total energy per rank (pJ) -system.physmem_0.averagePower 564.334256 # Core power per rank (mW) -system.physmem_0.totalIdleTime 641954026654 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 1425644900 # Time in different power states -system.physmem_0.memoryStateTime::REF 25162536000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 59321643250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 94080310817 # Time in different power states -system.physmem_0.memoryStateTime::ACT 118997964696 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 488552081837 # Time in different power states -system.physmem_1.actEnergy 15302205240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8133295995 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 16898973420 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 4310127900 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 58889273040.000015 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64896379290 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1612760640 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 219232237770 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 35640720960 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18160779360 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 443087552175 # Total energy per rank (pJ) -system.physmem_1.averagePower 562.622143 # Core power per rank (mW) -system.physmem_1.totalIdleTime 640996653350 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 1453270191 # Time in different power states -system.physmem_1.memoryStateTime::REF 24933432000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 67412776000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 92813399032 # Time in different power states -system.physmem_1.memoryStateTime::ACT 120155386459 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 480771917818 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 286296319 # Number of BP lookups -system.cpu.branchPred.condPredicted 223413056 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14631953 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158681776 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150365310 # Number of BTB hits +system.physmem_0.actEnergy 15118935720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8035889730 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16504816860 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 4222619820 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 59457815040.000015 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64415436660 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1624122240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 222796740750 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 36224267040 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 16152645360 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 444563646270 # Total energy per rank (pJ) +system.physmem_0.averagePower 564.284526 # Core power per rank (mW) +system.physmem_0.totalIdleTime 642315388170 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 1436139102 # Time in different power states +system.physmem_0.memoryStateTime::REF 25173062000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 59398115500 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 94331998561 # Time in different power states +system.physmem_0.memoryStateTime::ACT 118911366978 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 488585283359 # Time in different power states +system.physmem_1.actEnergy 15292958940 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8128385265 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 16894132500 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4307956380 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 58918161120.000015 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 64834688190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1616111040 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 219342669570 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 35641510560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18222503400 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 443208649005 # Total energy per rank (pJ) +system.physmem_1.averagePower 562.564626 # Core power per rank (mW) +system.physmem_1.totalIdleTime 641423107931 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 1455389769 # Time in different power states +system.physmem_1.memoryStateTime::REF 24945910000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 67593570250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 92814429154 # Time in different power states +system.physmem_1.memoryStateTime::ACT 120009883050 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 481016783277 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 286288991 # Number of BP lookups +system.cpu.branchPred.condPredicted 223379889 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14638803 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157014468 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150316303 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.759029 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16643535 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 3038 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 1928 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 1110 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 135 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.734046 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16636731 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3547 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2042 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 1505 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -353,7 +355,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -383,7 +385,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -413,7 +415,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -444,133 +446,133 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 1575080364 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 1575671932 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13929690 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067600144 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286296319 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 167010773 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1546402654 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29288795 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 390 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 943 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656982335 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1574978074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.406414 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.233446 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1546978368 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29302455 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 1029 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656906223 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 925 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1575573272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.405744 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.233501 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492512848 31.27% 31.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465448024 29.55% 60.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101428874 6.44% 67.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515588328 32.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 493163312 31.30% 31.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465492881 29.54% 60.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101391668 6.44% 67.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515525411 32.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1574978074 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.181766 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.312695 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74681637 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 577546655 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849949420 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58156641 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14643721 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42204470 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 713 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2037236907 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52506596 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14643721 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139754890 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 492363005 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 15806 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837855661 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 90344991 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976429927 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26743123 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45374465 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 126519 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1703162 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 29238118 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985901380 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9128373257 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432925820 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1575573272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.181693 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.312107 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74679257 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 578142352 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 849952798 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58148325 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14650540 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 135611620 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 746 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037153887 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52516232 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14650540 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139761664 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 493000122 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16309 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837842196 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 90302441 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976324662 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26749907 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45308958 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 126668 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1624936 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 29276583 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985726338 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127758695 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432766069 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 161 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 311002435 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 176 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 310827393 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 177 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111413296 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542580071 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199306810 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26873371 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 29046971 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1948011764 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857503284 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13502415 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 283979579 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 647409512 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1574978074 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.179384 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.151840 # Number of insts issued each cycle +system.cpu.rename.skidInsts 111376144 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542477238 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199268014 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26870545 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28963209 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947887828 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 229 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857408251 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13517769 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 283855641 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 647022412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 59 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1575573272 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.178878 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151815 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 622116780 39.50% 39.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325952300 20.70% 60.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378187133 24.01% 84.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219716912 13.95% 98.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28998763 1.84% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6186 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 622703787 39.52% 39.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 326030740 20.69% 60.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378156304 24.00% 84.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219671219 13.94% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29004864 1.84% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6358 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1574978074 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1575573272 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166073423 40.98% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 2008 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191445503 47.24% 88.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 47741848 11.78% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166096777 40.98% 40.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2401 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191354081 47.22% 88.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47812478 11.80% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 31 0.00% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138255860 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800923 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138249696 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 803001 0.04% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued @@ -594,90 +596,90 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 34 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532128426 28.65% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186317966 10.03% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 33 0.00% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532063614 28.65% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186291823 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 37 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857503284 # Type of FU issued -system.cpu.iq.rate 1.179307 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405262832 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218176 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5708749627 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2232004447 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805721857 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2262765960 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 156 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17817152 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857408251 # Type of FU issued +system.cpu.iq.rate 1.178804 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405265784 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218189 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5709173052 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2231756417 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805664221 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 288 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 75 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262673874 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17815816 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84273737 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66671 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13339 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24459765 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84170904 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66799 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13274 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24420969 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4534666 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4848313 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4535474 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4852528 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14643721 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25440287 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1476217 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1948012141 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14650540 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25426885 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1470128 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947888203 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542580071 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199306810 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159536 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1315183 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13339 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7701795 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8704622 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16406417 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827836046 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516947496 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29667238 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542477238 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199268014 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 167 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 159099 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1309527 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13274 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7696809 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8718333 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16415142 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827780120 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516898840 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29628131 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 146 # number of nop insts executed -system.cpu.iew.exec_refs 698700973 # number of memory reference insts executed -system.cpu.iew.exec_branches 229547821 # Number of branches executed -system.cpu.iew.exec_stores 181753477 # Number of stores executed -system.cpu.iew.exec_rate 1.160472 # Inst execution rate -system.cpu.iew.wb_sent 1808752239 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805721927 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169243033 # num instructions producing a value -system.cpu.iew.wb_consumers 1689661119 # num instructions consuming a value -system.cpu.iew.wb_rate 1.146432 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.691999 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 258080144 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 698650840 # number of memory reference insts executed +system.cpu.iew.exec_branches 229565077 # Number of branches executed +system.cpu.iew.exec_stores 181752000 # Number of stores executed +system.cpu.iew.exec_rate 1.160000 # Inst execution rate +system.cpu.iew.wb_sent 1808693799 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805664296 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169145221 # num instructions producing a value +system.cpu.iew.wb_consumers 1689395973 # num instructions consuming a value +system.cpu.iew.wb_rate 1.145965 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692049 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 257953466 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14631277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1535484809 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.083718 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.009601 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14638116 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1536081048 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.083297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.009309 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 955186516 62.21% 62.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250636789 16.32% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 110101292 7.17% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55286350 3.60% 89.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29268667 1.91% 91.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 34069623 2.22% 93.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24728092 1.61% 95.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18117164 1.18% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58090316 3.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 955788021 62.22% 62.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250630730 16.32% 78.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110093475 7.17% 85.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55285008 3.60% 89.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29278263 1.91% 91.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34064309 2.22% 93.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24750177 1.61% 95.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18104449 1.18% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58086616 3.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1535484809 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1536081048 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563042 # Number of instructions committed system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -727,78 +729,78 @@ system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction -system.cpu.commit.bw_lim_events 58090316 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 3399506472 # The number of ROB reads -system.cpu.rob.rob_writes 3883723576 # The number of ROB writes -system.cpu.timesIdled 829 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 102290 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 58086616 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 3399979733 # The number of ROB reads +system.cpu.rob.rob_writes 3883469027 # The number of ROB writes +system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 98660 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563024 # Number of Instructions Simulated system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.019758 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.019758 # CPI: Total CPI of All Threads -system.cpu.ipc 0.980625 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.980625 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175817673 # number of integer regfile reads -system.cpu.int_regfile_writes 1261583983 # number of integer regfile writes -system.cpu.fp_regfile_reads 40 # number of floating regfile reads -system.cpu.fp_regfile_writes 52 # number of floating regfile writes -system.cpu.cc_regfile_reads 6965793426 # number of cc regfile reads -system.cpu.cc_regfile_writes 551861251 # number of cc regfile writes -system.cpu.misc_regfile_reads 675850688 # number of misc regfile reads +system.cpu.cpi 1.020141 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.020141 # CPI: Total CPI of All Threads +system.cpu.ipc 0.980257 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.980257 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175723378 # number of integer regfile reads +system.cpu.int_regfile_writes 1261531313 # number of integer regfile writes +system.cpu.fp_regfile_reads 42 # number of floating regfile reads +system.cpu.fp_regfile_writes 57 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965468307 # number of cc regfile reads +system.cpu.cc_regfile_writes 551796531 # number of cc regfile writes +system.cpu.misc_regfile_reads 675796862 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 17003339 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963435 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638067140 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17003851 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.524861 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 82999500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963435 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 17001793 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.963908 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638014747 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17002305 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 81846500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.963908 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335713311 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335713311 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 469350712 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469350712 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168716268 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168716268 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335598455 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335598455 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 469297691 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469297691 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168716899 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168716899 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638066980 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638066980 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638066980 # number of overall hits -system.cpu.dcache.overall_hits::total 638066980 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17417847 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17417847 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3869779 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3869779 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638014590 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638014590 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638014590 # number of overall hits +system.cpu.dcache.overall_hits::total 638014590 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17414213 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17414213 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3869148 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3869148 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21287626 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21287626 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21287628 # number of overall misses -system.cpu.dcache.overall_misses::total 21287628 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 440481080000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 440481080000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157197656848 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157197656848 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 597678736848 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 597678736848 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 597678736848 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 597678736848 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486768559 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486768559 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21283361 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21283361 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21283363 # number of overall misses +system.cpu.dcache.overall_misses::total 21283363 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 440649629000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 440649629000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157410000348 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157410000348 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 389500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 389500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 598059629348 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 598059629348 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 598059629348 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 598059629348 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486711904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486711904 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -807,70 +809,70 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659354606 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659354606 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659354608 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659354608 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022422 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.022422 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659297951 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659297951 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659297953 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659297953 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022419 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022419 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25289.065864 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25289.065864 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40621.869323 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40621.869323 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54375 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54375 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28076.345237 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28076.345237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28076.342599 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28076.342599 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21218402 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3791861 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 939506 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67507 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.584637 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 56.169893 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17003339 # number of writebacks -system.cpu.dcache.writebacks::total 17003339 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151564 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3151564 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132202 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1132202 # number of WriteReq MSHR hits +system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25304.022008 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25304.022008 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40683.375345 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40683.375345 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 97375 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 97375 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28099.867749 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28099.867749 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28099.865108 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28099.865108 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21246265 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3823077 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 940794 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67416 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.583334 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 56.708749 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 17001793 # number of writebacks +system.cpu.dcache.writebacks::total 17001793 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149457 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3149457 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1131591 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1131591 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4283766 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4283766 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4283766 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4283766 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266283 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14266283 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737577 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737577 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14264756 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14264756 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737557 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737557 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17003860 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17003860 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17003861 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17003861 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354100253000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 354100253000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121015069211 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 121015069211 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 17002313 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17002313 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17002314 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17002314 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354315671500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 354315671500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121139018143 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 121139018143 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475115322211 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 475115322211 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475115397211 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 475115397211 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475454689643 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 475454689643 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475454764643 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 475454764643 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses @@ -881,400 +883,400 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24820.778685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24820.778685 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44205.174580 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44205.174580 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24838.537126 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24838.537126 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44250.774739 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44250.774739 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27941.615740 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 27941.615740 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27941.618507 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 27941.618507 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 587 # number of replacements -system.cpu.icache.tags.tagsinuse 445.528749 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656980742 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 611713.912477 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27964.118155 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27964.118155 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27964.120922 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27964.120922 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 591 # number of replacements +system.cpu.icache.tags.tagsinuse 443.744305 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656904625 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 611074.069767 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.528749 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870173 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870173 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 487 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 443.744305 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.866688 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.866688 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.951172 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313965738 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313965738 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 656980742 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656980742 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656980742 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656980742 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656980742 # number of overall hits -system.cpu.icache.overall_hits::total 656980742 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1590 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1590 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1590 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1590 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1590 # number of overall misses -system.cpu.icache.overall_misses::total 1590 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 127348986 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 127348986 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 127348986 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 127348986 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 127348986 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 127348986 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656982332 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656982332 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656982332 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656982332 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656982332 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656982332 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1313813517 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313813517 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 656904625 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656904625 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656904625 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656904625 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656904625 # number of overall hits +system.cpu.icache.overall_hits::total 656904625 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1596 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1596 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1596 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1596 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1596 # number of overall misses +system.cpu.icache.overall_misses::total 1596 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 121940986 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 121940986 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 121940986 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 121940986 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 121940986 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 121940986 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656906221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656906221 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656906221 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656906221 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656906221 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656906221 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80093.701887 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 80093.701887 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 80093.701887 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 80093.701887 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 20708 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 276 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76404.126566 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76404.126566 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76404.126566 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76404.126566 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19802 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 110.737968 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 587 # number of writebacks -system.cpu.icache.writebacks::total 587 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 515 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 515 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 515 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 515 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 515 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 515 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 91881989 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 91881989 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 91881989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 91881989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 91881989 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 91881989 # number of overall MSHR miss cycles +system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 105.893048 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33.600000 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 591 # number of writebacks +system.cpu.icache.writebacks::total 591 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 520 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 520 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 520 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 520 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 520 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 520 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 89957490 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 89957490 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 89957490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 89957490 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 89957490 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 89957490 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85471.617674 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85471.617674 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 11608007 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11635645 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 18478 # number of redundant prefetches already in prefetch queue +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83603.615242 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83603.615242 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 11616550 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11644306 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 18561 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped -system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655443 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.tags.replacements 4648753 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15870.733376 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 13264824 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4664667 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.843681 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfRemovedFull 1 # number of prefetches dropped due to prefetch queue size +system.cpu.l2cache.prefetcher.pfSpanPage 4655502 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.replacements 4647569 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15870.791949 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 13265757 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4663475 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.844608 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15649.436196 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 221.297180 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.955166 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013507 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.968673 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 130 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15784 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4048 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7174 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2624 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1515 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007935 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963379 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 561782498 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 561782498 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.WritebackDirty_hits::writebacks 4829115 # number of WritebackDirty hits -system.cpu.l2cache.WritebackDirty_hits::total 4829115 # number of WritebackDirty hits -system.cpu.l2cache.WritebackClean_hits::writebacks 12153582 # number of WritebackClean hits -system.cpu.l2cache.WritebackClean_hits::total 12153582 # number of WritebackClean hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1756982 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1756982 # number of ReadExReq hits -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11509164 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 419563267345 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_hits::cpu.data 49537 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 49538 # number of overall MSHR hits +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1199044 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 977021 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 977021 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1021 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1021 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709403 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709403 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1021 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3686424 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3687445 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1021 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3686424 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4886489 # number of overall MSHR misses +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84363300436 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 137500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 137500 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98257390500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98257390500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 82266500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 82266500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237433882500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237433882500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 82266500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335691273000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 335773539500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 82266500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335691273000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 420136839936 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356775 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.190062 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.190062 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.216949 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356889 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.948885 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189938 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189938 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.216865 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.287311 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70317.710271 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15200 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15200 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100474.462434 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100474.462434 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82803.834808 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82803.834808 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87483.716582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87483.716582 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90921.729885 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85875.879117 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 34008864 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003947 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21229 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 200156 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200155 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.287383 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70358.802876 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100568.350629 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100568.350629 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80574.436827 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80574.436827 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.283974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.283974 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91058.589213 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85979.286956 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 34005774 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 17002402 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21251 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 202098 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 202097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 14267297 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 6463501 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 12174811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 3014367 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1493474 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFResp 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737628 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266223 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2736 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011077 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 51013813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106304 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176461184 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2176567488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 6142243 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 104601728 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 23147163 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.009565 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.097331 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 14265775 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 6471532 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 12165120 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 3013301 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1495847 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737605 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 14264700 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51006435 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 51009177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176263168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2176369792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 6143430 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 104594048 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 23146806 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.009650 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.097758 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 22925769 99.04% 99.04% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 221393 0.96% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 22923448 99.04% 99.04% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 223357 0.96% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23147163 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 34008359033 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 23146806 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 34005271029 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 24049 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 21045 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1612497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 25505785487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 25503465992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 9335651 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 4669993 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 9333292 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 4668829 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 3710005 # Transaction distribution -system.membus.trans_dist::WritebackDirty 1634386 # Transaction distribution -system.membus.trans_dist::CleanEvict 3014367 # Transaction distribution -system.membus.trans_dist::UpgradeReq 10 # Transaction distribution -system.membus.trans_dist::ReadExReq 976882 # Transaction distribution -system.membus.trans_dist::ReadExResp 976882 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 3710006 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14022538 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14022538 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404561472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 404561472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 3708542 # Transaction distribution +system.membus.trans_dist::WritebackDirty 1634268 # Transaction distribution +system.membus.trans_dist::CleanEvict 3013301 # Transaction distribution +system.membus.trans_dist::UpgradeReq 9 # Transaction distribution +system.membus.trans_dist::ReadExReq 977171 # Transaction distribution +system.membus.trans_dist::ReadExResp 977171 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 3708543 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14019005 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14019005 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404478784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 404478784 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 4686898 # Request fanout histogram +system.membus.snoop_fanout::samples 4685723 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4686898 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 4685723 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4686898 # Request fanout histogram -system.membus.reqLayer0.occupancy 17643111757 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 4685723 # Request fanout histogram +system.membus.reqLayer0.occupancy 17639856241 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 25454576781 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 25447920698 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index f4cf26547..aa0694fe0 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,19 +1,19 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.132539 # Number of seconds simulated -sim_ticks 132538562500 # Number of ticks simulated -final_tick 132538562500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.132570 # Number of seconds simulated +sim_ticks 132570000500 # Number of ticks simulated +final_tick 132570000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 360845 # Simulator instruction rate (inst/s) -host_op_rate 380389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 277544932 # Simulator tick rate (ticks/s) -host_mem_usage 274852 # Number of bytes of host memory used -host_seconds 477.54 # Real time elapsed on the host +host_inst_rate 373440 # Simulator instruction rate (inst/s) +host_op_rate 393666 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 287300012 # Simulator tick rate (ticks/s) +host_mem_usage 274936 # Number of bytes of host memory used +host_seconds 461.43 # Real time elapsed on the host sim_insts 172317810 # Number of instructions simulated sim_ops 181650743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 138240 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory system.physmem.bytes_read::total 247552 # Number of bytes read from this memory @@ -22,14 +22,14 @@ system.physmem.bytes_inst_read::total 138240 # Nu system.physmem.num_reads::cpu.inst 2160 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory system.physmem.num_reads::total 3868 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1043017 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 824756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1867773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1043017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1043017 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1043017 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 824756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1867773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1042770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 824561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1867330 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1042770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1042770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1042770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 824561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1867330 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 3868 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 3868 # Number of DRAM read bursts, including those serviced by the write queue @@ -76,7 +76,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 132538461500 # Total gap between requests +system.physmem.totGap 132569899500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,8 +91,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 239 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -189,24 +189,24 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 928 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 265.103448 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.439776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 277.287318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 274 29.53% 29.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 366 39.44% 68.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 89 9.59% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 6.14% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 24 2.59% 87.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 19 2.05% 89.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 1.94% 91.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 18 1.94% 93.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 63 6.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.513478 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 277.064139 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 273 29.42% 29.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 364 39.22% 68.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 95 10.24% 78.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 53 5.71% 84.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 24 2.59% 87.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 21 2.26% 89.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 18 1.94% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.94% 93.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 62 6.68% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 928 # Bytes accessed per row activation -system.physmem.totQLat 84421250 # Total ticks spent queuing -system.physmem.totMemAccLat 156946250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 82551750 # Total ticks spent queuing +system.physmem.totMemAccLat 155076750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 19340000 # Total ticks spent in databus transfers -system.physmem.avgQLat 21825.56 # Average queueing delay per DRAM burst +system.physmem.avgQLat 21342.23 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 40575.56 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 40092.23 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.87 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.87 # Average system read bandwidth in MiByte/s @@ -221,62 +221,62 @@ system.physmem.readRowHits 2935 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.88 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34265372.67 # Average gap between requests +system.physmem.avgGap 34273500.39 # Average gap between requests system.physmem.pageHitRate 75.88 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2977380 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1582515 # Energy for precharge commands per rank (pJ) +system.physmem_0.actEnergy 2963100 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1574925 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 14822640 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 159806400.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 56564520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 6779040 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 507399750 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 193240800 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 31407910590 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 32351114145 # Total energy per rank (pJ) -system.physmem_0.averagePower 244.088313 # Core power per rank (mW) -system.physmem_0.totalIdleTime 132395468250 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 11004000 # Time in different power states -system.physmem_0.memoryStateTime::REF 67828000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 130780838250 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 503202000 # Time in different power states -system.physmem_0.memoryStateTime::ACT 62983500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1112706750 # Time in different power states -system.physmem_1.actEnergy 3684240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1939245 # Energy for precharge commands per rank (pJ) +system.physmem_0.refreshEnergy 157347840.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56147850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 6612480 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 497768460 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 192585120 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 31420705950 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 32350562865 # Total energy per rank (pJ) +system.physmem_0.averagePower 244.026270 # Core power per rank (mW) +system.physmem_0.totalIdleTime 132428576750 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 10716000 # Time in different power states +system.physmem_0.memoryStateTime::REF 66782000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 130836450000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 501553500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 62926000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1091573000 # Time in different power states +system.physmem_1.actEnergy 3698520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1946835 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 12794880 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 142596480.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 50045430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 5323200 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 514216380 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 148467840 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 31429438665 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 32308536150 # Total energy per rank (pJ) -system.physmem_1.averagePower 243.767063 # Core power per rank (mW) -system.physmem_1.totalIdleTime 132414854750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 7934000 # Time in different power states -system.physmem_1.memoryStateTime::REF 60464000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 130900584250 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 386668500 # Time in different power states -system.physmem_1.memoryStateTime::ACT 55249000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1127662750 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 49693791 # Number of BP lookups -system.cpu.branchPred.condPredicted 39499604 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5516746 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24160971 # Number of BTB lookups -system.cpu.branchPred.BTBHits 22899506 # Number of BTB hits +system.physmem_1.refreshEnergy 143211120.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 50027190 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 5428800 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 512852940 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 149734560 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 31437405705 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 32317131480 # Total energy per rank (pJ) +system.physmem_1.averagePower 243.774090 # Core power per rank (mW) +system.physmem_1.totalIdleTime 132446049750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 8198000 # Time in different power states +system.physmem_1.memoryStateTime::REF 60730000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 130931475750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 389968500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 54962000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1124666250 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 49693872 # Number of BP lookups +system.cpu.branchPred.condPredicted 39498414 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5520434 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24194736 # Number of BTB lookups +system.cpu.branchPred.BTBHits 22923274 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.778914 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1894448 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 94.744882 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1894785 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 142 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 213843 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 208090 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 5753 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40382 # Number of mispredicted indirect branches. +system.cpu.branchPred.indirectLookups 213909 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 208025 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 5884 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40447 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -306,7 +306,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -336,7 +336,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -366,7 +366,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -397,16 +397,16 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 265077125 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 265140001 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317810 # Number of instructions committed system.cpu.committedOps 181650743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11524051 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11517797 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.538304 # CPI: cycles per instruction -system.cpu.ipc 0.650067 # IPC: instructions per cycle +system.cpu.cpi 1.538669 # CPI: cycles per instruction +system.cpu.ipc 0.649913 # IPC: instructions per cycle system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.op_class_0::IntAlu 138988213 76.51% 76.51% # Class of committed instruction system.cpu.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction @@ -446,18 +446,18 @@ system.cpu.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Cl system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.op_class_0::total 181650743 # Class of committed instruction -system.cpu.tickCycles 256741537 # Number of cycles that the object actually ticked -system.cpu.idleCycles 8335588 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.tickCycles 256807085 # Number of cycles that the object actually ticked +system.cpu.idleCycles 8332916 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1378.587934 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40755397 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1378.592517 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40754461 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1811 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22504.360574 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22503.843733 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1378.587934 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336569 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336569 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1378.592517 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336570 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336570 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1769 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id @@ -465,73 +465,73 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 85 system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1359 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431885 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81517417 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81517417 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28347488 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28347488 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362633 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362633 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 81515543 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81515543 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28346550 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28346550 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362634 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362634 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 463 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 463 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40710121 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40710121 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40710583 # number of overall hits -system.cpu.dcache.overall_hits::total 40710583 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 40709184 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40709184 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40709647 # number of overall hits +system.cpu.dcache.overall_hits::total 40709647 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 751 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 751 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1654 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1653 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1653 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2405 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2405 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2406 # number of overall misses -system.cpu.dcache.overall_misses::total 2406 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64864500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64864500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 147460000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 147460000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 212324500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 212324500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 212324500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 212324500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28348239 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28348239 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 2404 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2404 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2405 # number of overall misses +system.cpu.dcache.overall_misses::total 2405 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 64086500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 64086500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 146233500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 146233500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 210320000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 210320000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 210320000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 210320000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28347301 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28347301 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 464 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 464 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40712526 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40712526 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40712989 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40712989 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40711588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40711588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40712052 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40712052 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000134 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.000134 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002155 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.002155 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000059 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000059 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000059 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000059 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86370.838881 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 86370.838881 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89153.567110 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 89153.567110 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 88284.615385 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 88284.615385 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 88247.921862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 88247.921862 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 85334.886818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 85334.886818 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 88465.517241 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 88465.517241 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 87487.520799 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 87487.520799 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 87451.143451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 87451.143451 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -542,12 +542,12 @@ system.cpu.dcache.writebacks::writebacks 16 # nu system.cpu.dcache.writebacks::total 16 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 555 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 555 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 595 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 595 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 595 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 595 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 554 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 554 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 594 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 594 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 594 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1099 # number of WriteReq MSHR misses @@ -558,162 +558,162 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1811 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1811 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 61185500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 61185500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 100181500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 100181500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 60392000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 60392000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 99618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 99618500 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 77000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 77000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161367000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161444000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161444000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 160010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 160010500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 160087500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 160087500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002155 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002155 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86055.555556 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86055.555556 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91156.960874 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91156.960874 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84939.521800 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84939.521800 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 90644.676979 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 90644.676979 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 77000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 77000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 89153.038674 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 89153.038674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 89146.327996 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 89146.327996 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 2864 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.889067 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 70941363 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4663 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15213.674244 # Average number of references to valid blocks. +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88403.591160 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 88403.591160 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88397.294313 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 88397.294313 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 2861 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.892665 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 70991309 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4660 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15234.186481 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.889067 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695747 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695747 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.892665 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695748 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695748 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1799 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 491 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 131 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1069 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.878418 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 141896717 # Number of tag accesses -system.cpu.icache.tags.data_accesses 141896717 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 70941363 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 70941363 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 70941363 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 70941363 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 70941363 # number of overall hits -system.cpu.icache.overall_hits::total 70941363 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4664 # 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average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50633.233212 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50633.233212 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50633.233212 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 2864 # number of writebacks -system.cpu.icache.writebacks::total 2864 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4664 # 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average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49719.018010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49719.018010 # average overall mshr miss latency -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49633.447758 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49633.447758 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49633.447758 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49633.447758 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2835.336724 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 5160 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2835.344855 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5154 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3868 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.334023 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.332472 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.638236 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.698487 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046009 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.641960 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1327.702895 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.040518 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.086528 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3868 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 367 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2841 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.118042 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 76228 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 76228 # Number of data accesses -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.tags.tag_accesses 76180 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 76180 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # 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miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463551 # miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463551 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.463849 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.463849 # miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.887640 # miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.887640 # miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463551 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.463849 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.951408 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.600000 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463551 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.600278 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.463849 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951408 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.600000 # miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90236.021998 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90236.021998 # average ReadExReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91692.645698 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91692.645698 # average ReadCleanReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93781.645570 # average ReadSharedReq miss latency -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93781.645570 # average ReadSharedReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 91623.423423 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91692.645698 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91536.564132 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 91623.423423 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.600278 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89719.981668 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89719.981668 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 91456.290472 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 91456.290472 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 92526.107595 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 92526.107595 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 91142.728443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 91456.290472 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90749.274521 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 91142.728443 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,79 +806,79 @@ system.cpu.l2cache.demand_mshr_misses::total 3869 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2161 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3869 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87537500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87537500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176566000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 51432500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 51432500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176566000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138970000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 315536000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176566000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138970000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 315536000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 86974500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 86974500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 176055000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 176055000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 50639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 50639500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 176055000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137614000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 313669000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 176055000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137614000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 313669000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992721 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992721 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463336 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.463634 # mshr miss rate for ReadCleanReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.866573 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.866573 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.597529 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463336 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.597806 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.463634 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943125 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.597529 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80236.021998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80236.021998 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81705.691809 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81705.691809 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83358.995138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 83358.995138 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81705.691809 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81364.168618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81554.923753 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 9381 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3042 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.597806 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79719.981668 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79719.981668 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 81469.227210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 81469.227210 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82073.743922 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 82073.743922 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 81469.227210 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80570.257611 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81072.370121 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 9375 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3038 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_requests 336 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 5375 # Transaction distribution +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 5372 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2864 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2861 # Transaction distribution system.cpu.toL2Bus.trans_dist::CleanEvict 26 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1099 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1099 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4664 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 4661 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadSharedReq 712 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12191 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12182 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3664 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 15855 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481728 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 15846 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481344 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 598656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 598272 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 6475 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.072896 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.259985 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6472 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.072775 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.259787 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 6003 92.71% 92.71% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 472 7.29% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 6001 92.72% 92.72% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 471 7.28% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6475 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7570500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 6472 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7564500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6994999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6990499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2723985 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) @@ -888,7 +888,7 @@ system.membus.snoop_filter.hit_multi_requests 0 system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 132538562500 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 132570000500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2777 # Transaction distribution system.membus.trans_dist::ReadExReq 1091 # Transaction distribution system.membus.trans_dist::ReadExResp 1091 # Transaction distribution @@ -909,9 +909,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3868 # Request fanout histogram -system.membus.reqLayer0.occupancy 4518000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 4525000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 20568250 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20564500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 5040af9e4..8786b6479 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,67 +1,67 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.086149 # Number of seconds simulated -sim_ticks 86149358000 # Number of ticks simulated -final_tick 86149358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085986 # Number of seconds simulated +sim_ticks 85986203000 # Number of ticks simulated +final_tick 85986203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 240669 # Simulator instruction rate (inst/s) -host_op_rate 253706 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120331720 # Simulator tick rate (ticks/s) -host_mem_usage 272336 # Number of bytes of host memory used -host_seconds 715.93 # Real time elapsed on the host +host_inst_rate 210936 # Simulator instruction rate (inst/s) +host_op_rate 222361 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 105265513 # Simulator tick rate (ticks/s) +host_mem_usage 272504 # Number of bytes of host memory used +host_seconds 816.85 # Real time elapsed on the host sim_insts 172303022 # Number of instructions simulated sim_ops 181635954 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 652096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 192896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71744 # Number of bytes read from this memory -system.physmem.bytes_read::total 916736 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 652096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 652096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 10189 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3014 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14324 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 7569366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2239088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 832786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 10641240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7569366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7569366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7569366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2239088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 832786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10641240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 14324 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 651776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 193408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71680 # Number of bytes read from this memory +system.physmem.bytes_read::total 916864 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 651776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 651776 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 10184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3022 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 7580007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2249291 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 833622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10662920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7580007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7580007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7580007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2249291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 833622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10662920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 14327 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 14324 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 14327 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 916736 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 916928 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 916736 # Total read bytes from the system interface side +system.physmem.bytesReadSys 916928 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1375 # Per bank write bursts -system.physmem.perBankRdBursts::1 498 # Per bank write bursts -system.physmem.perBankRdBursts::2 5101 # Per bank write bursts -system.physmem.perBankRdBursts::3 808 # Per bank write bursts -system.physmem.perBankRdBursts::4 2279 # Per bank write bursts -system.physmem.perBankRdBursts::5 424 # Per bank write bursts -system.physmem.perBankRdBursts::6 384 # Per bank write bursts -system.physmem.perBankRdBursts::7 628 # Per bank write bursts +system.physmem.perBankRdBursts::0 1379 # Per bank write bursts +system.physmem.perBankRdBursts::1 501 # Per bank write bursts +system.physmem.perBankRdBursts::2 5100 # Per bank write bursts +system.physmem.perBankRdBursts::3 815 # Per bank write bursts +system.physmem.perBankRdBursts::4 2265 # Per bank write bursts +system.physmem.perBankRdBursts::5 427 # Per bank write bursts +system.physmem.perBankRdBursts::6 394 # Per bank write bursts +system.physmem.perBankRdBursts::7 623 # Per bank write bursts system.physmem.perBankRdBursts::8 270 # Per bank write bursts -system.physmem.perBankRdBursts::9 231 # Per bank write bursts +system.physmem.perBankRdBursts::9 230 # Per bank write bursts system.physmem.perBankRdBursts::10 354 # Per bank write bursts -system.physmem.perBankRdBursts::11 348 # Per bank write bursts -system.physmem.perBankRdBursts::12 320 # Per bank write bursts -system.physmem.perBankRdBursts::13 267 # Per bank write bursts -system.physmem.perBankRdBursts::14 240 # Per bank write bursts -system.physmem.perBankRdBursts::15 797 # Per bank write bursts +system.physmem.perBankRdBursts::11 345 # Per bank write bursts +system.physmem.perBankRdBursts::12 321 # Per bank write bursts +system.physmem.perBankRdBursts::13 266 # Per bank write bursts +system.physmem.perBankRdBursts::14 239 # Per bank write bursts +system.physmem.perBankRdBursts::15 798 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -80,14 +80,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 86149299500 # Total gap between requests +system.physmem.totGap 85986194000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 14324 # Read request sizes (log2) +system.physmem.readPktSize::6 14327 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -95,15 +95,15 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 12783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 12781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1074 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see @@ -191,29 +191,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 8487 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.956168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 86.535791 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 122.736079 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 5894 69.45% 69.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 2098 24.72% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 256 3.02% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 0.74% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 36 0.42% 98.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 32 0.38% 98.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 19 0.22% 98.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 8483 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.969350 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 86.508882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 122.734500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 5897 69.52% 69.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 2092 24.66% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 251 2.96% 97.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 65 0.77% 97.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 0.45% 98.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 36 0.42% 98.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 15 0.18% 98.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 8487 # Bytes accessed per row activation -system.physmem.totQLat 1500750524 # Total ticks spent queuing -system.physmem.totMemAccLat 1769325524 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 71620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 104771.75 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::total 8483 # Bytes accessed per row activation +system.physmem.totQLat 1497477800 # Total ticks spent queuing +system.physmem.totMemAccLat 1766109050 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 71635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 104521.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 123521.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 10.64 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 123271.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 10.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 10.64 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 10.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.08 # Data bus utilization in percentage @@ -221,66 +221,66 @@ system.physmem.busUtilRead 0.08 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5833 # Number of row buffer hits during reads +system.physmem.readRowHits 5838 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.72 # Row buffer hit rate for reads +system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 6014332.55 # Average gap between requests -system.physmem.pageHitRate 40.72 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 51543660 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 27384720 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 82088580 # Energy for read commands per rank (pJ) +system.physmem.avgGap 6001688.70 # Average gap between requests +system.physmem.pageHitRate 40.75 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 82138560 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5186946960.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1121176890 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 276161760 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 12273342600 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8346662400 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 9294814230 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 36662152740 # Total energy per rank (pJ) -system.physmem_0.averagePower 425.565010 # Core power per rank (mW) -system.physmem_0.totalIdleTime 82965211526 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 532687000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2205840000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 34315599752 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 21736059604 # Time in different power states -system.physmem_0.memoryStateTime::ACT 443979474 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 26915192170 # Time in different power states -system.physmem_1.actEnergy 9082080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4823445 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20184780 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 5188176240.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1121049780 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 275286240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 12230933460 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8389841280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 9251896980 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 36621408690 # Total energy per rank (pJ) +system.physmem_0.averagePower 425.898657 # Core power per rank (mW) +system.physmem_0.totalIdleTime 82802255264 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 532741000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2206324000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 34133171250 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21848572364 # Time in different power states +system.physmem_0.memoryStateTime::ACT 443169236 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 26822225150 # Time in different power states +system.physmem_1.actEnergy 9046380 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4800675 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20149080 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 883852320.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 198703710 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 50905920 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 1989700140 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 1383894720 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 18830063895 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 23371485780 # Total energy per rank (pJ) -system.physmem_1.averagePower 271.290305 # Core power per rank (mW) -system.physmem_1.totalIdleTime 85580460271 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 101384000 # Time in different power states -system.physmem_1.memoryStateTime::REF 376118000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 77613150500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 3603890386 # Time in different power states -system.physmem_1.memoryStateTime::ACT 91368979 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 4363446135 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 85639426 # Number of BP lookups -system.cpu.branchPred.condPredicted 68185953 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5937258 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 39949340 # Number of BTB lookups -system.cpu.branchPred.BTBHits 38185565 # Number of BTB hits +system.physmem_1.refreshEnergy 880164480.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 198118890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 50592480 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 1982659500 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 1381296480 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 18795083175 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 23322152130 # Total energy per rank (pJ) +system.physmem_1.averagePower 271.231327 # Core power per rank (mW) +system.physmem_1.totalIdleTime 85419499755 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 100592000 # Time in different power states +system.physmem_1.memoryStateTime::REF 374546000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 77474388250 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 3597111150 # Time in different power states +system.physmem_1.memoryStateTime::ACT 91565245 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 4348000355 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 85644201 # Number of BP lookups +system.cpu.branchPred.condPredicted 68263451 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5948841 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 39900262 # Number of BTB lookups +system.cpu.branchPred.BTBHits 38156956 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.584971 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3683095 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81909 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 681696 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 653573 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 28123 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 40352 # Number of mispredicted indirect branches. +system.cpu.branchPred.BTBHitPct 95.630841 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3658994 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81907 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 654149 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 629298 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 24851 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 40566 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -310,7 +310,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -340,7 +340,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -370,7 +370,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -401,242 +401,242 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 172298717 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 171972407 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5689617 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 347266831 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85639426 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42522233 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158380748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 11888463 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4145 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5684699 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 346733793 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85644201 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42445248 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158074641 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 11911485 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 4331 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 4281 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78346664 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 18062 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 170023102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.137102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.057569 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 4750 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78152122 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17905 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169724243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.137034 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.057596 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18318468 10.77% 10.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30068726 17.69% 28.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31619725 18.60% 47.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90016183 52.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 18311667 10.79% 10.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29948653 17.65% 28.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31633861 18.64% 47.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 89830062 52.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 170023102 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.497040 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.015493 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17554244 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 18101467 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 121824905 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6773054 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5769432 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11065775 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 189948 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 305038109 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27237354 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5769432 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37539679 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8956907 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 601126 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108322423 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8833535 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 277447852 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13184486 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3097243 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842563 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2612762 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 40533 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 26849 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 481448776 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1187920227 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 296497585 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005089 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169724243 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.498011 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.016218 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17545924 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 18077628 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 121579812 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6764631 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5756248 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 32661376 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 214759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 304427843 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27289068 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5756248 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37507593 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8946109 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 602389 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108088153 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8823751 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 276998119 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13097154 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3089202 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 850461 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2596711 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 40764 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26854 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 480912034 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1185877305 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 296009785 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3004340 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 188471847 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23626 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23625 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13449474 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 33921609 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14424624 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2552614 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1816807 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 263824183 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45978 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214443460 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5190288 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82234207 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 216932052 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 170023102 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.261261 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.018489 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 187935105 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23572 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23567 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13428642 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 33801265 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14384966 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2539582 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1819756 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 263460878 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45929 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214221426 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5142742 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 81870853 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 215931448 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 713 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169724243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.262173 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.018049 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 53215331 31.30% 31.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36043504 21.20% 52.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65536118 38.55% 91.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13631246 8.02% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1550810 0.91% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 45816 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 277 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 53012533 31.23% 31.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36041444 21.24% 52.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65469642 38.57% 91.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13608265 8.02% 99.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1546158 0.91% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 45935 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 266 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 170023102 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169724243 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35671391 66.13% 66.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 153271 0.28% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35712 0.07% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 556 0.00% 66.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 40135 0.07% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 13909773 25.79% 92.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3850022 7.14% 99.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 142020 0.26% 99.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 136319 0.25% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35637562 66.14% 66.14% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 153239 0.28% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35742 0.07% 66.49% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 559 0.00% 66.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 40182 0.07% 66.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 13886588 25.77% 92.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3846845 7.14% 99.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 141772 0.26% 99.75% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 136229 0.25% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167011334 77.88% 77.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 919426 0.43% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33015 0.02% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165180 0.08% 78.40% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245708 0.11% 78.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.55% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460349 0.21% 78.77% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206623 0.10% 78.86% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.90% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 31296412 14.59% 93.49% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13233182 6.17% 99.66% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 576648 0.27% 99.93% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 147624 0.07% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 166877725 77.90% 77.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 919560 0.43% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.33% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.34% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165187 0.08% 78.42% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245719 0.11% 78.54% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460300 0.21% 78.79% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206641 0.10% 78.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 31220842 14.57% 93.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13220710 6.17% 99.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 576371 0.27% 99.93% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 147395 0.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214443460 # Type of FU issued -system.cpu.iq.rate 1.244603 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53940732 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.251538 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654047721 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 344100630 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204290427 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3993321 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2010682 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806323 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266209914 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2174278 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1590245 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214221426 # Type of FU issued +system.cpu.iq.rate 1.245673 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53880251 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.251517 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 653198075 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 343375917 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204156399 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3992013 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2008700 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806249 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 265928183 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2173494 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1586831 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6025465 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7430 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7094 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1779990 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5905121 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7000 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1740332 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25605 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 790 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25012 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 810 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5769432 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5627104 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 174387 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 263890272 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5756248 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5611049 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 173372 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 263527171 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 33921609 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14424624 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23570 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3854 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 167353 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7094 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3148097 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247402 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6395499 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207161825 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30639651 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7281635 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 33801265 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14384966 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23521 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3789 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 166382 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7000 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3130012 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3255540 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6385552 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 206995589 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30591856 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7225837 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 20111 # number of nop insts executed -system.cpu.iew.exec_refs 43786600 # number of memory reference insts executed -system.cpu.iew.exec_branches 44861358 # Number of branches executed -system.cpu.iew.exec_stores 13146949 # Number of stores executed -system.cpu.iew.exec_rate 1.202341 # Inst execution rate -system.cpu.iew.wb_sent 206406222 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206096750 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129381204 # num instructions producing a value -system.cpu.iew.wb_consumers 221650091 # num instructions consuming a value -system.cpu.iew.wb_rate 1.196160 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.583718 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 68697467 # The number of squashed insts skipped by commit +system.cpu.iew.exec_nop 20364 # number of nop insts executed +system.cpu.iew.exec_refs 43730352 # number of memory reference insts executed +system.cpu.iew.exec_branches 44853428 # Number of branches executed +system.cpu.iew.exec_stores 13138496 # Number of stores executed +system.cpu.iew.exec_rate 1.203656 # Inst execution rate +system.cpu.iew.wb_sent 206269583 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 205962648 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129302452 # num instructions producing a value +system.cpu.iew.wb_consumers 221536410 # num instructions consuming a value +system.cpu.iew.wb_rate 1.197649 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.583662 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 68402964 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5762459 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158721175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.144462 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.650716 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5749347 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158452610 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146402 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.651768 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 74120611 46.70% 46.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41150811 25.93% 72.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22560961 14.21% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9504738 5.99% 92.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3552513 2.24% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2129219 1.34% 96.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1299436 0.82% 97.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1012456 0.64% 97.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3390430 2.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73893836 46.63% 46.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41104048 25.94% 72.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22555911 14.24% 86.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9496527 5.99% 92.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3557786 2.25% 95.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2129951 1.34% 96.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1320929 0.83% 97.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1010558 0.64% 97.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3383064 2.14% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158721175 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158452610 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317410 # Number of instructions committed system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -686,383 +686,389 @@ system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction -system.cpu.commit.bw_lim_events 3390430 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 405673353 # The number of ROB reads -system.cpu.rob.rob_writes 512011515 # The number of ROB writes -system.cpu.timesIdled 9971 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2275615 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 3383064 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 405117651 # The number of ROB reads +system.cpu.rob.rob_writes 511394543 # The number of ROB writes +system.cpu.timesIdled 9924 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2248164 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303022 # Number of Instructions Simulated system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.999975 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.999975 # CPI: Total CPI of All Threads -system.cpu.ipc 1.000025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.000025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218762027 # number of integer regfile reads -system.cpu.int_regfile_writes 114194444 # number of integer regfile writes -system.cpu.fp_regfile_reads 2903946 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441681 # number of floating regfile writes -system.cpu.cc_regfile_reads 708323214 # number of cc regfile reads -system.cpu.cc_regfile_writes 229513810 # number of cc regfile writes -system.cpu.misc_regfile_reads 57456345 # number of misc regfile reads +system.cpu.cpi 0.998081 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.998081 # CPI: Total CPI of All Threads +system.cpu.ipc 1.001922 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.001922 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218599432 # number of integer regfile reads +system.cpu.int_regfile_writes 114087616 # number of integer regfile writes +system.cpu.fp_regfile_reads 2903991 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441715 # number of floating regfile writes +system.cpu.cc_regfile_reads 707769294 # number of cc regfile reads +system.cpu.cc_regfile_writes 229397390 # number of cc regfile writes +system.cpu.misc_regfile_reads 57427586 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 72586 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.401008 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41045518 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73098 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 561.513557 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 555248500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.401008 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998830 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998830 # Average percentage of cache occupancy +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 72391 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.400200 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40997604 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 72903 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 562.358257 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 554902500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.400200 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998829 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998829 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82389396 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82389396 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 28659277 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28659277 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341322 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341322 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 365 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 365 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 82292817 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82292817 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 28611296 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28611296 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341384 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341384 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 362 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 362 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22154 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22154 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41000599 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41000599 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41000964 # number of overall hits -system.cpu.dcache.overall_hits::total 41000964 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89290 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89290 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22965 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22965 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 112255 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 112255 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 112371 # number of overall misses -system.cpu.dcache.overall_misses::total 112371 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1989594500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1989594500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 244666499 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 244666499 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2316500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 2234260999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 2234260999 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 2234260999 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 2234260999 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28748567 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28748567 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 40952680 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40952680 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40953042 # number of overall hits +system.cpu.dcache.overall_hits::total 40953042 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89081 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89081 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22903 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22903 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 111984 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 111984 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112101 # number of overall misses +system.cpu.dcache.overall_misses::total 112101 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1981259500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1981259500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 246570499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 246570499 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2257000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2257000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 2227829999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 2227829999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 2227829999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 2227829999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28700377 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28700377 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 481 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 481 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41112854 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41112854 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41113335 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41113335 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003106 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001857 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001857 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.241164 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.241164 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002730 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002730 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002733 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002733 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22282.388845 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22282.388845 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10653.886305 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10653.886305 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8909.615385 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19903.443045 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19903.443045 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19882.896824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19882.896824 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 41064664 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41064664 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41065143 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41065143 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001852 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001852 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244259 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.244259 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011291 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011291 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002727 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002727 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002730 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002730 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22241.100796 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22241.100796 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10765.860324 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10765.860324 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8920.948617 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8920.948617 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19894.181303 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19894.181303 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19873.417713 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19873.417713 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 11152 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 11209 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 864 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 12.907407 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 72586 # number of writebacks -system.cpu.dcache.writebacks::total 72586 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24872 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24872 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14398 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 14398 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 39270 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 39270 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 39270 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 39270 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64418 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64418 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8567 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8567 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 72985 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 72985 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73098 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73098 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1060539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1060539500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 87795999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 87795999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 969000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1148335499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 1148335499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1149304499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 1149304499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002241 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002241 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.234927 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.234927 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001775 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001778 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16463.403086 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16463.403086 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10248.161433 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10248.161433 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8575.221239 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15733.856258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 15733.856258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15722.789940 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 15722.789940 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 53582 # number of replacements -system.cpu.icache.tags.tagsinuse 510.578561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78288973 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54094 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1447.276463 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 85378568500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.578561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997224 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997224 # Average percentage of cache occupancy +system.cpu.dcache.avg_blocked_cycles::no_targets 12.958382 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 72391 # number of writebacks +system.cpu.dcache.writebacks::total 72391 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24849 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24849 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14345 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14345 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 253 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 253 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 39194 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 39194 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 39194 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 39194 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64232 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64232 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8558 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8558 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 114 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 72790 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 72790 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 72904 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 72904 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1056234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1056234000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88380499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 88380499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 977000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 977000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1144614499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 1144614499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1145591499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 1145591499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.237996 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.237996 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001773 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001773 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001775 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16444.046581 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16444.046581 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10327.237556 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10327.237556 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8570.175439 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8570.175439 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15724.886647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 15724.886647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15713.698823 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15713.698823 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 53106 # number of replacements +system.cpu.icache.tags.tagsinuse 510.578015 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78094905 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 53618 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1456.505371 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 85215430500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.578015 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997223 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156747350 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156747350 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 78288973 # 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number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2247853926 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2247853926 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2247853926 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2247853926 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78346628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78346628 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78346628 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78346628 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78346628 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78346628 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000736 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000736 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000736 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000736 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000736 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38988.013633 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38988.013633 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38988.013633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38988.013633 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38988.013633 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 94468 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 55 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 3203 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 29.493600 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 27.500000 # average number of cycles each access was blocked -system.cpu.icache.writebacks::writebacks 53582 # number of writebacks -system.cpu.icache.writebacks::total 53582 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3560 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3560 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3560 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3560 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3560 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3560 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54095 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54095 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54095 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54095 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54095 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54095 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2052751452 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2052751452 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2052751452 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2052751452 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2052751452 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2052751452 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000690 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000690 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000690 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000690 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37947.156891 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37947.156891 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37947.156891 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37947.156891 # average overall mshr miss latency -system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.l2cache.prefetcher.num_hwpf_issued 9257 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9257 # number of prefetch candidates identified +system.cpu.icache.tags.tag_accesses 156357779 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156357779 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.icache.ReadReq_hits::cpu.inst 78094905 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78094905 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78094905 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78094905 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78094905 # number of overall hits +system.cpu.icache.overall_hits::total 78094905 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57175 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57175 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57175 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57175 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57175 # number of overall misses +system.cpu.icache.overall_misses::total 57175 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2239186435 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2239186435 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2239186435 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2239186435 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2239186435 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2239186435 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78152080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78152080 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78152080 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78152080 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78152080 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78152080 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000732 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000732 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000732 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000732 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000732 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000732 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39163.733013 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 39163.733013 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 39163.733013 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 39163.733013 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 91615 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 88 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.176752 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked +system.cpu.icache.writebacks::writebacks 53106 # number of writebacks +system.cpu.icache.writebacks::total 53106 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3554 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3554 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3554 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3554 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3554 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3554 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 53621 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 53621 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 53621 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 53621 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 53621 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 53621 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2047106952 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2047106952 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2047106952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2047106952 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2047106952 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2047106952 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38177.336342 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38177.336342 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency +system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.num_hwpf_issued 9132 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9132 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1327 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.prefetcher.pfSpanPage 1308 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1809.107747 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 98955 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2836 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 34.892454 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 1811.625085 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 98153 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2844 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 34.512307 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1727.095683 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 82.012064 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.105414 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005006 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.110419 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 131 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2705 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 1727.578627 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 84.046457 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.105443 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.005130 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.110573 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 138 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 15 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 66 # 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number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1646592500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1646592500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 536158000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 536158000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1646592500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 555557000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 2202149500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1646592500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 555557000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 99174661 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 2301324161 # number of overall MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.188354 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043202 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043202 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.103803 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188354 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041232 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027243 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.189948 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043359 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.104384 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.189948 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041452 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.119904 # mshr miss rate for overall accesses -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 47911.933105 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81969.432314 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81969.432314 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161810.236530 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161810.236530 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 193500.179533 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 193500.179533 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167110.012876 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161810.236530 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185026.211015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 47911.933105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151103.346600 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 253361 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 126188 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10476 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 927 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 926 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.l2cache.overall_mshr_miss_rate::total 0.120081 # mshr miss rate for overall accesses +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 49936.888721 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82548.936170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82548.936170 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161668.384880 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161668.384880 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192378.184428 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192378.184428 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166741.084273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161668.384880 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 183837.524818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151472.662476 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 252022 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 125518 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 866 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 865 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 118558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 64701 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 61467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8634 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 54095 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 64464 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 161771 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218782 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 380553 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6891264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9323776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 16215040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2398 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 129591 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.088154 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.283547 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 117896 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 64558 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 60939 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2337 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8626 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 53621 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 64277 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160345 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218199 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 378544 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6830336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9298816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 16129152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2338 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 128862 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.088172 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.283573 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 118168 91.19% 91.19% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 11422 8.81% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 117501 91.18% 91.18% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 11360 8.82% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 129591 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 252848500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 128862 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 251508000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 81149483 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 80437981 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 109651491 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 109359491 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 14324 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 10483 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 14328 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 10478 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 86149358000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 14094 # Transaction distribution -system.membus.trans_dist::ReadExReq 229 # Transaction distribution -system.membus.trans_dist::ReadExResp 229 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 14095 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28647 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28647 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 916672 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 14090 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 235 # Transaction distribution +system.membus.trans_dist::ReadExResp 235 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 14092 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28653 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28653 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 14324 # Request fanout histogram +system.membus.snoop_fanout::samples 14328 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 14324 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 14328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 14324 # Request fanout histogram -system.membus.reqLayer0.occupancy 18004660 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 14328 # Request fanout histogram +system.membus.reqLayer0.occupancy 18011178 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 77243027 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 77254535 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 4554501a1..059c65964 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,63 +1,63 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.103324 # Number of seconds simulated -sim_ticks 103323995500 # Number of ticks simulated -final_tick 103323995500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.102721 # Number of seconds simulated +sim_ticks 102721386000 # Number of ticks simulated +final_tick 102721386000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113414 # Simulator instruction rate (inst/s) -host_op_rate 190092 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 88727502 # Simulator tick rate (ticks/s) -host_mem_usage 308112 # Number of bytes of host memory used -host_seconds 1164.51 # Real time elapsed on the host +host_inst_rate 115023 # Simulator instruction rate (inst/s) +host_op_rate 192789 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89461870 # Simulator tick rate (ticks/s) +host_mem_usage 308536 # Number of bytes of host memory used +host_seconds 1148.21 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu.inst 232832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 130880 # Number of bytes read from this memory -system.physmem.bytes_read::total 363712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 232832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 232832 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3638 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2045 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5683 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2253417 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1266695 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3520112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2253417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2253417 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2253417 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1266695 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3520112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5683 # Number of read requests accepted +system.physmem.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu.inst 235072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 130944 # Number of bytes read from this memory +system.physmem.bytes_read::total 366016 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 235072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 235072 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2046 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5719 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2288443 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1274749 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3563192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2288443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2288443 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2288443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1274749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3563192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5719 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5683 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5719 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 363712 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 366016 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 363712 # Total read bytes from the system interface side +system.physmem.bytesReadSys 366016 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 307 # Per bank write bursts -system.physmem.perBankRdBursts::1 383 # Per bank write bursts -system.physmem.perBankRdBursts::2 475 # Per bank write bursts -system.physmem.perBankRdBursts::3 366 # Per bank write bursts -system.physmem.perBankRdBursts::4 364 # Per bank write bursts -system.physmem.perBankRdBursts::5 336 # Per bank write bursts -system.physmem.perBankRdBursts::6 422 # Per bank write bursts -system.physmem.perBankRdBursts::7 392 # Per bank write bursts -system.physmem.perBankRdBursts::8 390 # Per bank write bursts -system.physmem.perBankRdBursts::9 296 # Per bank write bursts -system.physmem.perBankRdBursts::10 255 # Per bank write bursts -system.physmem.perBankRdBursts::11 273 # Per bank write bursts -system.physmem.perBankRdBursts::12 229 # Per bank write bursts -system.physmem.perBankRdBursts::13 485 # Per bank write bursts -system.physmem.perBankRdBursts::14 425 # Per bank write bursts -system.physmem.perBankRdBursts::15 285 # Per bank write bursts +system.physmem.perBankRdBursts::0 315 # Per bank write bursts +system.physmem.perBankRdBursts::1 393 # Per bank write bursts +system.physmem.perBankRdBursts::2 481 # Per bank write bursts +system.physmem.perBankRdBursts::3 362 # Per bank write bursts +system.physmem.perBankRdBursts::4 367 # Per bank write bursts +system.physmem.perBankRdBursts::5 335 # Per bank write bursts +system.physmem.perBankRdBursts::6 442 # Per bank write bursts +system.physmem.perBankRdBursts::7 357 # Per bank write bursts +system.physmem.perBankRdBursts::8 405 # Per bank write bursts +system.physmem.perBankRdBursts::9 298 # Per bank write bursts +system.physmem.perBankRdBursts::10 258 # Per bank write bursts +system.physmem.perBankRdBursts::11 270 # Per bank write bursts +system.physmem.perBankRdBursts::12 235 # Per bank write bursts +system.physmem.perBankRdBursts::13 489 # Per bank write bursts +system.physmem.perBankRdBursts::14 424 # Per bank write bursts +system.physmem.perBankRdBursts::15 288 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -76,14 +76,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 103323737000 # Total gap between requests +system.physmem.totGap 102721127000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5683 # Read request sizes (log2) +system.physmem.readPktSize::6 5719 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,12 +91,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 973 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 211 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4464 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 987 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -187,29 +187,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1258 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 287.745628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 162.611559 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.712964 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 571 45.39% 45.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 250 19.87% 65.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 94 7.47% 72.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 65 5.17% 77.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 43 3.42% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.53% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 29 2.31% 88.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 22 1.75% 89.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 127 10.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1258 # Bytes accessed per row activation -system.physmem.totQLat 187208250 # Total ticks spent queuing -system.physmem.totMemAccLat 293764500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 28415000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32941.80 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1259 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.245433 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 165.404896 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.969258 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 547 43.45% 43.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 270 21.45% 64.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 107 8.50% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 4.05% 77.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 47 3.73% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 64 5.08% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 24 1.91% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.99% 90.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 124 9.85% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1259 # Bytes accessed per row activation +system.physmem.totQLat 198070500 # Total ticks spent queuing +system.physmem.totMemAccLat 305301750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 28595000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34633.76 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51691.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 53383.76 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.56 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.56 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage @@ -217,309 +217,309 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4417 # Number of row buffer hits during reads +system.physmem.readRowHits 4452 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.72 # Row buffer hit rate for reads +system.physmem.readRowHitRate 77.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 18181196.02 # Average gap between requests -system.physmem.pageHitRate 77.72 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5404980 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2853840 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 21741300 # Energy for read commands per rank (pJ) +system.physmem.avgGap 17961379.09 # Average gap between requests +system.physmem.pageHitRate 77.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5319300 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2808300 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 21791280 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 298715040.000000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 95918460 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 16609440 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 744016440 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 410144160 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 24152474700 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 25747878360 # Total energy per rank (pJ) -system.physmem_0.averagePower 249.195533 # Core power per rank (mW) -system.physmem_0.totalIdleTime 103070096750 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 32003500 # Time in different power states -system.physmem_0.memoryStateTime::REF 127050000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 100370697500 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 1068078250 # Time in different power states -system.physmem_0.memoryStateTime::ACT 94522250 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 1631644000 # Time in different power states -system.physmem_1.actEnergy 3634260 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1920270 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18835320 # Energy for read commands per rank (pJ) +system.physmem_0.refreshEnergy 308549280.000000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94282560 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 17303520 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 739487790 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 445716000 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 23991769245 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 25627073595 # Total energy per rank (pJ) +system.physmem_0.averagePower 249.481384 # Core power per rank (mW) +system.physmem_0.totalIdleTime 102469123000 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 33581500 # Time in different power states +system.physmem_0.memoryStateTime::REF 131264000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 99687058000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 1160707250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 87094500 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 1621680750 # Time in different power states +system.physmem_1.actEnergy 3727080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1969605 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19042380 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 228031440.000000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73672500 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12688320 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 586536840 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 299079840 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 24303470280 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 25527869070 # Total energy per rank (pJ) -system.physmem_1.averagePower 247.066219 # Core power per rank (mW) -system.physmem_1.totalIdleTime 103129135750 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 24348000 # Time in different power states -system.physmem_1.memoryStateTime::REF 96994000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 101064274500 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 778849000 # Time in different power states -system.physmem_1.memoryStateTime::ACT 73295500 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 1286234500 # Time in different power states -system.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.branchPred.lookups 40855234 # Number of BP lookups -system.cpu.branchPred.condPredicted 40855234 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6727710 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 35293159 # Number of BTB lookups +system.physmem_1.refreshEnergy 233563200.000000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 75326640 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12588960 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 599034660 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 319716000 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 24137455500 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 25402424025 # Total energy per rank (pJ) +system.physmem_1.averagePower 247.294404 # Core power per rank (mW) +system.physmem_1.totalIdleTime 102523153750 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 23880000 # Time in different power states +system.physmem_1.memoryStateTime::REF 99310000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 100377149750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 832585250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74819500 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 1313641500 # Time in different power states +system.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.branchPred.lookups 40475108 # Number of BP lookups +system.cpu.branchPred.condPredicted 40475108 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6616133 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 34806541 # Number of BTB lookups system.cpu.branchPred.BTBHits 0 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3199678 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 605841 # Number of incorrect RAS predictions. -system.cpu.branchPred.indirectLookups 35293159 # Number of indirect predictor lookups. -system.cpu.branchPred.indirectHits 9878902 # Number of indirect target hits. -system.cpu.branchPred.indirectMisses 25414257 # Number of indirect misses. -system.cpu.branchPredindirectMispredicted 5019418 # Number of mispredicted indirect branches. +system.cpu.branchPred.usedRAS 3130768 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 590894 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 34806541 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 9997740 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 24808801 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 4890379 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.pwrStateResidencyTicks::ON 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.numCycles 206647992 # number of cpu cycles simulated +system.cpu.pwrStateResidencyTicks::ON 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.numCycles 205442773 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 46314104 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 419677545 # Number of instructions fetch has processed -system.cpu.fetch.Branches 40855234 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 13078580 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 152558577 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14911731 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 146 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 6162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 75545 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 535 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 173 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 41227932 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1521125 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 10 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 206411107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.413574 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.660203 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 45893468 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 415890095 # Number of instructions fetch has processed +system.cpu.fetch.Branches 40475108 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 13128508 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 151898710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14677491 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 200 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 64355 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 603 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 40893606 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1496111 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 12 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 205202132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.402306 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.658033 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 99253613 48.09% 48.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5140686 2.49% 50.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5371591 2.60% 53.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5329252 2.58% 55.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 6011005 2.91% 58.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5851603 2.83% 61.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5726027 2.77% 64.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4748810 2.30% 66.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 68978520 33.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98918732 48.21% 48.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5142243 2.51% 50.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5340112 2.60% 53.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5342271 2.60% 55.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 5947890 2.90% 58.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5817544 2.84% 61.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5684313 2.77% 64.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4746268 2.31% 66.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 68262759 33.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 206411107 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.197704 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.030881 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32267820 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 86650194 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 62332865 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17704363 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 7455865 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 590435256 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 7455865 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 42053837 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46607662 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 29929 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 68827187 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 41436627 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 551754102 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1587 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 36503796 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4817365 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 169314 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 629088770 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1485013522 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 974082903 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 15054868 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 205202132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.197014 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.024360 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31935878 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 86571693 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 61623233 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 17732583 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 7338745 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 585424017 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 7338745 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 41662208 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 46227710 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28975 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 68218759 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 41725735 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 547333455 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1808 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 36710047 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4936211 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 172798 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 624155686 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1473918398 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 966803184 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 14714209 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 369659320 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2323 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2340 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 89508181 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 128738720 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 45872059 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 77414851 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25246681 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 490126112 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 61893 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 338153574 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1099180 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 268824621 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 526308720 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 60648 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 206411107 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.638253 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.802953 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 364726236 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2257 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2274 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 89803577 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 127813025 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 45569326 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 76700063 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 25076085 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 486700618 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 63617 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 336591199 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1075816 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 265400851 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 520101355 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 62372 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 205202132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.640291 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.801229 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 73313522 35.52% 35.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 46679908 22.62% 58.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 32876430 15.93% 74.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20896006 10.12% 84.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 15048824 7.29% 91.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 8392050 4.07% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5201413 2.52% 98.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2354868 1.14% 99.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1648086 0.80% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 72558879 35.36% 35.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 46563371 22.69% 58.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32833591 16.00% 74.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20829399 10.15% 84.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 14957397 7.29% 91.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 8327086 4.06% 95.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5158088 2.51% 98.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2335665 1.14% 99.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1638656 0.80% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 206411107 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 205202132 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 756912 19.27% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMisc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.27% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2690839 68.51% 87.78% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 431049 10.97% 98.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemRead 45501 1.16% 99.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMemWrite 3340 0.09% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 746075 18.99% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMisc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2709270 68.98% 87.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 425878 10.84% 98.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemRead 43262 1.10% 99.91% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMemWrite 3383 0.09% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211791 0.36% 0.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 216412325 64.00% 64.36% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 800256 0.24% 64.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7047583 2.08% 66.68% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1802667 0.53% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 82552665 24.41% 91.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 26471074 7.83% 99.45% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemRead 1726255 0.51% 99.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMemWrite 128958 0.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1212158 0.36% 0.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 215249611 63.95% 64.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 800532 0.24% 64.55% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7048368 2.09% 66.64% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1789279 0.53% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.17% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 82235879 24.43% 91.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 26412297 7.85% 99.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemRead 1712250 0.51% 99.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMemWrite 130825 0.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 338153574 # Type of FU issued -system.cpu.iq.rate 1.636375 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3927641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011615 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 879585731 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 744431622 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 315835107 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 8159345 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 15410519 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3544176 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 336768258 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 4101166 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18155454 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 336591199 # Type of FU issued +system.cpu.iq.rate 1.638370 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3927868 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.011670 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 875283157 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 737961913 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 314539873 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 8105057 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 15024545 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3526208 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 335233754 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 4073155 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18221671 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 72089133 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 55091 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 866955 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 25356342 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 71163438 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 53029 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 858947 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 25053609 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50448 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 55 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 50433 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 53 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 7455865 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35715167 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 589866 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 490188005 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1248811 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 128738720 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 45872059 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 22561 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 546009 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 38338 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 866955 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1295323 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6857589 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8152912 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 326241588 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 80652390 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 11911986 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 7338745 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35257397 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 584477 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 486764235 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1231542 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 127813025 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 45569326 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23100 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 542722 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 38323 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 858947 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1297189 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 6715157 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8012346 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 324846022 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 80370790 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 11745177 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 106269865 # number of memory reference insts executed -system.cpu.iew.exec_branches 18918443 # Number of branches executed -system.cpu.iew.exec_stores 25617475 # Number of stores executed -system.cpu.iew.exec_rate 1.578731 # Inst execution rate -system.cpu.iew.wb_sent 322387752 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 319379283 # cumulative count of insts written-back -system.cpu.iew.wb_producers 256328359 # num instructions producing a value -system.cpu.iew.wb_consumers 435429845 # num instructions consuming a value -system.cpu.iew.wb_rate 1.545523 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.588679 # average fanout of values written-back -system.cpu.commit.commitSquashedInsts 268850223 # The number of squashed insts skipped by commit +system.cpu.iew.exec_refs 105939673 # number of memory reference insts executed +system.cpu.iew.exec_branches 18800592 # Number of branches executed +system.cpu.iew.exec_stores 25568883 # Number of stores executed +system.cpu.iew.exec_rate 1.581200 # Inst execution rate +system.cpu.iew.wb_sent 321037948 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 318066081 # cumulative count of insts written-back +system.cpu.iew.wb_producers 255309822 # num instructions producing a value +system.cpu.iew.wb_consumers 434053597 # num instructions consuming a value +system.cpu.iew.wb_rate 1.548198 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.588199 # average fanout of values written-back +system.cpu.commit.commitSquashedInsts 265431223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6732902 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 163914906 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.350477 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.932475 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6620631 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 163283495 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.355700 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.936592 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 67189595 40.99% 40.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 54970007 33.54% 74.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13274329 8.10% 82.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 10696589 6.53% 89.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 5450081 3.32% 92.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 3128441 1.91% 94.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1086544 0.66% 95.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1161401 0.71% 95.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6957919 4.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 66681947 40.84% 40.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 54877402 33.61% 74.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13218916 8.10% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 10716769 6.56% 89.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 5408933 3.31% 92.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 3143149 1.92% 94.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1097453 0.67% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1149760 0.70% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6989166 4.28% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 163914906 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 163283495 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,469 +569,469 @@ system.cpu.commit.op_class_0::FloatMemWrite 105487 0.05% 100.00% # system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6957919 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 647170594 # The number of ROB reads -system.cpu.rob.rob_writes 1023323556 # The number of ROB writes -system.cpu.timesIdled 2853 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 236885 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.commit.bw_lim_events 6989166 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 643088936 # The number of ROB reads +system.cpu.rob.rob_writes 1015902477 # The number of ROB writes +system.cpu.timesIdled 2803 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 240641 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.564671 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.564671 # CPI: Total CPI of All Threads -system.cpu.ipc 0.639112 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.639112 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 524350393 # number of integer regfile reads -system.cpu.int_regfile_writes 288862618 # number of integer regfile writes -system.cpu.fp_regfile_reads 4510095 # number of floating regfile reads -system.cpu.fp_regfile_writes 3309705 # number of floating regfile writes -system.cpu.cc_regfile_reads 106995415 # number of cc regfile reads -system.cpu.cc_regfile_writes 65768687 # number of cc regfile writes -system.cpu.misc_regfile_reads 176729824 # number of misc regfile reads +system.cpu.cpi 1.555546 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.555546 # CPI: Total CPI of All Threads +system.cpu.ipc 0.642861 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.642861 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 522853571 # number of integer regfile reads +system.cpu.int_regfile_writes 287693953 # number of integer regfile writes +system.cpu.fp_regfile_reads 4488277 # number of floating regfile reads +system.cpu.fp_regfile_writes 3288210 # number of floating regfile writes +system.cpu.cc_regfile_reads 106934935 # number of cc regfile reads +system.cpu.cc_regfile_writes 65654592 # number of cc regfile writes +system.cpu.misc_regfile_reads 175824659 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.tags.replacements 82 # number of replacements -system.cpu.dcache.tags.tagsinuse 1514.501359 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 82730891 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2127 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 38895.576399 # Average number of references to valid blocks. +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.tags.replacements 101 # number of replacements +system.cpu.dcache.tags.tagsinuse 1519.152295 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 82373071 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2121 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 38836.902876 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1514.501359 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.369751 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.369751 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 111 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1470 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.499268 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 165469279 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 165469279 # Number of data accesses -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.dcache.ReadReq_hits::cpu.data 62216578 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 62216578 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513684 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513684 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 82730262 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 82730262 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 82730262 # number of overall hits -system.cpu.dcache.overall_hits::total 82730262 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1267 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1267 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2047 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2047 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3314 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3314 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3314 # number of overall misses -system.cpu.dcache.overall_misses::total 3314 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 112642500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 112642500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 136500000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 136500000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 249142500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 249142500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 249142500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 249142500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 62217845 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 62217845 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 1519.152295 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.370887 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.370887 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2020 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 426 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1452 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.493164 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 164753603 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 164753603 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.dcache.ReadReq_hits::cpu.data 61858750 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 61858750 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513717 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513717 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 82372467 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 82372467 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 82372467 # number of overall hits +system.cpu.dcache.overall_hits::total 82372467 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1260 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1260 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3274 # 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number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 61860010 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 82733576 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 82733576 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 82733576 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 82733576 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 82375741 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 82375741 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 82375741 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 82375741 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000020 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000020 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000100 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000100 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000098 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000098 # miss rate for WriteReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.000040 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.000040 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000040 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000040 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88904.893449 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 88904.893449 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66682.950660 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66682.950660 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 75178.786964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 75178.786964 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 75178.786964 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 331 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 143 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 82.750000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 71.500000 # average number of cycles each access was blocked -system.cpu.dcache.writebacks::writebacks 17 # number of writebacks -system.cpu.dcache.writebacks::total 17 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 658 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 658 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 664 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 664 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 609 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2041 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2650 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2650 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2650 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2650 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70639000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70639000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 134072000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 134072000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 204711000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 204711000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 204711000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 204711000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 102222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68543.694141 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 68543.694141 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 81504.886988 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 81504.886988 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 81504.886988 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 635 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 58 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 127 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 58 # average number of cycles each access was blocked +system.cpu.dcache.writebacks::writebacks 22 # number of writebacks +system.cpu.dcache.writebacks::total 22 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 652 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 652 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 663 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 663 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 663 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 663 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 608 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2003 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2003 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2611 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2611 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2611 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2611 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 79597500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 79597500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 135457500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 135457500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215055000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 215055000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215055000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 215055000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000099 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000099 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000098 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000098 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000032 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 115991.789819 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 115991.789819 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65689.367957 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65689.367957 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77249.433962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77249.433962 # average overall mshr miss latency -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.icache.tags.replacements 6640 # number of replacements -system.cpu.icache.tags.tagsinuse 1671.571610 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 41214631 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 8628 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4776.846430 # Average number of references to valid blocks. +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 130916.940789 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 130916.940789 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67627.309036 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67627.309036 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82364.994255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82364.994255 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.icache.tags.replacements 6438 # number of replacements +system.cpu.icache.tags.tagsinuse 1691.823634 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 40880551 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 8435 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 4846.538352 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1671.571610 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.816197 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.816197 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1988 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 860 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 713 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.970703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 82465000 # Number of tag accesses -system.cpu.icache.tags.data_accesses 82465000 # Number of data accesses -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.icache.ReadReq_hits::cpu.inst 41214631 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 41214631 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 41214631 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 41214631 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 41214631 # number of overall hits -system.cpu.icache.overall_hits::total 41214631 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13297 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13297 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13297 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13297 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13297 # number of overall misses -system.cpu.icache.overall_misses::total 13297 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 657223000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 657223000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 657223000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 657223000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 657223000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 657223000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 41227928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 41227928 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 41227928 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 41227928 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 41227928 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 41227928 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000323 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000323 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000323 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000323 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000323 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000323 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49426.411973 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49426.411973 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49426.411973 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49426.411973 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49426.411973 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49426.411973 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2020 # 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Number of tag accesses +system.cpu.l2cache.tags.data_accesses 146063 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.l2cache.WritebackDirty_hits::writebacks 22 # number of WritebackDirty hits +system.cpu.l2cache.WritebackDirty_hits::total 22 # number of WritebackDirty hits +system.cpu.l2cache.WritebackClean_hits::writebacks 6400 # number of WritebackClean hits +system.cpu.l2cache.WritebackClean_hits::total 6400 # number of WritebackClean hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 490 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 490 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 4761 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 4761 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 67 # 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number of ReadSharedReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2046 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5719 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3673 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2046 # number of overall misses +system.cpu.l2cache.overall_misses::total 5719 # number of overall misses +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 126886000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 126886000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 392741000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 392741000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 77762500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 77762500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 392741000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 204648500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 597389500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 392741000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 204648500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 597389500 # number of overall miss cycles +system.cpu.l2cache.WritebackDirty_accesses::writebacks 22 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackDirty_accesses::total 22 # number of WritebackDirty accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::writebacks 6400 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.WritebackClean_accesses::total 6400 # number of WritebackClean accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 490 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 490 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1515 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1515 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 8434 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 8434 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 606 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8434 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2121 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 10555 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8434 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2121 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 10555 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994719 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.994719 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.435499 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.435499 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.889439 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.889439 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.435499 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.964639 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.541829 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.435499 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.964639 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.541829 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84197.743862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84197.743862 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 106926.490607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 106926.490607 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 144271.799629 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 144271.799629 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104456.985487 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 106926.490607 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 100023.704790 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104456.985487 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1513 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1513 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3638 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3638 # number of ReadCleanReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 532 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 532 # number of ReadSharedReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3638 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2045 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5683 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3638 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2045 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5683 # number of overall MSHR misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 109950500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 109950500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 353832000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 353832000 # number of ReadCleanReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 63372500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 63372500 # number of ReadSharedReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 353832000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173323000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 527155000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 353832000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173323000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 527155000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.995395 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.995395 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.422042 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.876442 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.876442 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.528799 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.422042 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.961448 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.528799 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 72670.522141 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 72670.522141 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 97260.032985 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 97260.032985 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 119121.240602 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 119121.240602 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 97260.032985 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84754.523227 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 92759.985923 # average overall mshr miss latency -system.cpu.toL2Bus.snoop_filter.tot_requests 18517 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 6823 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1046 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1507 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3673 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3673 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 539 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 539 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3673 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2046 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5719 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2046 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5719 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 111816000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 111816000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 356011000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 356011000 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 72372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 72372500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 356011000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 184188500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 540199500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 356011000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 184188500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 540199500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994719 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994719 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.435499 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.889439 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.889439 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.541829 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.435499 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964639 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.541829 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74197.743862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74197.743862 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 96926.490607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 96926.490607 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 134271.799629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 134271.799629 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 96926.490607 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90023.704790 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 94456.985487 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 18075 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 6619 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 979 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.cpu.toL2Bus.trans_dist::ReadResp 9751 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 6640 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 65 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1520 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 9145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 607 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24404 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5382 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 29786 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1113792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 525 # Total snoops (count) -system.cpu.toL2Bus.snoopTraffic 33600 # Total snoop traffic (bytes) -system.cpu.toL2Bus.snoop_fanout::samples 11795 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.096651 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.295495 # Request fanout histogram +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.cpu.toL2Bus.trans_dist::ReadResp 9530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 22 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 6438 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 490 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1515 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 8925 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 606 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23796 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5323 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 29119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 951744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 137152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1088896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 491 # Total snoops (count) +system.cpu.toL2Bus.snoopTraffic 31424 # Total snoop traffic (bytes) +system.cpu.toL2Bus.snoop_fanout::samples 11536 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.091713 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.288633 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 10655 90.33% 90.33% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 1140 9.67% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 10478 90.83% 90.83% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1058 9.17% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 11795 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15915500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 11536 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15497500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 13716000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 13386000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3452000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3426999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.snoop_filter.tot_requests 5683 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.tot_requests 5719 # Total number of requests made to the snoop filter. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 103323995500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadResp 4170 # Transaction distribution -system.membus.trans_dist::ReadExReq 1513 # Transaction distribution -system.membus.trans_dist::ReadExResp 1513 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 4170 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11366 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11366 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11366 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 363712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 363712 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 363712 # Cumulative packet size per connected master and slave (bytes) +system.membus.pwrStateResidencyTicks::UNDEFINED 102721386000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadResp 4212 # Transaction distribution +system.membus.trans_dist::ReadExReq 1507 # Transaction distribution +system.membus.trans_dist::ReadExResp 1507 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4212 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11438 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11438 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 366016 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 366016 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 5683 # Request fanout histogram +system.membus.snoop_fanout::samples 5719 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5683 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5719 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5683 # Request fanout histogram -system.membus.reqLayer0.occupancy 6909500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5719 # Request fanout histogram +system.membus.reqLayer0.occupancy 6957500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 30126750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 30309750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |