diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-07-22 20:31:24 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-07-22 20:31:24 -0500 |
| commit | 2590a7dd0a563d8548ba13a62c9ea8b82fa464ad (patch) | |
| tree | 87c6d67b85cbe7e328576b263a4a992117ef9709 /tests/long | |
| parent | 11a551ae3ac179c6ce0e72dccfd4476fdf640798 (diff) | |
| download | gem5-2590a7dd0a563d8548ba13a62c9ea8b82fa464ad.tar.xz | |
Regression: Update stats due to changes to x86 cpuid instruction
Diffstat (limited to 'tests/long')
11 files changed, 1325 insertions, 1245 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 43a81f743..1fa068d9c 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -999,7 +999,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.physmem.port[0] system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave +master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave slave=system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.int_master [system.membus.badaddr_responder] @@ -1261,7 +1261,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1281,7 +1281,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index fd09f1faf..98becac20 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -2,7 +2,18 @@ warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. +warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc +warn: x86 cpuid: unknown family 0xbacc warn: instruction 'fxsave' unimplemented +warn: x86 cpuid: unknown family 0x8086 +warn: x86 cpuid: unknown family 0x8086 +warn: x86 cpuid: unimplemented function 8 +warn: x86 cpuid: unimplemented function 8 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index c8a74a70a..e7dca044c 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,15 @@ +Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout +Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:58:39 -gem5 started Jul 2 2012 14:54:43 -gem5 executing on zizzer -command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing +gem5 compiled Jul 22 2012 08:05:39 +gem5 started Jul 22 2012 08:05:57 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 + 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5173840734500 because m5_exit instruction encountered +Exiting @ tick 5172902281500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 4862f54d8..4fa4cc520 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,186 +1,186 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.173841 # Number of seconds simulated -sim_ticks 5173840734500 # Number of ticks simulated -final_tick 5173840734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.172902 # Number of seconds simulated +sim_ticks 5172902281500 # Number of ticks simulated +final_tick 5172902281500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158571 # Simulator instruction rate (inst/s) -host_op_rate 312487 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1923470418 # Simulator tick rate (ticks/s) -host_mem_usage 368528 # Number of bytes of host memory used -host_seconds 2689.85 # Real time elapsed on the host -sim_insts 426531587 # Number of instructions simulated -sim_ops 840543055 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::pc.south_bridge.ide 2458496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1064640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10449152 # Number of bytes read from this memory -system.physmem.bytes_read::total 13975936 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1064640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1064640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9180480 # Number of bytes written to this memory -system.physmem.bytes_written::total 9180480 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 38414 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 50 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16635 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 163268 # Number of read requests responded to by this memory -system.physmem.num_reads::total 218374 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143445 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143445 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 475178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 618 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 205774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2019612 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2701269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 205774 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 205774 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1774403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1774403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1774403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 475178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 618 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 205774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2019612 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4475672 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 107079 # number of replacements -system.l2c.tagsinuse 64844.194000 # Cycle average of tags in use -system.l2c.total_refs 3995584 # Total number of references to valid blocks. -system.l2c.sampled_refs 171337 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.320030 # Average number of references to valid blocks. +host_inst_rate 117061 # Simulator instruction rate (inst/s) +host_op_rate 230687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1419746087 # Simulator tick rate (ticks/s) +host_mem_usage 420308 # Number of bytes of host memory used +host_seconds 3643.54 # Real time elapsed on the host +sim_insts 426515724 # Number of instructions simulated +sim_ops 840516219 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::pc.south_bridge.ide 2496512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 3520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1067840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10426304 # Number of bytes read from this memory +system.physmem.bytes_read::total 13994560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1067840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1067840 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9194240 # Number of bytes written to this memory +system.physmem.bytes_written::total 9194240 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 39008 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 55 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 162911 # Number of read requests responded to by this memory +system.physmem.num_reads::total 218665 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143660 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143660 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 482613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 206430 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2015562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2705359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 206430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 206430 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1777385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1777385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1777385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 482613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 206430 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2015562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4482745 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 107419 # number of replacements +system.l2c.tagsinuse 64844.084797 # Cycle average of tags in use +system.l2c.total_refs 3992672 # Total number of references to valid blocks. +system.l2c.sampled_refs 171622 # Sample count of references to valid blocks. +system.l2c.avg_refs 23.264337 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 50153.806815 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 12.883885 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.168545 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 3383.279361 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 11294.055394 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.765286 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 50135.967843 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 12.897301 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.156788 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 3372.666022 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 11322.396844 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.765014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000197 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.itb.walker 0.000003 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.051625 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.172334 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.989444 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 110015 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 8879 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 1055721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 1346083 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2520698 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1613450 # number of Writeback hits -system.l2c.Writeback_hits::total 1613450 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 329 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 329 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 163813 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 163813 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 110015 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 8879 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 1055721 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1509896 # number of demand (read+write) hits -system.l2c.demand_hits::total 2684511 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 110015 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 8879 # number of overall hits -system.l2c.overall_hits::cpu.inst 1055721 # number of overall hits -system.l2c.overall_hits::cpu.data 1509896 # number of overall hits -system.l2c.overall_hits::total 2684511 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 50 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 16637 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 34998 # number of ReadReq misses -system.l2c.ReadReq_misses::total 51692 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 1514 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1514 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 129215 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 129215 # number of ReadExReq misses -system.l2c.demand_misses::cpu.dtb.walker 50 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 16637 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 164213 # number of demand (read+write) misses -system.l2c.demand_misses::total 180907 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 50 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu.inst 16637 # number of overall misses -system.l2c.overall_misses::cpu.data 164213 # number of overall misses -system.l2c.overall_misses::total 180907 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 2626500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 364000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.inst 883116000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.data 1863608490 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2749714990 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu.data 39367500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 39367500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6737631498 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6737631498 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu.dtb.walker 2626500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.itb.walker 364000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.inst 883116000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 8601239988 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 9487346488 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu.dtb.walker 2626500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.itb.walker 364000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.inst 883116000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 8601239988 # number of overall miss cycles -system.l2c.overall_miss_latency::total 9487346488 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.dtb.walker 110065 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 8886 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 1072358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1381081 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2572390 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1613450 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1613450 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 1843 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1843 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 293028 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 293028 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 110065 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 8886 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 1072358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1674109 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2865418 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 110065 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 8886 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 1072358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1674109 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2865418 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000454 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000788 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.015514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.025341 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020095 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.821487 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.821487 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.440965 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.440965 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000454 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000788 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.015514 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.098090 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.063135 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000454 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000788 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.015514 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.098090 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.063135 # 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number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 2241000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.itb.walker 240000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.inst 682427500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 6600966001 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 7285874501 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 2241000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.itb.walker 240000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.inst 682427500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 6600966001 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 7285874501 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 59192209064 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 59192209064 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1211526000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1211526000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu.data 60403735064 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60403735064 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.020136 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.818133 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.818133 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.439970 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.439970 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.063075 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000497 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.015577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.097941 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.063075 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40891.313496 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41029.716804 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40984.435741 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40269.154557 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40269.154557 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40096.474875 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40096.474875 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40900.659275 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 41054.425752 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 41004.405201 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40282.321900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40282.321900 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40078.000458 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40078.000458 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40410 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40745.454545 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40891.313496 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40295.368183 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40350.188498 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40900.659275 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40286.640226 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40343.498754 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -289,39 +289,39 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 47568 # number of replacements -system.iocache.tagsinuse 0.202980 # Cycle average of tags in use +system.iocache.replacements 47565 # number of replacements +system.iocache.tagsinuse 0.200108 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 47584 # Sample count of references to valid blocks. +system.iocache.sampled_refs 47581 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 5000598826000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::pc.south_bridge.ide 0.202980 # Average occupied blocks per requestor -system.iocache.occ_percent::pc.south_bridge.ide 0.012686 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.012686 # Average percentage of cache occupancy -system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses -system.iocache.ReadReq_misses::total 903 # number of ReadReq misses +system.iocache.warmup_cycle 5000599162000 # Cycle when the warmup percentage was hit. +system.iocache.occ_blocks::pc.south_bridge.ide 0.200108 # Average occupied blocks per requestor +system.iocache.occ_percent::pc.south_bridge.ide 0.012507 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.012507 # Average percentage of cache occupancy +system.iocache.ReadReq_misses::pc.south_bridge.ide 900 # number of ReadReq misses +system.iocache.ReadReq_misses::total 900 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # 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number of overall miss cycles -system.iocache.overall_miss_latency::total 7041568092 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 47620 # number of demand (read+write) misses +system.iocache.demand_misses::total 47620 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 47620 # number of overall misses +system.iocache.overall_misses::total 47620 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 135466932 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 135466932 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 6926961160 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 6926961160 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 7062428092 # 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number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 47620 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 47620 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 47620 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 47620 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses @@ -330,14 +330,14 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150399.703212 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 150399.703212 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 147811.583048 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 147811.583048 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 147860.657497 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147860.657497 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 147860.657497 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 150518.813333 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 150518.813333 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 148265.435788 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 148265.435788 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 148308.023772 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 148308.023772 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 148308.023772 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 269004 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 25 # number of cycles access was blocked @@ -348,22 +348,22 @@ system.iocache.fast_writes 0 # nu system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 903 # 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number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88635000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88635000 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 4497207944 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 4497207944 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 4585842944 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 4585842944 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 4585842944 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses @@ -372,14 +372,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98364.341085 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 98364.341085 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 95804.857149 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 95804.857149 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 95853.388615 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 95853.388615 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 98483.333333 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 98483.333333 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 96258.731678 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 96258.731678 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 96300.775808 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 96300.775808 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -393,141 +393,141 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.numCycles 473010428 # number of cpu cycles simulated +system.cpu.numCycles 472946175 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 90027775 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 90027775 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1176793 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 84224638 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 81706962 # Number of BTB hits +system.cpu.BPredUnit.lookups 90027772 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 90027772 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1176455 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 84282590 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 81704922 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 31360026 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 446936699 # Number of instructions fetch has processed -system.cpu.fetch.Branches 90027775 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 81706962 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 169789390 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5321789 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 167863 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 104601282 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 37271 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 44086 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9371006 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 537925 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5262 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 310106612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.836098 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.376721 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 31264026 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 446943348 # Number of instructions fetch has processed +system.cpu.fetch.Branches 90027772 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 81704922 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 169792009 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 5327046 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 167003 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 104616235 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 37821 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 45804 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 481 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9365381 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 539972 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5058 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 310035010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.836765 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.376817 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140752877 45.39% 45.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1771842 0.57% 45.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72784841 23.47% 69.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 985545 0.32% 69.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1639332 0.53% 70.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3672529 1.18% 71.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1138013 0.37% 71.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1446532 0.47% 72.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 85915101 27.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140677603 45.37% 45.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1773611 0.57% 45.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72784877 23.48% 69.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 988899 0.32% 69.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1639325 0.53% 70.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3670845 1.18% 71.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1138945 0.37% 71.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1446155 0.47% 72.29% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 85914750 27.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 310106612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.190329 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.944877 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 36504487 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 100689087 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 164100014 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4706777 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4106247 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 876222772 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 974 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4106247 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 40918052 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 44290154 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10988643 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 163783570 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 46019946 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 872439032 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 9880 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 35250675 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3950071 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 31995010 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1394183444 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2488413838 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2488413278 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 560 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1347594272 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 46589165 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 469708 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 477213 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 48119615 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 18916713 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10445823 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1292985 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1005726 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 865744936 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1721292 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 864337925 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 123293 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 26001434 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 53514506 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 205573 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 310106612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.787228 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.396179 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 310035010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.190355 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.945019 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36438516 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 100672732 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 164105371 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4706760 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4111631 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 876235114 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1005 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4111631 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 40855551 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 44279722 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 10981847 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 163785428 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46020831 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 872430616 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 10252 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 35253394 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3952381 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31994944 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1394146617 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2488353855 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2488353319 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1347546781 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 46599829 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 470336 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 478135 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48126988 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 18909339 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10455877 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1294020 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1017517 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 865756561 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1721302 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 864328719 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 124616 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 26046990 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 53600910 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 205527 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 310035010 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.787842 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.396151 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 102391332 33.02% 33.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23760486 7.66% 40.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 19024925 6.13% 46.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7818761 2.52% 49.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 80618326 26.00% 75.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3106091 1.00% 76.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72752494 23.46% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 520993 0.17% 99.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 113204 0.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 102334281 33.01% 33.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23751530 7.66% 40.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 19011662 6.13% 46.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7830278 2.53% 49.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 80611792 26.00% 75.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3104970 1.00% 76.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72755101 23.47% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 522761 0.17% 99.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 112635 0.04% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 310106612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 310035010 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 162823 7.80% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.80% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1765220 84.55% 92.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 159742 7.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 164564 7.88% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.88% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1763434 84.48% 92.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 159280 7.63% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 296671 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 829442170 95.96% 96.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 297202 0.03% 0.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 829439322 95.96% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.00% # Type of FU issued @@ -556,250 +556,250 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.00% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.00% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.00% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25162510 2.91% 98.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9436574 1.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25154463 2.91% 98.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9437732 1.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 864337925 # Type of FU issued -system.cpu.iq.rate 1.827313 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2087785 # FU busy when requested +system.cpu.iq.FU_type_0::total 864328719 # Type of FU issued +system.cpu.iq.rate 1.827541 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2087278 # FU busy when requested system.cpu.iq.fu_busy_rate 0.002415 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2041131934 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 893478671 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 853934886 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 231 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 260 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 63 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 866128931 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 108 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1577690 # Number of loads that had data forwarded from stores +system.cpu.iq.int_inst_queue_reads 2041042185 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 893535851 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 853927067 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 224 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 866118699 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 96 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1579181 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3621025 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 20103 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 12189 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2042088 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3618734 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 20083 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12084 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2054359 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7821421 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4286 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7821519 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4487 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4106247 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27916479 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1927801 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 867466228 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 303428 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 18916713 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10445834 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 882766 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 975199 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15962 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 12189 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 699297 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 625213 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1324510 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 862446659 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24735217 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1891265 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4111631 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27910035 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1927143 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 867477863 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 297836 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 18909339 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10455877 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 883178 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 975186 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15536 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12084 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 697834 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 626380 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1324214 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 862437508 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24726867 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1891210 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 33929559 # number of memory reference insts executed -system.cpu.iew.exec_branches 86496146 # Number of branches executed -system.cpu.iew.exec_stores 9194342 # Number of stores executed -system.cpu.iew.exec_rate 1.823314 # Inst execution rate -system.cpu.iew.wb_sent 861961974 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 853934949 # cumulative count of insts written-back -system.cpu.iew.wb_producers 669649521 # num instructions producing a value -system.cpu.iew.wb_consumers 1918783501 # num instructions consuming a value +system.cpu.iew.exec_refs 33920253 # number of memory reference insts executed +system.cpu.iew.exec_branches 86495383 # Number of branches executed +system.cpu.iew.exec_stores 9193386 # Number of stores executed +system.cpu.iew.exec_rate 1.823543 # Inst execution rate +system.cpu.iew.wb_sent 861952908 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 853927121 # cumulative count of insts written-back +system.cpu.iew.wb_producers 669642895 # num instructions producing a value +system.cpu.iew.wb_consumers 1918737755 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.805319 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.348997 # average fanout of values written-back +system.cpu.iew.wb_rate 1.805548 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.349002 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 426531587 # The number of committed instructions -system.cpu.commit.commitCommittedOps 840543055 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 26818803 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1515717 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1181719 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 306015924 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.746730 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.861261 # Number of insts commited each cycle +system.cpu.commit.commitCommittedInsts 426515724 # The number of committed instructions +system.cpu.commit.commitCommittedOps 840516219 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 26857823 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1515773 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 1181578 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 305938932 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.747333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.861326 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 125070317 40.87% 40.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 14726015 4.81% 45.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4257326 1.39% 47.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 76646045 25.05% 72.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3895754 1.27% 73.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1793252 0.59% 73.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1102852 0.36% 74.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71997039 23.53% 97.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6527324 2.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 125006118 40.86% 40.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 14720749 4.81% 45.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4254060 1.39% 47.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 76641454 25.05% 72.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3896789 1.27% 73.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1794252 0.59% 73.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1101361 0.36% 74.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71996786 23.53% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6527363 2.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 306015924 # Number of insts commited each cycle -system.cpu.commit.committedInsts 426531587 # Number of instructions committed -system.cpu.commit.committedOps 840543055 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 305938932 # Number of insts commited each cycle +system.cpu.commit.committedInsts 426515724 # Number of instructions committed +system.cpu.commit.committedOps 840516219 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 23699431 # Number of memory references committed -system.cpu.commit.loads 15295685 # Number of loads committed -system.cpu.commit.membars 781577 # Number of memory barriers committed -system.cpu.commit.branches 85508404 # Number of branches committed +system.cpu.commit.refs 23692120 # Number of memory references committed +system.cpu.commit.loads 15290602 # Number of loads committed +system.cpu.commit.membars 781565 # Number of memory barriers committed +system.cpu.commit.branches 85505775 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 768361520 # Number of committed integer instructions. +system.cpu.commit.int_insts 768334838 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 6527324 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6527363 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1166770942 # The number of ROB reads -system.cpu.rob.rob_writes 1738844954 # The number of ROB writes -system.cpu.timesIdled 2997386 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 162903816 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9874668492 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 426531587 # Number of Instructions Simulated -system.cpu.committedOps 840543055 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 426531587 # Number of Instructions Simulated -system.cpu.cpi 1.108969 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.108969 # CPI: Total CPI of All Threads -system.cpu.ipc 0.901738 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.901738 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2163215430 # number of integer regfile reads -system.cpu.int_regfile_writes 1362691420 # number of integer regfile writes -system.cpu.fp_regfile_reads 63 # number of floating regfile reads -system.cpu.misc_regfile_reads 281069935 # number of misc regfile reads -system.cpu.misc_regfile_writes 403791 # number of misc regfile writes -system.cpu.icache.replacements 1071897 # number of replacements -system.cpu.icache.tagsinuse 510.429584 # Cycle average of tags in use -system.cpu.icache.total_refs 8228054 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 1072409 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 7.672496 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 56932855000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.429584 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.996933 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.996933 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 8228054 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8228054 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8228054 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8228054 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8228054 # number of overall hits -system.cpu.icache.overall_hits::total 8228054 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1142948 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1142948 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1142948 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1142948 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1142948 # number of overall misses -system.cpu.icache.overall_misses::total 1142948 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18865193488 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18865193488 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18865193488 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18865193488 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18865193488 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18865193488 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9371002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9371002 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9371002 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9371002 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9371002 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9371002 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121966 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.121966 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.121966 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.121966 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.121966 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.121966 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16505.732096 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16505.732096 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16505.732096 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16505.732096 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16505.732096 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3301994 # number of cycles access was blocked +system.cpu.rob.rob_reads 1166706140 # The number of ROB reads +system.cpu.rob.rob_writes 1738874776 # The number of ROB writes +system.cpu.timesIdled 2996123 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 162911165 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9872855838 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 426515724 # Number of Instructions Simulated +system.cpu.committedOps 840516219 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 426515724 # Number of Instructions Simulated +system.cpu.cpi 1.108860 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.108860 # CPI: Total CPI of All Threads +system.cpu.ipc 0.901827 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.901827 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2163141042 # number of integer regfile reads +system.cpu.int_regfile_writes 1362663536 # number of integer regfile writes +system.cpu.fp_regfile_reads 54 # number of floating regfile reads +system.cpu.misc_regfile_reads 281062978 # number of misc regfile reads +system.cpu.misc_regfile_writes 403820 # number of misc regfile writes +system.cpu.icache.replacements 1070658 # number of replacements +system.cpu.icache.tagsinuse 510.425099 # Cycle average of tags in use +system.cpu.icache.total_refs 8224431 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 1071170 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.677989 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 56932899000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.425099 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.996924 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.996924 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 8224431 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8224431 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8224431 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8224431 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8224431 # number of overall hits +system.cpu.icache.overall_hits::total 8224431 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1140947 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1140947 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1140947 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1140947 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1140947 # number of overall misses +system.cpu.icache.overall_misses::total 1140947 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18841256486 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18841256486 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18841256486 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18841256486 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18841256486 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18841256486 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9365378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9365378 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9365378 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9365378 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9365378 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9365378 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.121826 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.121826 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.121826 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.121826 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.121826 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.121826 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16513.700011 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16513.700011 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16513.700011 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16513.700011 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16513.700011 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3271992 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 399 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 8275.674185 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 8200.481203 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 1600 # number of writebacks -system.cpu.icache.writebacks::total 1600 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70415 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70415 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70415 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70415 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70415 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70415 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1072533 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1072533 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1072533 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1072533 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1072533 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1072533 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14734319994 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14734319994 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14734319994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14734319994 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14734319994 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14734319994 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114452 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114452 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114452 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114452 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13737.870997 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13737.870997 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13737.870997 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13737.870997 # average overall mshr miss latency +system.cpu.icache.writebacks::writebacks 1605 # number of writebacks +system.cpu.icache.writebacks::total 1605 # number of writebacks +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69655 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 69655 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 69655 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 69655 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 69655 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 69655 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1071292 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1071292 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1071292 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1071292 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1071292 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1071292 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14719464992 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14719464992 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14719464992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14719464992 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14719464992 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14719464992 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114389 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114389 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114389 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114389 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13739.918708 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13739.918708 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13739.918708 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13739.918708 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.replacements 11177 # number of replacements -system.cpu.itb_walker_cache.tagsinuse 6.030365 # Cycle average of tags in use -system.cpu.itb_walker_cache.total_refs 31227 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.sampled_refs 11191 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.avg_refs 2.790367 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.warmup_cycle 5136145388000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.030365 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376898 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.occ_percent::total 0.376898 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31228 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 31228 # number of ReadReq hits +system.cpu.itb_walker_cache.replacements 10504 # number of replacements +system.cpu.itb_walker_cache.tagsinuse 6.031363 # Cycle average of tags in use +system.cpu.itb_walker_cache.total_refs 31807 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.sampled_refs 10516 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.avg_refs 3.024629 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.warmup_cycle 5135227037000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker 6.031363 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker 0.376960 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.occ_percent::total 0.376960 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 31848 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 31848 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 3 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 3 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31231 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 31231 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31231 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 31231 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 12057 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 12057 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 12057 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 12057 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 12057 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 12057 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 192652500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 192652500 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 192652500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 192652500 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 192652500 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 192652500 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43285 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 43285 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 31851 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 31851 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 31851 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 31851 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 11386 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 11386 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 11386 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 11386 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 11386 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 11386 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 182254500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 182254500 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 182254500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 182254500 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 182254500 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 182254500 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 43234 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 43234 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 3 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43288 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 43288 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43288 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 43288 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.278549 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.278549 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.278530 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.278530 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.278530 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.278530 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 15978.477233 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 15978.477233 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 15978.477233 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 15978.477233 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 15978.477233 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 43237 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 43237 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 43237 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 43237 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.263358 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.263358 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.263339 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.263339 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.263339 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.263339 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 16006.894432 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 16006.894432 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 16006.894432 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 16006.894432 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 16006.894432 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -808,78 +808,78 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 1620 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 1620 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 12057 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 12057 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 12057 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 12057 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 12057 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 12057 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 155859527 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 155859527 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 155859527 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 155859527 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 155859527 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 155859527 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.278549 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.278549 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.278530 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.278530 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.278530 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12926.891184 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12926.891184 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12926.891184 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 1641 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 1641 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 11386 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 11386 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 11386 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 11386 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 11386 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 11386 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147453030 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147453030 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147453030 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147453030 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147453030 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147453030 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.263358 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.263358 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.263339 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.263339 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.263339 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 12950.380292 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 12950.380292 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 12950.380292 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.replacements 116226 # number of replacements -system.cpu.dtb_walker_cache.tagsinuse 12.942586 # Cycle average of tags in use -system.cpu.dtb_walker_cache.total_refs 138119 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.sampled_refs 116242 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.avg_refs 1.188202 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.warmup_cycle 5112881220000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 12.942586 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.808912 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.occ_percent::total 0.808912 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 138119 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 138119 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 138119 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 138119 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 138119 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 138119 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 117277 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 117277 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 117277 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 117277 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 117277 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 117277 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2115105000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2115105000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2115105000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 2115105000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2115105000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 2115105000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255396 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 255396 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255396 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 255396 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255396 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 255396 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.459197 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.459197 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.459197 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.459197 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.459197 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.459197 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 18035.121976 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 18035.121976 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 18035.121976 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 18035.121976 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 18035.121976 # average overall miss latency +system.cpu.dtb_walker_cache.replacements 117278 # number of replacements +system.cpu.dtb_walker_cache.tagsinuse 13.523999 # Cycle average of tags in use +system.cpu.dtb_walker_cache.total_refs 136775 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.sampled_refs 117293 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.avg_refs 1.166097 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.warmup_cycle 5112876101000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 13.523999 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.845250 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.occ_percent::total 0.845250 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 136779 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 136779 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 136779 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 136779 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 136779 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 136779 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 118304 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 118304 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 118304 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 118304 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 118304 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 118304 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 2123660000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 2123660000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 2123660000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 2123660000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 2123660000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 2123660000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 255083 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 255083 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 255083 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 255083 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 255083 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 255083 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.463786 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.463786 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.463786 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.463786 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.463786 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.463786 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 17950.872329 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 17950.872329 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 17950.872329 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 17950.872329 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 17950.872329 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -888,146 +888,146 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 36600 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 36600 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 117277 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 117277 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 117277 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 117277 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 117277 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 117277 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1760668506 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1760668506 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1760668506 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1760668506 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.459197 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.459197 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.459197 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.459197 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 15012.905395 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 15012.905395 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 15012.905395 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 37674 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 37674 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 118304 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 118304 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 118304 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 118304 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 118304 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 118304 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1766049009 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1766049009 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1766049009 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1766049009 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.463786 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.463786 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.463786 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.463786 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 14928.058299 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 14928.058299 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 14928.058299 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1674194 # number of replacements -system.cpu.dcache.tagsinuse 511.997520 # Cycle average of tags in use -system.cpu.dcache.total_refs 19015880 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1674706 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.354757 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1673136 # number of replacements +system.cpu.dcache.tagsinuse 511.997556 # Cycle average of tags in use +system.cpu.dcache.total_refs 19006106 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1673648 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 11.356095 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 36854000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997520 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997556 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999995 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 10936415 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10936415 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8076863 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8076863 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 19013278 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19013278 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19013278 # number of overall hits -system.cpu.dcache.overall_hits::total 19013278 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2432524 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2432524 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 317516 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 317516 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2750040 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2750040 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2750040 # number of overall misses -system.cpu.dcache.overall_misses::total 2750040 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 45245018000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 45245018000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10626959991 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10626959991 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 55871977991 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 55871977991 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 55871977991 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 55871977991 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 13368939 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13368939 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8394379 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8394379 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21763318 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21763318 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21763318 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21763318 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181953 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.181953 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037825 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.037825 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.126361 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.126361 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.126361 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.126361 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18600.029434 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 18600.029434 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33469.053500 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33469.053500 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 20316.787389 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 20316.787389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20316.787389 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20316.787389 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 26625491 # number of cycles access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 10928708 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10928708 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8074811 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8074811 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 19003519 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19003519 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19003519 # number of overall hits +system.cpu.dcache.overall_hits::total 19003519 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2430538 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2430538 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317333 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317333 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2747871 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2747871 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2747871 # number of overall misses +system.cpu.dcache.overall_misses::total 2747871 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 45186101000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 45186101000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10603069990 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10603069990 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55789170990 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55789170990 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55789170990 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55789170990 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13359246 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13359246 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8392144 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8392144 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21751390 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21751390 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21751390 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21751390 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.181937 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.181937 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037813 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.037813 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.126331 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.126331 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.126331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.126331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 18590.987263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 18590.987263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33413.070781 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33413.070781 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20302.689242 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 20302.689242 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 20302.689242 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 27875990 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4915 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 4957 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5417.190437 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5623.560621 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1573630 # number of writebacks -system.cpu.dcache.writebacks::total 1573630 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1050273 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1050273 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22706 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 22706 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1072979 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1072979 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1072979 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1072979 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1382251 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1382251 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294810 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 294810 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1677061 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1677061 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1677061 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1677061 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23310362534 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23310362534 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9362745997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9362745997 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32673108531 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 32673108531 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32673108531 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 32673108531 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207340500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207340500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386118500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386118500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86593459000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 86593459000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103393 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103393 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035120 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035120 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.077059 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077059 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.077059 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16864.059085 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16864.059085 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31758.576700 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31758.576700 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19482.361423 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19482.361423 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1572269 # number of writebacks +system.cpu.dcache.writebacks::total 1572269 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1049151 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1049151 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22726 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 22726 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1071877 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1071877 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1071877 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1071877 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1381387 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1381387 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 294607 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 294607 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1675994 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1675994 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1675994 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1675994 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23290713035 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23290713035 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9337845997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9337845997 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 32628559032 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 32628559032 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32628559032 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 32628559032 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207723000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207723000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1386731000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1386731000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86594454000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 86594454000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.103403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.103403 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035105 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.035105 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.077052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.077052 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.077052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16860.382380 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16860.382380 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31695.940684 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31695.940684 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19468.183676 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19468.183676 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 6570dc326..6a8db2c50 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -23,7 +23,7 @@ Built 1 zonelists. Total pages: 30458 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
Initializing CPU#0
PID hash table entries: 512 (order: 9, 4096 bytes)
-time.c: Detected 2000.000 MHz processor.
+time.c: Detected 2000.001 MHz processor.
Console: colour dummy device 80x25
console handover: boot [earlyser0] -> real [ttyS0]
Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)
@@ -39,7 +39,7 @@ ACPI: Core revision 20070126 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812497
+result 7812499
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini index d219b0faf..7b9ea05e8 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -642,20 +642,30 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 +dataAccessLatency=1 +dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU +resourceStalls=false size=32768 start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 +dataAccessLatency=1 +dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU +resourceStalls=false size=32768 start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -696,20 +706,30 @@ version=1 [system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 +dataAccessLatency=1 +dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU +resourceStalls=false size=32768 start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 [system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 +dataAccessLatency=1 +dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU +resourceStalls=false size=32768 start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 [system.l1_cntrl1.sequencer] type=RubySequencer @@ -746,11 +766,16 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 +dataAccessLatency=1 +dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU +resourceStalls=false size=4194304 start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 [system.pc] type=Pc @@ -995,7 +1020,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-x86.img +image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1015,7 +1040,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] @@ -1192,7 +1217,7 @@ header_cycles=1 use_default_range=true width=8 default=system.pc.pciconfig.pio -master=system.physmem.port[0] system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave +master=system.physmem.port system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave slave=system.pc.south_bridge.ide.dma system.pc.south_bridge.io_apic.int_master system.l1_cntrl0.sequencer.pio_port system.l1_cntrl1.sequencer.pio_port system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master [system.ruby] @@ -1219,74 +1244,104 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5 +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 print_config=false -routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 +routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.int_links0.node_b [system.ruby.network.topology.ext_links0] type=SimpleExtLink +children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.routers0 +int_node=system.ruby.network.topology.ext_links0.int_node latency=1 link_id=0 weight=1 +[system.ruby.network.topology.ext_links0.int_node] +type=BasicRouter +router_id=0 + [system.ruby.network.topology.ext_links1] type=SimpleExtLink +children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl1 -int_node=system.ruby.network.topology.routers1 +int_node=system.ruby.network.topology.ext_links1.int_node latency=1 link_id=1 weight=1 +[system.ruby.network.topology.ext_links1.int_node] +type=BasicRouter +router_id=1 + [system.ruby.network.topology.ext_links2] type=SimpleExtLink +children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.routers2 +int_node=system.ruby.network.topology.ext_links2.int_node latency=1 link_id=2 weight=1 +[system.ruby.network.topology.ext_links2.int_node] +type=BasicRouter +router_id=2 + [system.ruby.network.topology.ext_links3] type=SimpleExtLink +children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.routers3 +int_node=system.ruby.network.topology.ext_links3.int_node latency=1 link_id=3 weight=1 +[system.ruby.network.topology.ext_links3.int_node] +type=BasicRouter +router_id=3 + [system.ruby.network.topology.ext_links4] type=SimpleExtLink +children=int_node bandwidth_factor=16 ext_node=system.dma_cntrl0 -int_node=system.ruby.network.topology.routers4 +int_node=system.ruby.network.topology.ext_links4.int_node latency=1 link_id=4 weight=1 +[system.ruby.network.topology.ext_links4.int_node] +type=BasicRouter +router_id=4 + [system.ruby.network.topology.int_links0] type=SimpleIntLink +children=node_b bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.routers0 -node_b=system.ruby.network.topology.routers5 +node_a=system.ruby.network.topology.ext_links0.int_node +node_b=system.ruby.network.topology.int_links0.node_b weight=1 +[system.ruby.network.topology.int_links0.node_b] +type=BasicRouter +router_id=5 + [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=6 -node_a=system.ruby.network.topology.routers1 -node_b=system.ruby.network.topology.routers5 +node_a=system.ruby.network.topology.ext_links1.int_node +node_b=system.ruby.network.topology.int_links0.node_b weight=1 [system.ruby.network.topology.int_links2] @@ -1294,8 +1349,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=7 -node_a=system.ruby.network.topology.routers2 -node_b=system.ruby.network.topology.routers5 +node_a=system.ruby.network.topology.ext_links2.int_node +node_b=system.ruby.network.topology.int_links0.node_b weight=1 [system.ruby.network.topology.int_links3] @@ -1303,8 +1358,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=8 -node_a=system.ruby.network.topology.routers3 -node_b=system.ruby.network.topology.routers5 +node_a=system.ruby.network.topology.ext_links3.int_node +node_b=system.ruby.network.topology.int_links0.node_b weight=1 [system.ruby.network.topology.int_links4] @@ -1312,34 +1367,10 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=9 -node_a=system.ruby.network.topology.routers4 -node_b=system.ruby.network.topology.routers5 +node_a=system.ruby.network.topology.ext_links4.int_node +node_b=system.ruby.network.topology.int_links0.node_b weight=1 -[system.ruby.network.topology.routers0] -type=BasicRouter -router_id=0 - -[system.ruby.network.topology.routers1] -type=BasicRouter -router_id=1 - -[system.ruby.network.topology.routers2] -type=BasicRouter -router_id=2 - -[system.ruby.network.topology.routers3] -type=BasicRouter -router_id=3 - -[system.ruby.network.topology.routers4] -type=BasicRouter -router_id=4 - -[system.ruby.network.topology.routers5] -type=BasicRouter -router_id=5 - [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats index 1bd343c5c..29187e6ec 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,26 +1,26 @@ -Real time: Jun/04/2012 17:25:31 +Real time: Jul/22/2012 09:10:52 Profiler Stats -------------- -Elapsed_time_in_seconds: 842 -Elapsed_time_in_minutes: 14.0333 -Elapsed_time_in_hours: 0.233889 -Elapsed_time_in_days: 0.00974537 +Elapsed_time_in_seconds: 936 +Elapsed_time_in_minutes: 15.6 +Elapsed_time_in_hours: 0.26 +Elapsed_time_in_days: 0.0108333 -Virtual_time_in_seconds: 842.03 -Virtual_time_in_minutes: 14.0338 -Virtual_time_in_hours: 0.233897 -Virtual_time_in_days: 0.00974572 +Virtual_time_in_seconds: 935.71 +Virtual_time_in_minutes: 15.5952 +Virtual_time_in_hours: 0.259919 +Virtual_time_in_days: 0.01083 -Ruby_current_time: 10609379371 +Ruby_current_time: 10611136755 Ruby_start_time: 0 -Ruby_cycles: 10609379371 +Ruby_cycles: 10611136755 -mbytes_resident: 268.047 -mbytes_total: 470.199 -resident_ratio: 0.570071 +mbytes_resident: 255.668 +mbytes_total: 506.359 +resident_ratio: 0.504922 -ruby_cycles_executed: [ 10609379372 10609379372 ] +ruby_cycles_executed: [ 10611136756 10611136756 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 @@ -30,18 +30,18 @@ DMA-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 187820632 average: 1.00009 | standard deviation: 0.00953306 | 0 187803562 17070 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 189629563 average: 1.00009 | standard deviation: 0.00948804 | 0 189612491 17072 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 1 max: 171 count: 187820631 average: 3.39134 | standard deviation: 5.2186 | 0 0 0 185167359 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968687 360 299 324 1431839 442 29 55471 396 374 169 16721 201 124 40 32 58 1 1 3 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12771 11 6 12 99731 53 39 34 64890 57 7 6 12 49 6 0 1 5 5 ] -miss_latency_LD: [binsize: 1 max: 171 count: 14904214 average: 5.1415 | standard deviation: 9.3064 | 0 0 0 13521342 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127527 49 51 45 1194807 288 8 19874 224 232 85 4872 149 99 34 25 32 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2618 2 2 1 16177 17 7 5 15599 14 3 1 4 10 3 0 0 1 1 ] -miss_latency_ST: [binsize: 1 max: 171 count: 9480962 average: 5.51309 | standard deviation: 17.8961 | 0 0 0 9129497 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28986 16 10 12 180921 99 2 14858 85 68 52 1857 24 15 2 2 7 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4517 5 0 4 70891 24 21 21 48866 33 3 5 5 39 3 0 1 4 4 ] -miss_latency_IFETCH: [binsize: 1 max: 165 count: 162265044 average: 3.09464 | standard deviation: 1.92336 | 0 0 0 161451088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 795815 273 223 254 225 27 19 28 19 28 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5358 4 4 7 11621 10 11 8 3 9 0 0 3 ] -miss_latency_RMW_Read: [binsize: 1 max: 163 count: 492779 average: 6.1766 | standard deviation: 10.7903 | 0 0 0 426659 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10783 15 11 11 33161 10 0 12125 33 16 10 8497 16 8 2 2 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227 0 0 0 868 1 0 0 315 1 1 ] -miss_latency_Locked_RMW_Read: [binsize: 1 max: 161 count: 338816 average: 5.46921 | standard deviation: 8.08396 | 0 0 0 299957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5576 7 4 2 22725 18 0 8586 35 30 22 1495 12 2 2 3 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 0 0 0 174 1 0 0 107 ] -miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338816 average: 3 | standard deviation: 0 | 0 0 0 338816 ] -miss_latency_NULL: [binsize: 1 max: 171 count: 187820631 average: 3.39134 | standard deviation: 5.2186 | 0 0 0 185167359 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 968687 360 299 324 1431839 442 29 55471 396 374 169 16721 201 124 40 32 58 1 1 3 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12771 11 6 12 99731 53 39 34 64890 57 7 6 12 49 6 0 1 5 5 ] +miss_latency: [binsize: 1 max: 171 count: 189629562 average: 3.38837 | standard deviation: 5.2007 | 0 0 0 186971926 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 971398 311 266 292 1434090 392 51 54821 354 335 192 16528 110 142 35 32 50 3 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12755 7 7 13 100203 39 33 32 64996 57 6 5 14 47 5 3 0 3 3 ] +miss_latency_LD: [binsize: 1 max: 168 count: 14911026 average: 5.14403 | standard deviation: 9.30738 | 0 0 0 13525110 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 129680 44 39 43 1195959 268 20 19713 183 210 99 4905 71 117 32 25 30 3 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2553 0 1 1 16289 11 3 6 15564 15 4 3 4 14 2 1 ] +miss_latency_ST: [binsize: 1 max: 171 count: 9485677 average: 5.51946 | standard deviation: 17.9241 | 0 0 0 9133789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28572 9 9 4 181841 81 8 14495 87 61 54 1688 25 14 1 4 6 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4608 3 3 4 71166 22 16 18 49004 33 1 2 6 31 3 1 0 3 3 ] +miss_latency_IFETCH: [binsize: 1 max: 168 count: 164061652 average: 3.09372 | standard deviation: 1.91508 | 0 0 0 163246895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 796713 238 201 234 171 20 21 22 23 20 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5320 4 3 8 11707 6 12 7 5 9 1 0 4 1 0 1 ] +miss_latency_RMW_Read: [binsize: 1 max: 166 count: 493615 average: 6.17279 | standard deviation: 10.7803 | 0 0 0 427441 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10781 17 14 10 33213 10 0 12152 28 23 20 8480 5 3 1 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 228 0 0 0 868 0 1 1 313 0 0 0 0 1 ] +miss_latency_Locked_RMW_Read: [binsize: 1 max: 161 count: 338796 average: 5.46747 | standard deviation: 8.06826 | 0 0 0 299895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5652 3 3 1 22906 13 2 8439 33 21 19 1455 9 8 1 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46 0 0 0 173 0 1 0 110 ] +miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338796 average: 3 | standard deviation: 0 | 0 0 0 338796 ] +miss_latency_NULL: [binsize: 1 max: 171 count: 189629562 average: 3.38837 | standard deviation: 5.2007 | 0 0 0 186971926 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 971398 311 266 292 1434090 392 51 54821 354 335 192 16528 110 142 35 32 50 3 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12755 7 7 13 100203 39 33 32 64996 57 6 5 14 47 5 3 0 3 3 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -52,12 +52,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 1 max: 171 count: 14904214 average: 5.1415 | standard deviation: 9.3064 | 0 0 0 13521342 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 127527 49 51 45 1194807 288 8 19874 224 232 85 4872 149 99 34 25 32 1 1 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2618 2 2 1 16177 17 7 5 15599 14 3 1 4 10 3 0 0 1 1 ] -miss_latency_ST_NULL: [binsize: 1 max: 171 count: 9480962 average: 5.51309 | standard deviation: 17.8961 | 0 0 0 9129497 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28986 16 10 12 180921 99 2 14858 85 68 52 1857 24 15 2 2 7 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4517 5 0 4 70891 24 21 21 48866 33 3 5 5 39 3 0 1 4 4 ] -miss_latency_IFETCH_NULL: [binsize: 1 max: 165 count: 162265044 average: 3.09464 | standard deviation: 1.92336 | 0 0 0 161451088 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 795815 273 223 254 225 27 19 28 19 28 0 0 0 0 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5358 4 4 7 11621 10 11 8 3 9 0 0 3 ] -miss_latency_RMW_Read_NULL: [binsize: 1 max: 163 count: 492779 average: 6.1766 | standard deviation: 10.7903 | 0 0 0 426659 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10783 15 11 11 33161 10 0 12125 33 16 10 8497 16 8 2 2 6 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 227 0 0 0 868 1 0 0 315 1 1 ] -miss_latency_Locked_RMW_Read_NULL: [binsize: 1 max: 161 count: 338816 average: 5.46921 | standard deviation: 8.08396 | 0 0 0 299957 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5576 7 4 2 22725 18 0 8586 35 30 22 1495 12 2 2 3 6 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 51 0 0 0 174 1 0 0 107 ] -miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338816 average: 3 | standard deviation: 0 | 0 0 0 338816 ] +miss_latency_LD_NULL: [binsize: 1 max: 168 count: 14911026 average: 5.14403 | standard deviation: 9.30738 | 0 0 0 13525110 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 129680 44 39 43 1195959 268 20 19713 183 210 99 4905 71 117 32 25 30 3 1 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2553 0 1 1 16289 11 3 6 15564 15 4 3 4 14 2 1 ] +miss_latency_ST_NULL: [binsize: 1 max: 171 count: 9485677 average: 5.51946 | standard deviation: 17.9241 | 0 0 0 9133789 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28572 9 9 4 181841 81 8 14495 87 61 54 1688 25 14 1 4 6 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4608 3 3 4 71166 22 16 18 49004 33 1 2 6 31 3 1 0 3 3 ] +miss_latency_IFETCH_NULL: [binsize: 1 max: 168 count: 164061652 average: 3.09372 | standard deviation: 1.91508 | 0 0 0 163246895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 796713 238 201 234 171 20 21 22 23 20 0 0 0 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5320 4 3 8 11707 6 12 7 5 9 1 0 4 1 0 1 ] +miss_latency_RMW_Read_NULL: [binsize: 1 max: 166 count: 493615 average: 6.17279 | standard deviation: 10.7803 | 0 0 0 427441 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10781 17 14 10 33213 10 0 12152 28 23 20 8480 5 3 1 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 228 0 0 0 868 0 1 1 313 0 0 0 0 1 ] +miss_latency_Locked_RMW_Read_NULL: [binsize: 1 max: 161 count: 338796 average: 5.46747 | standard deviation: 8.06826 | 0 0 0 299895 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5652 3 3 1 22906 13 2 8439 33 21 19 1455 9 8 1 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 46 0 0 0 173 0 1 0 110 ] +miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338796 average: 3 | standard deviation: 0 | 0 0 0 338796 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -71,12 +71,12 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 13 count: 10850974 average: 0.59462 | standard deviation: 1.42374 | 9237583 1029 657 892 1609097 1059 106 119 110 244 9 6 16 47 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 | standard deviation: 0.296857 | 4737436 520 425 679 25631 106 3 1 10 5 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6086158 average: 1.04263 | standard deviation: 1.75725 | 4500147 509 232 213 1583466 953 103 118 100 239 9 6 16 47 ] +Total_delay_cycles: [binsize: 1 max: 13 count: 10872044 average: 0.594087 | standard deviation: 1.42322 | 9257017 966 601 871 1611047 867 138 98 114 242 5 7 16 55 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4773322 average: 0.0220343 | standard deviation: 0.294682 | 4746360 488 366 641 25333 123 1 2 5 3 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6098722 average: 1.04182 | standard deviation: 1.75681 | 4510657 478 235 230 1585714 744 137 96 109 239 5 7 16 55 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 83533 average: 0.0149761 | standard deviation: 0.225696 | 83067 123 97 98 116 28 0 0 0 4 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 9 count: 4681283 average: 0.0225067 | standard deviation: 0.297971 | 4654369 397 328 581 25515 78 3 1 10 1 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 82482 average: 0.0127543 | standard deviation: 0.207023 | 82092 101 67 103 99 17 0 0 0 3 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 8 count: 4690840 average: 0.0221975 | standard deviation: 0.295989 | 4664268 387 299 538 25234 106 1 2 5 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -87,82 +87,82 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4764816 average: 0.0223746 | Resource Usage -------------- page_size: 4096 -user_time: 841 +user_time: 935 system_time: 0 -page_reclaims: 69674 -page_faults: 18 +page_reclaims: 66867 +page_faults: 113 swaps: 0 -block_inputs: 16056 -block_outputs: 408 +block_inputs: 0 +block_outputs: 0 Network Stats ------------- -total_msg_count_Control: 8492901 67943208 -total_msg_count_Request_Control: 248654 1989232 -total_msg_count_Response_Data: 8788194 632749968 -total_msg_count_Response_Control: 10854297 86834376 -total_msg_count_Writeback_Data: 4753752 342270144 -total_msg_count_Writeback_Control: 282753 2262024 -total_msgs: 33420551 total_bytes: 1134048952 +total_msg_count_Control: 8507592 68060736 +total_msg_count_Request_Control: 245557 1964456 +total_msg_count_Response_Data: 8804181 633901032 +total_msg_count_Response_Control: 10879239 87033912 +total_msg_count_Writeback_Data: 4760235 342736920 +total_msg_count_Writeback_Control: 290208 2321664 +total_msgs: 33487012 total_bytes: 1136018720 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.0323999 - links_utilized_percent_switch_0_link_0: 0.0382499 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.02655 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 42688 341504 [ 42688 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 842729 60676488 [ 0 842729 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 488898 3911184 [ 0 488898 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 855066 6840528 [ 855066 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 40424 2910528 [ 0 40424 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 517774 4142192 [ 0 16296 501478 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 429162 30899664 [ 429108 54 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 34458 275664 [ 34458 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.0329182 + links_utilized_percent_switch_0_link_0: 0.0389055 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.0269309 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 42316 338528 [ 42316 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 857284 61724448 [ 0 857284 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 498762 3990096 [ 0 498762 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 869376 6955008 [ 869376 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 39863 2870136 [ 0 39863 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 527853 4222824 [ 0 16344 511509 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 435670 31368240 [ 435613 57 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 38325 306600 [ 38325 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0735359 - links_utilized_percent_switch_1_link_0: 0.0818749 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.0651969 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 40845 326760 [ 40845 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 1788501 128772072 [ 0 1788501 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 1235479 9883832 [ 0 1235479 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 1798206 14385648 [ 1798206 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 34071 2453112 [ 0 34071 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 1270539 10164312 [ 0 17798 1252741 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 1155422 83190384 [ 1155308 114 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 59793 478344 [ 59793 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.0731522 + links_utilized_percent_switch_1_link_0: 0.0814063 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.064898 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 40166 321328 [ 40166 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 1778465 128049480 [ 0 1778465 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1229916 9839328 [ 0 1229916 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 1788260 14306080 [ 1788260 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 33641 2422152 [ 0 33641 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1263724 10109792 [ 0 17462 1246262 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 1151075 82877400 [ 1150966 109 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 58411 467288 [ 58411 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.110241 - links_utilized_percent_switch_2_link_0: 0.0976111 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.122871 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Control: 2653272 21226176 [ 2653272 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 202919 14610168 [ 0 202919 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 1876808 15014464 [ 0 122589 1754219 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 1584584 114090048 [ 1584416 168 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 94251 754008 [ 94251 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 81588 652704 [ 81588 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 2677208 192758976 [ 0 2677208 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 1717623 13740984 [ 0 1717623 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.110433 + links_utilized_percent_switch_2_link_0: 0.0977505 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.123116 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 2657636 21261088 [ 2657636 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 203222 14631984 [ 0 203222 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 1880796 15046368 [ 0 123025 1757771 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 1586745 114245640 [ 1586579 166 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 96736 773888 [ 96736 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 178228 1425824 [ 178228 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 80593 644744 [ 80593 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 2682995 193175640 [ 0 2682995 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1722141 13777128 [ 0 1722141 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.00651138 - links_utilized_percent_switch_3_link_0: 0.00495717 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.00806559 bw: 16000 base_latency: 1 +links_utilized_percent_switch_3: 0.00653492 + links_utilized_percent_switch_3_link_0: 0.00498048 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.00808936 bw: 16000 base_latency: 1 - outgoing_messages_switch_3_link_0_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 95249 6857928 [ 0 95249 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 16914 135312 [ 0 16914 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 177695 12794040 [ 0 177695 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 112163 897304 [ 0 112163 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Control: 178228 1425824 [ 178228 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 95756 6894432 [ 0 95756 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 16939 135512 [ 0 16939 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 178228 12832416 [ 0 178228 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 112695 901560 [ 0 112695 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 @@ -173,104 +173,104 @@ links_utilized_percent_switch_4: 0 switch_5_inlinks: 5 switch_5_outlinks: 5 -links_utilized_percent_switch_5: 0.0445386 - links_utilized_percent_switch_5_link_0: 0.0382499 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.0818749 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_2: 0.0976111 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_3: 0.00495717 bw: 16000 base_latency: 1 +links_utilized_percent_switch_5: 0.0446086 + links_utilized_percent_switch_5_link_0: 0.0389055 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.0814063 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_2: 0.0977505 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_3: 0.00498048 bw: 16000 base_latency: 1 links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1 - outgoing_messages_switch_5_link_0_Request_Control: 42688 341504 [ 42688 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 842729 60676488 [ 0 842729 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 488898 3911184 [ 0 488898 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 40845 326760 [ 40845 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 1788501 128772072 [ 0 1788501 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 1235479 9883832 [ 0 1235479 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Control: 2653272 21226176 [ 2653272 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Response_Data: 202919 14610168 [ 0 202919 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Response_Control: 1876808 15014464 [ 0 122589 1754219 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Writeback_Data: 1584584 114090048 [ 1584416 168 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Writeback_Control: 94251 754008 [ 94251 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Control: 177695 1421560 [ 177695 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Response_Data: 95249 6857928 [ 0 95249 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Response_Control: 16914 135312 [ 0 16914 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Request_Control: 42316 338528 [ 42316 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 857284 61724448 [ 0 857284 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 498762 3990096 [ 0 498762 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 40166 321328 [ 40166 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 1778465 128049480 [ 0 1778465 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 1229916 9839328 [ 0 1229916 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Control: 2657636 21261088 [ 2657636 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Data: 203222 14631984 [ 0 203222 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Control: 1880796 15046368 [ 0 123025 1757771 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Data: 1586745 114245640 [ 1586579 166 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Control: 96736 773888 [ 96736 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Control: 178228 1425824 [ 178228 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Data: 95756 6894432 [ 0 95756 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Control: 16939 135512 [ 0 16939 0 0 0 0 0 0 0 0 ] base_latency: 1 Cache Stats: system.l1_cntrl0.L1IcacheMemory - system.l1_cntrl0.L1IcacheMemory_total_misses: 326846 - system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 326846 + system.l1_cntrl0.L1IcacheMemory_total_misses: 331052 + system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 331052 system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0 system.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100% - system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 326846 100% + system.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 331052 100% Cache Stats: system.l1_cntrl0.L1DcacheMemory - system.l1_cntrl0.L1DcacheMemory_total_misses: 528220 - system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 528220 + system.l1_cntrl0.L1DcacheMemory_total_misses: 538324 + system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 538324 system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl0.L1DcacheMemory_request_type_LD: 54.1774% - system.l1_cntrl0.L1DcacheMemory_request_type_ST: 45.8226% + system.l1_cntrl0.L1DcacheMemory_request_type_LD: 54.6959% + system.l1_cntrl0.L1DcacheMemory_request_type_ST: 45.3041% - system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 528220 100% + system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 538324 100% --- L1Cache --- - Event Counts - -Load [6224073 8680141 ] 14904214 -Ifetch [103471616 58793435 ] 162265051 -Store [5279560 5371813 ] 10651373 -Inv [16350 17912 ] 34262 -L1_Replacement [827635 1770998 ] 2598633 -Fwd_GETX [12252 11795 ] 24047 -Fwd_GETS [14082 11138 ] 25220 +Load [6302183 8608843 ] 14911026 +Ifetch [105452422 58609236 ] 164061658 +Store [5316807 5340077 ] 10656884 +Inv [16401 17571 ] 33972 +L1_Replacement [842231 1761215 ] 2603446 +Fwd_GETX [11967 11549 ] 23516 +Fwd_GETS [13944 11046 ] 24990 Fwd_GET_INSTR [4 0 ] 4 -Data [658 968 ] 1626 -Data_Exclusive [248296 1024255 ] 1272551 -DataS_fromL1 [11138 14086 ] 25224 -Data_all_Acks [582637 749192 ] 1331829 -Ack [12337 9705 ] 22042 -Ack_all [12995 10673 ] 23668 -WB_Ack [463566 1215101 ] 1678667 +Data [640 949 ] 1589 +Data_Exclusive [256580 1019234 ] 1275814 +DataS_fromL1 [11046 13948 ] 24994 +Data_all_Acks [589018 744334 ] 1333352 +Ack [12092 9795 ] 21887 +Ack_all [12732 10744 ] 23476 +WB_Ack [473938 1209377 ] 1683315 - Transitions - -NP Load [277889 1086402 ] 1364291 -NP Ifetch [326723 486562 ] 813285 -NP Store [224047 199057 ] 423104 -NP Inv [5639 4132 ] 9771 +NP Load [286086 1081309 ] 1367395 +NP Ifetch [330926 483173 ] 814099 +NP Store [226242 197757 ] 423999 +NP Inv [5584 4068 ] 9652 NP L1_Replacement [0 0 ] 0 -I Load [8287 10294 ] 18581 -I Ifetch [123 548 ] 671 -I Store [5660 5638 ] 11298 +I Load [8355 10166 ] 18521 +I Ifetch [126 532 ] 658 +I Store [5549 5528 ] 11077 I Inv [0 0 ] 0 -I L1_Replacement [8798 9094 ] 17892 +I L1_Replacement [8754 8728 ] 17482 -S Load [577238 501390 ] 1078628 -S Ifetch [103144768 58306320 ] 161451088 -S Store [12337 9705 ] 22042 -S Inv [10590 13636 ] 24226 -S L1_Replacement [355271 546803 ] 902074 +S Load [576650 500308 ] 1076958 +S Ifetch [105121368 58125527 ] 163246895 +S Store [12092 9795 ] 21887 +S Inv [10695 13362 ] 24057 +S L1_Replacement [359539 543110 ] 902649 -E Load [1142385 2670000 ] 3812385 +E Load [1186542 2631089 ] 3817631 E Ifetch [0 0 ] 0 -E Store [81265 85104 ] 166369 -E Inv [67 30 ] 97 -E L1_Replacement [165622 937435 ] 1103057 -E Fwd_GETX [352 103 ] 455 -E Fwd_GETS [877 1394 ] 2271 +E Store [82337 84568 ] 166905 +E Inv [65 32 ] 97 +E L1_Replacement [172847 933185 ] 1106032 +E Fwd_GETX [241 150 ] 391 +E Fwd_GETS [923 1251 ] 2174 E Fwd_GET_INSTR [0 0 ] 0 -M Load [4218274 4412055 ] 8630329 +M Load [4244550 4385971 ] 8630521 M Ifetch [0 0 ] 0 -M Store [4956251 5072309 ] 10028560 -M Inv [54 114 ] 168 -M L1_Replacement [297944 277666 ] 575610 -M Fwd_GETX [11900 11692 ] 23592 -M Fwd_GETS [13205 9744 ] 22949 +M Store [4990587 5042429 ] 10033016 +M Inv [57 109 ] 166 +M L1_Replacement [301091 276192 ] 577283 +M Fwd_GETX [11726 11399 ] 23125 +M Fwd_GETS [13021 9795 ] 22816 M Fwd_GET_INSTR [4 0 ] 4 IS Load [0 0 ] 0 @@ -278,17 +278,17 @@ IS Ifetch [0 0 ] 0 IS Store [0 0 ] 0 IS Inv [0 0 ] 0 IS L1_Replacement [0 0 ] 0 -IS Data_Exclusive [248296 1024255 ] 1272551 -IS DataS_fromL1 [11138 14086 ] 25224 -IS Data_all_Acks [353588 545465 ] 899053 +IS Data_Exclusive [256580 1019234 ] 1275814 +IS DataS_fromL1 [11046 13948 ] 24994 +IS Data_all_Acks [357867 541998 ] 899865 IM Load [0 0 ] 0 IM Ifetch [0 0 ] 0 IM Store [0 0 ] 0 IM Inv [0 0 ] 0 IM L1_Replacement [0 0 ] 0 -IM Data [658 968 ] 1626 -IM Data_all_Acks [229049 203727 ] 432776 +IM Data [640 949 ] 1589 +IM Data_all_Acks [231151 202336 ] 433487 IM Ack [0 0 ] 0 SM Load [0 0 ] 0 @@ -296,8 +296,8 @@ SM Ifetch [0 0 ] 0 SM Store [0 0 ] 0 SM Inv [0 0 ] 0 SM L1_Replacement [0 0 ] 0 -SM Ack [12337 9705 ] 22042 -SM Ack_all [12995 10673 ] 23668 +SM Ack [12092 9795 ] 21887 +SM Ack_all [12732 10744 ] 23476 IS_I Load [0 0 ] 0 IS_I Ifetch [0 0 ] 0 @@ -309,14 +309,14 @@ IS_I DataS_fromL1 [0 0 ] 0 IS_I Data_all_Acks [0 0 ] 0 M_I Load [0 0 ] 0 -M_I Ifetch [2 5 ] 7 +M_I Ifetch [2 4 ] 6 M_I Store [0 0 ] 0 M_I Inv [0 0 ] 0 M_I L1_Replacement [0 0 ] 0 M_I Fwd_GETX [0 0 ] 0 M_I Fwd_GETS [0 0 ] 0 M_I Fwd_GET_INSTR [0 0 ] 0 -M_I WB_Ack [463566 1215101 ] 1678667 +M_I WB_Ack [473938 1209377 ] 1683315 SINK_WB_ACK Load [0 0 ] 0 SINK_WB_ACK Ifetch [0 0 ] 0 @@ -326,97 +326,97 @@ SINK_WB_ACK L1_Replacement [0 0 ] 0 SINK_WB_ACK WB_Ack [0 0 ] 0 Cache Stats: system.l1_cntrl1.L1IcacheMemory - system.l1_cntrl1.L1IcacheMemory_total_misses: 487110 - system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 487110 + system.l1_cntrl1.L1IcacheMemory_total_misses: 483705 + system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 483705 system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0 system.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100% - system.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 487110 100% + system.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 483705 100% Cache Stats: system.l1_cntrl1.L1DcacheMemory - system.l1_cntrl1.L1DcacheMemory_total_misses: 1311096 - system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1311096 + system.l1_cntrl1.L1DcacheMemory_total_misses: 1304555 + system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1304555 system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0 system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0 - system.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.6473% - system.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.3527% + system.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.6665% + system.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.3335% - system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1311096 100% + system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1304555 100% Cache Stats: system.l2_cntrl0.L2cacheMemory - system.l2_cntrl0.L2cacheMemory_total_misses: 226966 - system.l2_cntrl0.L2cacheMemory_total_demand_misses: 226966 + system.l2_cntrl0.L2cacheMemory_total_misses: 226738 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 226738 system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.l2_cntrl0.L2cacheMemory_request_type_GETS: 26.2969% - system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.50861% - system.l2_cntrl0.L2cacheMemory_request_type_GETX: 66.1945% + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 26.2245% + system.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.53822% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 66.2372% - system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 226966 100% + system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 226738 100% --- L2Cache --- - Event Counts - -L1_GET_INSTR [813956 ] 813956 -L1_GETS [1383116 ] 1383116 -L1_GETX [434406 ] 434406 -L1_UPGRADE [22042 ] 22042 -L1_PUTX [1678667 ] 1678667 +L1_GET_INSTR [814757 ] 814757 +L1_GETS [1386175 ] 1386175 +L1_GETX [435076 ] 435076 +L1_UPGRADE [21887 ] 21887 +L1_PUTX [1683315 ] 1683315 L1_PUTX_old [0 ] 0 Fwd_L1_GETX [0 ] 0 Fwd_L1_GETS [0 ] 0 Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [95206 ] 95206 -L2_Replacement_clean [16957 ] 16957 -Mem_Data [177695 ] 177695 -Mem_Ack [112163 ] 112163 -WB_Data [24702 ] 24702 -WB_Data_clean [690 ] 690 -Ack [1945 ] 1945 -Ack_all [8481 ] 8481 -Unblock [25224 ] 25224 +L2_Replacement [95713 ] 95713 +L2_Replacement_clean [16982 ] 16982 +Mem_Data [178228 ] 178228 +Mem_Ack [112695 ] 112695 +WB_Data [24497 ] 24497 +WB_Data_clean [663 ] 663 +Ack [1889 ] 1889 +Ack_all [8441 ] 8441 +Unblock [24994 ] 24994 Unblock_Cancel [0 ] 0 -Exclusive_Unblock [1728995 ] 1728995 +Exclusive_Unblock [1732777 ] 1732777 MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR [17038 ] 17038 -NP L1_GETS [34465 ] 34465 -NP L1_GETX [126192 ] 126192 +NP L1_GET_INSTR [17088 ] 17088 +NP L1_GETS [34471 ] 34471 +NP L1_GETX [126669 ] 126669 NP L1_PUTX [0 ] 0 NP L1_PUTX_old [0 ] 0 -SS L1_GET_INSTR [796726 ] 796726 -SS L1_GETS [85101 ] 85101 -SS L1_GETX [1832 ] 1832 -SS L1_UPGRADE [22042 ] 22042 +SS L1_GET_INSTR [797476 ] 797476 +SS L1_GETS [85112 ] 85112 +SS L1_GETX [1790 ] 1790 +SS L1_UPGRADE [21887 ] 21887 SS L1_PUTX [0 ] 0 SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [266 ] 266 -SS L2_Replacement_clean [8118 ] 8118 +SS L2_Replacement [269 ] 269 +SS L2_Replacement_clean [8075 ] 8075 SS MEM_Inv [0 ] 0 -M L1_GET_INSTR [188 ] 188 -M L1_GETS [1238086 ] 1238086 -M L1_GETX [282331 ] 282331 +M L1_GET_INSTR [189 ] 189 +M L1_GETS [1241343 ] 1241343 +M L1_GETX [283101 ] 283101 M L1_PUTX [0 ] 0 M L1_PUTX_old [0 ] 0 -M L2_Replacement [94758 ] 94758 -M L2_Replacement_clean [8756 ] 8756 +M L2_Replacement [95264 ] 95264 +M L2_Replacement_clean [8824 ] 8824 M MEM_Inv [0 ] 0 MT L1_GET_INSTR [4 ] 4 -MT L1_GETS [25220 ] 25220 -MT L1_GETX [24047 ] 24047 -MT L1_PUTX [1678667 ] 1678667 +MT L1_GETS [24990 ] 24990 +MT L1_GETX [23516 ] 23516 +MT L1_PUTX [1683315 ] 1683315 MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [182 ] 182 +MT L2_Replacement [180 ] 180 MT L2_Replacement_clean [83 ] 83 MT MEM_Inv [0 ] 0 @@ -426,7 +426,7 @@ M_I L1_GETX [0 ] 0 M_I L1_UPGRADE [0 ] 0 M_I L1_PUTX [0 ] 0 M_I L1_PUTX_old [0 ] 0 -M_I Mem_Ack [112163 ] 112163 +M_I Mem_Ack [112695 ] 112695 M_I MEM_Inv [0 ] 0 MT_I L1_GET_INSTR [0 ] 0 @@ -435,7 +435,7 @@ MT_I L1_GETX [0 ] 0 MT_I L1_UPGRADE [0 ] 0 MT_I L1_PUTX [0 ] 0 MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [125 ] 125 +MT_I WB_Data [123 ] 123 MT_I WB_Data_clean [0 ] 0 MT_I Ack_all [57 ] 57 MT_I MEM_Inv [0 ] 0 @@ -456,8 +456,8 @@ I_I L1_GETX [0 ] 0 I_I L1_UPGRADE [0 ] 0 I_I L1_PUTX [0 ] 0 I_I L1_PUTX_old [0 ] 0 -I_I Ack [1679 ] 1679 -I_I Ack_all [8118 ] 8118 +I_I Ack [1633 ] 1633 +I_I Ack_all [8075 ] 8075 S_I L1_GET_INSTR [0 ] 0 S_I L1_GETS [0 ] 0 @@ -465,8 +465,8 @@ S_I L1_GETX [0 ] 0 S_I L1_UPGRADE [0 ] 0 S_I L1_PUTX [0 ] 0 S_I L1_PUTX_old [0 ] 0 -S_I Ack [266 ] 266 -S_I Ack_all [266 ] 266 +S_I Ack [256 ] 256 +S_I Ack_all [269 ] 269 S_I MEM_Inv [0 ] 0 ISS L1_GET_INSTR [0 ] 0 @@ -476,7 +476,7 @@ ISS L1_PUTX [0 ] 0 ISS L1_PUTX_old [0 ] 0 ISS L2_Replacement [0 ] 0 ISS L2_Replacement_clean [0 ] 0 -ISS Mem_Data [34465 ] 34465 +ISS Mem_Data [34471 ] 34471 ISS MEM_Inv [0 ] 0 IS L1_GET_INSTR [0 ] 0 @@ -486,7 +486,7 @@ IS L1_PUTX [0 ] 0 IS L1_PUTX_old [0 ] 0 IS L2_Replacement [0 ] 0 IS L2_Replacement_clean [0 ] 0 -IS Mem_Data [17038 ] 17038 +IS Mem_Data [17088 ] 17088 IS MEM_Inv [0 ] 0 IM L1_GET_INSTR [0 ] 0 @@ -496,11 +496,11 @@ IM L1_PUTX [0 ] 0 IM L1_PUTX_old [0 ] 0 IM L2_Replacement [0 ] 0 IM L2_Replacement_clean [0 ] 0 -IM Mem_Data [126192 ] 126192 +IM Mem_Data [126669 ] 126669 IM MEM_Inv [0 ] 0 SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [174 ] 174 +SS_MB L1_GETS [197 ] 197 SS_MB L1_GETX [0 ] 0 SS_MB L1_UPGRADE [0 ] 0 SS_MB L1_PUTX [0 ] 0 @@ -508,19 +508,19 @@ SS_MB L1_PUTX_old [0 ] 0 SS_MB L2_Replacement [0 ] 0 SS_MB L2_Replacement_clean [0 ] 0 SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [23874 ] 23874 +SS_MB Exclusive_Unblock [23677 ] 23677 SS_MB MEM_Inv [0 ] 0 MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [70 ] 70 -MT_MB L1_GETX [4 ] 4 +MT_MB L1_GETS [62 ] 62 +MT_MB L1_GETX [0 ] 0 MT_MB L1_UPGRADE [0 ] 0 MT_MB L1_PUTX [0 ] 0 MT_MB L1_PUTX_old [0 ] 0 MT_MB L2_Replacement [0 ] 0 MT_MB L2_Replacement_clean [0 ] 0 MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [1705121 ] 1705121 +MT_MB Exclusive_Unblock [1709100 ] 1709100 MT_MB MEM_Inv [0 ] 0 M_MB L1_GET_INSTR [0 ] 0 @@ -542,9 +542,9 @@ MT_IIB L1_PUTX [0 ] 0 MT_IIB L1_PUTX_old [0 ] 0 MT_IIB L2_Replacement [0 ] 0 MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [24523 ] 24523 -MT_IIB WB_Data_clean [689 ] 689 -MT_IIB Unblock [12 ] 12 +MT_IIB WB_Data [24325 ] 24325 +MT_IIB WB_Data_clean [663 ] 663 +MT_IIB Unblock [6 ] 6 MT_IIB MEM_Inv [0 ] 0 MT_IB L1_GET_INSTR [0 ] 0 @@ -555,8 +555,8 @@ MT_IB L1_PUTX [0 ] 0 MT_IB L1_PUTX_old [0 ] 0 MT_IB L2_Replacement [0 ] 0 MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [11 ] 11 -MT_IB WB_Data_clean [1 ] 1 +MT_IB WB_Data [6 ] 6 +MT_IB WB_Data_clean [0 ] 0 MT_IB Unblock_Cancel [0 ] 0 MT_IB MEM_Inv [0 ] 0 @@ -568,41 +568,41 @@ MT_SB L1_PUTX [0 ] 0 MT_SB L1_PUTX_old [0 ] 0 MT_SB L2_Replacement [0 ] 0 MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [25212 ] 25212 +MT_SB Unblock [24988 ] 24988 MT_SB MEM_Inv [0 ] 0 Memory controller: system.dir_cntrl0.memBuffer: - memory_total_requests: 272944 - memory_reads: 177695 - memory_writes: 95249 - memory_refreshes: 4108449 - memory_total_request_delays: 25207 - memory_delays_per_request: 0.0923523 - memory_delays_in_input_queue: 7 + memory_total_requests: 273984 + memory_reads: 178228 + memory_writes: 95756 + memory_refreshes: 4121604 + memory_total_request_delays: 24710 + memory_delays_per_request: 0.0901877 + memory_delays_in_input_queue: 14 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 25200 - memory_stalls_for_bank_busy: 11193 + memory_delays_stalled_at_head_of_bank_queue: 24696 + memory_stalls_for_bank_busy: 10948 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 2202 - memory_stalls_for_bus: 11804 + memory_stalls_for_arbitration: 2078 + memory_stalls_for_bus: 11665 memory_stalls_for_tfaw: 0 memory_stalls_for_read_write_turnaround: 0 - memory_stalls_for_read_read_turnaround: 1 - accesses_per_bank: 8796 9232 8713 8487 8759 8199 8936 8313 8486 8359 8337 9440 8301 8128 8185 7202 8172 8248 8224 8141 8420 8367 8241 8178 8468 8442 8634 9202 9127 8950 10053 8204 + memory_stalls_for_read_read_turnaround: 5 + accesses_per_bank: 8772 9164 8720 8601 8832 8296 9047 8408 8557 8367 8357 9453 8328 8124 8143 7165 8279 8292 8242 8119 8483 8396 8265 8262 8529 8487 8608 9184 9135 8956 10142 8271 --- Directory --- - Event Counts - -Fetch [177695 ] 177695 -Data [95249 ] 95249 -Memory_Data [177695 ] 177695 -Memory_Ack [95249 ] 95249 +Fetch [178228 ] 178228 +Data [95756 ] 95756 +Memory_Data [178228 ] 178228 +Memory_Ack [95756 ] 95756 DMA_READ [0 ] 0 DMA_WRITE [0 ] 0 -CleanReplacement [16914 ] 16914 +CleanReplacement [16939 ] 16939 - Transitions - -I Fetch [177695 ] 177695 +I Fetch [178228 ] 178228 I DMA_READ [0 ] 0 I DMA_WRITE [0 ] 0 @@ -618,20 +618,20 @@ ID_W Memory_Ack [0 ] 0 ID_W DMA_READ [0 ] 0 ID_W DMA_WRITE [0 ] 0 -M Data [95249 ] 95249 +M Data [95756 ] 95756 M DMA_READ [0 ] 0 M DMA_WRITE [0 ] 0 -M CleanReplacement [16914 ] 16914 +M CleanReplacement [16939 ] 16939 IM Fetch [0 ] 0 IM Data [0 ] 0 -IM Memory_Data [177695 ] 177695 +IM Memory_Data [178228 ] 178228 IM DMA_READ [0 ] 0 IM DMA_WRITE [0 ] 0 MI Fetch [0 ] 0 MI Data [0 ] 0 -MI Memory_Ack [95249 ] 95249 +MI Memory_Ack [95756 ] 95756 MI DMA_READ [0 ] 0 MI DMA_WRITE [0 ] 0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr index 62578ab56..a4244c4ca 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr @@ -3,8 +3,10 @@ warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. warn: instruction 'fxsave' unimplemented +warn: x86 cpuid: unknown family 0x8086 warn: instruction 'wbinvd' unimplemented warn: instruction 'wbinvd' unimplemented +warn: x86 cpuid: unknown family 0x8086 hack: Assuming logical destinations are 1 << id. warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout index 9c27e2eb7..00f64894a 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout @@ -1,12 +1,15 @@ +Redirecting stdout to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout +Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:03:01 -gem5 started Jul 2 2012 15:09:17 -gem5 executing on zizzer -command line: build/X86_MESI_CMP_directory/gem5.fast -d build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/fast/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory +gem5 compiled Jul 22 2012 08:55:10 +gem5 started Jul 22 2012 08:55:16 +gem5 executing on ribera.cs.wisc.edu +command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp + 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5305568291500 because m5_exit instruction encountered +Exiting @ tick 5305568377500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index b9331fa8f..90df3051e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -1,77 +1,107 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 5.305568 # Number of seconds simulated -sim_ticks 5305568291500 # Number of ticks simulated -final_tick 5305568291500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 5305568377500 # Number of ticks simulated +final_tick 5305568377500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 254586 # Simulator instruction rate (inst/s) -host_op_rate 522269 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 9722568027 # Simulator tick rate (ticks/s) -host_mem_usage 466304 # Number of bytes of host memory used -host_seconds 545.70 # Real time elapsed on the host -sim_insts 138926459 # Number of instructions simulated -sim_ops 285000258 # Number of ops (including micro ops) simulated +host_inst_rate 148548 # Simulator instruction rate (inst/s) +host_op_rate 304739 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5673062484 # Simulator tick rate (ticks/s) +host_mem_usage 518516 # Number of bytes of host memory used +host_seconds 935.22 # Real time elapsed on the host +sim_insts 138925597 # Number of instructions simulated +sim_ops 284998538 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 131880 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 65368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 843624624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 40107648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 843619360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 40106316 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 91872 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 42696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 468878472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 53485285 # Number of bytes read from this memory -system.physmem.bytes_read::total 1406463005 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 843624624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 468878472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1312503096 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 468873856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 53484588 # Number of bytes read from this memory +system.physmem.bytes_read::total 1406451096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 843619360 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 468873856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1312493216 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 32434308 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 35512736 # Number of bytes written to this memory -system.physmem.bytes_written::total 70938164 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 32433610 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 35512400 # Number of bytes written to this memory +system.physmem.bytes_written::total 70937130 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 16485 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 8171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 105453078 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 6721984 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 105452420 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6721793 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 11484 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 5337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 58609809 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8980290 # Number of read requests responded to by this memory -system.physmem.num_reads::total 179807449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58609232 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8980167 # Number of read requests responded to by this memory +system.physmem.num_reads::total 179805900 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4872641 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4951979 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9871358 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4872539 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 4951932 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9871209 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 6627 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 24857 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 12321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 159007401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7559539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 159006406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7559287 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 17316 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 8047 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 88374788 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 10080972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 265091867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 159007401 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 88374788 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 247382189 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 88373916 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10080840 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 265089618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 159006406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 88373916 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 247380322 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 563767 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6113258 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6693484 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13370512 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6113126 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6693420 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13370317 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::pc.south_bridge.ide 570394 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 24857 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 12324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 159007401 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13672797 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 159006406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13672414 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 17316 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 8047 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 88374788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16774456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 278462379 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 88373916 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 16774261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 278459935 # Total bandwidth to/from this memory (bytes/s) +system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads +system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes +system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -84,50 +114,50 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.numCycles 10611136583 # number of cpu cycles simulated +system.cpu0.numCycles 10611136755 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 90467543 # Number of instructions committed -system.cpu0.committedOps 191745753 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 172320951 # Number of integer alu accesses +system.cpu0.committedInsts 90467113 # Number of instructions committed +system.cpu0.committedOps 191744891 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 172320091 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 0 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 18433460 # number of instructions that are conditional controls -system.cpu0.num_int_insts 172320951 # number of integer instructions +system.cpu0.num_conditional_control_insts 18433408 # number of instructions that are conditional controls +system.cpu0.num_int_insts 172320091 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 529440727 # number of times the integer registers were read -system.cpu0.num_int_register_writes 286411795 # number of times the integer registers were written +system.cpu0.num_int_register_reads 529438037 # number of times the integer registers were read +system.cpu0.num_int_register_writes 286410601 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 19683524 # number of memory refs -system.cpu0.num_load_insts 14800104 # Number of load instructions -system.cpu0.num_store_insts 4883420 # Number of store instructions -system.cpu0.num_idle_cycles 10087380547.886099 # Number of idle cycles -system.cpu0.num_busy_cycles 523756035.113901 # Number of busy cycles +system.cpu0.num_mem_refs 19683230 # number of memory refs +system.cpu0.num_load_insts 14799913 # Number of load instructions +system.cpu0.num_store_insts 4883317 # Number of store instructions +system.cpu0.num_idle_cycles 10087385086.886099 # Number of idle cycles +system.cpu0.num_busy_cycles 523751668.113901 # Number of busy cycles system.cpu0.not_idle_fraction 0.049359 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.950641 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu1.numCycles 10608184508 # number of cpu cycles simulated +system.cpu1.numCycles 10608184676 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48458916 # Number of instructions committed -system.cpu1.committedOps 93254505 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 88898001 # Number of integer alu accesses +system.cpu1.committedInsts 48458484 # Number of instructions committed +system.cpu1.committedOps 93253647 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 88897203 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 0 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 8156206 # number of instructions that are conditional controls -system.cpu1.num_int_insts 88898001 # number of integer instructions +system.cpu1.num_conditional_control_insts 8156142 # number of instructions that are conditional controls +system.cpu1.num_int_insts 88897203 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 272266493 # number of times the integer registers were read -system.cpu1.num_int_register_writes 138281277 # number of times the integer registers were written +system.cpu1.num_int_register_reads 272264147 # number of times the integer registers were read +system.cpu1.num_int_register_writes 138280138 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 14383510 # number of memory refs -system.cpu1.num_load_insts 9129721 # Number of load instructions -system.cpu1.num_store_insts 5253789 # Number of store instructions -system.cpu1.num_idle_cycles 10274260882.632458 # Number of idle cycles -system.cpu1.num_busy_cycles 333923625.367543 # Number of busy cycles +system.cpu1.num_mem_refs 14383325 # number of memory refs +system.cpu1.num_load_insts 9129593 # Number of load instructions +system.cpu1.num_store_insts 5253732 # Number of store instructions +system.cpu1.num_idle_cycles 10274264583.773684 # Number of idle cycles +system.cpu1.num_busy_cycles 333920092.226317 # Number of busy cycles system.cpu1.not_idle_fraction 0.031478 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.968522 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal index 4761ea437..b43e07266 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal @@ -39,7 +39,7 @@ CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line) CPU: L2 Cache: 1024K (64 bytes/line)
Freeing SMP alternatives: 34k freed
Using local APIC timer interrupts.
-result 7812492
+result 7812491
Detected 7.812 MHz APIC timer.
Booting processor 1/2 APIC 0x1
Initializing CPU#1
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