diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:41 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-09-25 11:49:41 -0500 |
| commit | 91e74beee60b2085d18dfbfd51018dce2c779d8d (patch) | |
| tree | 96a71f2f316d24e9378bc3a68df207880e0eccca /tests/long | |
| parent | 80a26a3e39874dab7c0b51cd5ce0258039494e30 (diff) | |
| download | gem5-91e74beee60b2085d18dfbfd51018dce2c779d8d.tar.xz | |
ARM: update stats for bp and squash fixes.
Diffstat (limited to 'tests/long')
84 files changed, 8435 insertions, 8204 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 35fda0d55..f66d752af 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -10,13 +10,15 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +clock=1 +dtb_filename= early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -37,12 +39,11 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] @@ -63,7 +64,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -134,7 +135,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -184,7 +184,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -201,8 +200,8 @@ walker=system.cpu.checker.dtb.walker [system.cpu.checker.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[5] @@ -214,8 +213,8 @@ walker=system.cpu.checker.itb.walker [system.cpu.checker.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[4] @@ -227,16 +226,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -255,8 +256,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -528,16 +529,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -559,8 +562,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -586,16 +589,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 +hit_latency=50000 is_top_level=false -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50000 size=1024 subblock_size=0 system=system @@ -611,16 +616,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=92 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=4194304 subblock_size=0 system=system @@ -645,9 +652,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -661,8 +669,9 @@ pio=system.membus.default [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=true -file= in_addr_map=true latency=30000 latency_var=0 @@ -682,17 +691,19 @@ system=system [system.realview.a9scu] type=A9SCU +clock=1 pio_addr=520093696 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268451840 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -736,16 +747,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=2 disks=system.cf0 io_shift=1 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=2 pci_dev=7 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.realview system=system config=system.iobus.master[8] @@ -758,8 +768,6 @@ amba_id=1315089 clock=41667 gic=system.realview.gic int_num=55 -max_backoff_delay=10000000 -min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 system=system @@ -770,17 +778,19 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268632064 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake +clock=1 fake_mem=true pio_addr=1073741824 -pio_latency=1000 +pio_latency=100000 pio_size=536870912 ret_bad_addr=false ret_data16=65535 @@ -794,6 +804,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic +clock=1 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -807,39 +818,43 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268513280 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268517376 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268521472 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=52 is_mouse=false pio_addr=268460032 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[5] @@ -847,21 +862,23 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=53 is_mouse=true pio_addr=268464128 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake +clock=1 fake_mem=false pio_addr=520101888 -pio_latency=1000 +pio_latency=100000 pio_size=4095 ret_bad_addr=false ret_data16=65535 @@ -880,23 +897,25 @@ gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268455936 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 @@ -907,9 +926,10 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl +clock=1 idreg=0 pio_addr=268435456 -pio_latency=1000 +pio_latency=100000 proc_id0=201326592 proc_id1=201327138 system=system @@ -918,11 +938,12 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 +clock=1 gic=system.realview.gic int_delay=100000 int_num=42 pio_addr=268529664 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] @@ -930,73 +951,80 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268492800 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=269357056 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=true pio_addr=268439552 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268488704 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=36 int_num1=36 pio_addr=268505088 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=37 int_num1=37 pio_addr=268509184 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[3] [system.realview.uart] type=Pl011 +clock=1 end_on_eot=false gic=system.realview.gic int_delay=100000 int_num=44 pio_addr=268472320 -pio_latency=1000 +pio_latency=100000 platform=system.realview system=system terminal=system.terminal @@ -1005,36 +1033,40 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268476416 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268480512 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268484608 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268500992 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[15] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 8990e0cd7..3e85e4166 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -4,8 +4,40 @@ warn: Sockets disabled, not accepting gdb connections warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. -panic: Not supported on checker! - @ cycle 197694500 -[getInstPort:build/ARM/cpu/checker/cpu.hh, line 130] -Memory Usage: 355632 KBytes -Program aborted at cycle 197694500 +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: 6471379000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 6479236500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 6488789500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 6527432500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6543641500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 7089434000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 12809896500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 12854316500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 13169361500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 14424922500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 14474529500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 15519752500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: 15669382500: Instruction results do not match! (Values may not actually be integers) Inst: 0xc02dd14c, checker: 0xc781befc +warn: LCD dual screen mode not supported +warn: 54391557500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors +warn: 816692532000: Instruction results do not match! (Values may not actually be integers) Inst: 0, checker: 0x1 +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +warn: 2486377425500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2500398254500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2501706856500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2523057678500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2523647855500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2529994034500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2530576345500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2531219324500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2531220454500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 8772dfecb..5011d2336 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:40:00 -gem5 started Jul 27 2012 02:25:32 -gem5 executing on zizzer +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:35:22 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 2537929870500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index e2d527772..30432f4d1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538087 # Number of seconds simulated -sim_ticks 2538087368500 # Number of ticks simulated -final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.537930 # Number of seconds simulated +sim_ticks 2537929870500 # Number of ticks simulated +final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 75387 # Simulator instruction rate (inst/s) -host_op_rate 96971 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3156986836 # Simulator tick rate (ticks/s) -host_mem_usage 390016 # Number of bytes of host memory used -host_seconds 803.96 # Real time elapsed on the host -sim_insts 60608307 # Number of instructions simulated -sim_ops 77960925 # Number of ops (including micro ops) simulated +host_inst_rate 52642 # Simulator instruction rate (inst/s) +host_op_rate 67714 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2204296601 # Simulator tick rate (ticks/s) +host_mem_usage 387316 # Number of bytes of host memory used +host_seconds 1151.36 # Real time elapsed on the host +sim_insts 60609996 # Number of instructions simulated +sim_ops 77962726 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory +system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,153 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64372 # number of replacements -system.l2c.tagsinuse 51362.522219 # Cycle average of tags in use -system.l2c.total_refs 1967256 # Total number of references to valid blocks. -system.l2c.sampled_refs 129768 # Sample count of references to valid blocks. -system.l2c.avg_refs 15.159793 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2527077414000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36916.413821 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 48.977748 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.000243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 8176.092256 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6221.038150 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563300 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.dtb.walker 0.000747 # Average percentage of cache occupancy +system.l2c.replacements 64349 # number of replacements +system.l2c.tagsinuse 51364.190937 # Cycle average of tags in use +system.l2c.total_refs 1931844 # Total number of references to valid blocks. +system.l2c.sampled_refs 129748 # Sample count of references to valid blocks. +system.l2c.avg_refs 14.889201 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2501176617000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36900.070707 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 52.346118 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.000306 # Average occupied blocks per requestor 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number of ReadReq hits -system.l2c.Writeback_hits::writebacks 608347 # number of Writeback hits -system.l2c.Writeback_hits::total 608347 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 42 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 112891 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 112891 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 123430 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 11706 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 978266 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 500583 # number of demand (read+write) hits -system.l2c.demand_hits::total 1613985 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 123430 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 11706 # number of overall hits -system.l2c.overall_hits::cpu.inst 978266 # number of overall hits -system.l2c.overall_hits::cpu.data 500583 # number of overall hits -system.l2c.overall_hits::total 1613985 # number of overall hits -system.l2c.ReadReq_misses::cpu.dtb.walker 61 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses +system.l2c.occ_percent::cpu.inst 0.124815 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.095091 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.783755 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 84751 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 12176 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 977692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 389039 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1463658 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 609524 # number of Writeback hits +system.l2c.Writeback_hits::total 609524 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 48 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 48 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 113135 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113135 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 84751 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 12176 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 977692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 502174 # number of demand (read+write) hits +system.l2c.demand_hits::total 1576793 # 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(read+write) misses -system.l2c.demand_misses::cpu.data 143884 # number of demand (read+write) misses -system.l2c.demand_misses::total 156312 # number of demand (read+write) misses -system.l2c.overall_misses::cpu.dtb.walker 61 # number of overall misses -system.l2c.overall_misses::cpu.itb.walker 1 # number of overall misses +system.l2c.demand_misses::cpu.data 143849 # number of demand (read+write) misses +system.l2c.demand_misses::total 156282 # number of demand (read+write) misses +system.l2c.overall_misses::cpu.dtb.walker 65 # number of overall misses +system.l2c.overall_misses::cpu.itb.walker 2 # number of overall misses system.l2c.overall_misses::cpu.inst 12366 # number of overall misses -system.l2c.overall_misses::cpu.data 143884 # number of overall misses -system.l2c.overall_misses::total 156312 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu.dtb.walker 3194000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu.itb.walker 60000 # number of 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0.015164 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.985748 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.985748 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.541261 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.541261 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000494 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000085 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.223260 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.088297 # miss rate for demand accesses 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+system.l2c.overall_mshr_uncacheable_latency::total 198840598588 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026627 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.015516 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.983827 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.983827 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.540621 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,9 +336,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 15052368 # DTB read hits -system.cpu.checker.dtb.read_misses 7317 # DTB read misses -system.cpu.checker.dtb.write_hits 11296020 # DTB write hits +system.cpu.checker.dtb.read_hits 15052897 # DTB read hits +system.cpu.checker.dtb.read_misses 7321 # DTB read misses +system.cpu.checker.dtb.write_hits 11296410 # DTB write hits system.cpu.checker.dtb.write_misses 2195 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -345,13 +349,13 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 181 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 15059685 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11298215 # DTB write accesses +system.cpu.checker.dtb.read_accesses 15060218 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11298605 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 26348388 # DTB hits -system.cpu.checker.dtb.misses 9512 # DTB misses -system.cpu.checker.dtb.accesses 26357900 # DTB accesses -system.cpu.checker.itb.inst_hits 61787075 # ITB inst hits +system.cpu.checker.dtb.hits 26349307 # DTB hits +system.cpu.checker.dtb.misses 9516 # DTB misses +system.cpu.checker.dtb.accesses 26358823 # DTB accesses +system.cpu.checker.itb.inst_hits 61788771 # ITB inst hits system.cpu.checker.itb.inst_misses 4471 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -368,36 +372,36 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61791546 # ITB inst accesses -system.cpu.checker.itb.hits 61787075 # DTB hits +system.cpu.checker.itb.inst_accesses 61793242 # ITB inst accesses +system.cpu.checker.itb.hits 61788771 # DTB hits system.cpu.checker.itb.misses 4471 # DTB misses -system.cpu.checker.itb.accesses 61791546 # DTB accesses -system.cpu.checker.numCycles 78251500 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61793242 # DTB accesses +system.cpu.checker.numCycles 78253308 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51778790 # DTB read hits -system.cpu.dtb.read_misses 81353 # DTB read misses -system.cpu.dtb.write_hits 11881898 # DTB write hits -system.cpu.dtb.write_misses 18166 # DTB write misses +system.cpu.dtb.read_hits 51757171 # DTB read hits +system.cpu.dtb.read_misses 78755 # DTB read misses +system.cpu.dtb.write_hits 11824944 # DTB write hits +system.cpu.dtb.write_misses 17612 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 8033 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 7813 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860143 # DTB read accesses -system.cpu.dtb.write_accesses 11900064 # DTB write accesses +system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51835926 # DTB read accesses +system.cpu.dtb.write_accesses 11842556 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63660688 # DTB hits -system.cpu.dtb.misses 99519 # DTB misses -system.cpu.dtb.accesses 63760207 # DTB accesses -system.cpu.itb.inst_hits 13142674 # ITB inst hits -system.cpu.itb.inst_misses 12012 # ITB inst misses +system.cpu.dtb.hits 63582115 # DTB hits +system.cpu.dtb.misses 96367 # DTB misses +system.cpu.dtb.accesses 63678482 # DTB accesses +system.cpu.itb.inst_hits 13115769 # ITB inst hits +system.cpu.itb.inst_misses 12252 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -406,538 +410,538 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 5318 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 5204 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13154686 # ITB inst accesses -system.cpu.itb.hits 13142674 # DTB hits -system.cpu.itb.misses 12012 # DTB misses -system.cpu.itb.accesses 13154686 # DTB accesses -system.cpu.numCycles 487300785 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13128021 # ITB inst accesses +system.cpu.itb.hits 13115769 # DTB hits +system.cpu.itb.misses 12252 # DTB misses +system.cpu.itb.accesses 13128021 # DTB accesses +system.cpu.numCycles 487049956 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits +system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued -system.cpu.iq.rate 0.259577 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued +system.cpu.iq.rate 0.259310 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255111 # number of nop insts executed -system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed -system.cpu.iew.exec_branches 11930392 # Number of branches executed -system.cpu.iew.exec_stores 12393079 # Number of stores executed -system.cpu.iew.exec_rate 0.253002 # Inst execution rate -system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47523827 # num instructions producing a value -system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value +system.cpu.iew.exec_nop 226495 # number of nop insts executed +system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed +system.cpu.iew.exec_branches 11753944 # Number of branches executed +system.cpu.iew.exec_stores 12337385 # Number of stores executed +system.cpu.iew.exec_rate 0.252721 # Inst execution rate +system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47490892 # num instructions producing a value +system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758688 # Number of instructions committed -system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60760377 # Number of instructions committed +system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520186 # Number of memory references committed -system.cpu.commit.loads 15719769 # Number of loads committed -system.cpu.commit.membars 413359 # Number of memory barriers committed -system.cpu.commit.branches 10163898 # Number of branches committed +system.cpu.commit.refs 27521116 # Number of memory references committed +system.cpu.commit.loads 15720306 # Number of loads committed +system.cpu.commit.membars 413361 # Number of memory barriers committed +system.cpu.commit.branches 10025135 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. -system.cpu.commit.function_calls 996262 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69149691 # Number of committed integer instructions. +system.cpu.commit.function_calls 996276 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256700614 # The number of ROB reads -system.cpu.rob.rob_writes 209796185 # The number of ROB writes -system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608307 # Number of Instructions Simulated -system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated -system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558050325 # number of integer regfile reads -system.cpu.int_regfile_writes 90161621 # number of integer regfile writes -system.cpu.fp_regfile_reads 8290 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads -system.cpu.misc_regfile_writes 913390 # number of misc regfile writes -system.cpu.icache.replacements 991554 # number of replacements -system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use -system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits -system.cpu.icache.overall_hits::total 12061582 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses -system.cpu.icache.overall_misses::total 1076715 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked +system.cpu.rob.rob_reads 256258159 # The number of ROB reads +system.cpu.rob.rob_writes 209428063 # The number of ROB writes +system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60609996 # Number of Instructions Simulated +system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated +system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557221655 # number of integer regfile reads +system.cpu.int_regfile_writes 90065137 # number of integer regfile writes +system.cpu.fp_regfile_reads 8220 # number of floating regfile reads +system.cpu.fp_regfile_writes 2852 # number of floating regfile writes +system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads +system.cpu.misc_regfile_writes 913466 # number of misc regfile writes +system.cpu.icache.replacements 990831 # number of replacements +system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use +system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits +system.cpu.icache.overall_hits::total 12036161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses +system.cpu.icache.overall_misses::total 1075440 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits 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miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643955 # number of replacements -system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use 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StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285808 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24926244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24926244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24926244 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24926244 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052182 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052182 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292007 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292007 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046437 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046437 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150825 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150825 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150825 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150825 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19428.423293 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19428.423293 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43236.852036 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43236.852036 # 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cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7440 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits 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ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19441.350363 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43224.019859 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43224.019859 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 34382405 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7145000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7505 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4581.266489 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25070.175439 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608347 # number of writebacks -system.cpu.dcache.writebacks::total 608347 # number of writebacks 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-system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks +system.cpu.dcache.writebacks::total 609524 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -959,16 +963,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 7a79f323f..f00ea7875 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,13 +10,15 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +clock=1 +dtb_filename= early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -37,12 +39,11 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] @@ -63,7 +64,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -134,7 +135,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -168,16 +168,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -196,8 +198,8 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -469,16 +471,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -500,8 +504,8 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -576,7 +580,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -610,16 +613,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -638,8 +643,8 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -911,16 +916,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -942,8 +949,8 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -969,16 +976,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 +hit_latency=50000 is_top_level=false -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50000 size=1024 subblock_size=0 system=system @@ -994,16 +1003,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=92 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=4194304 subblock_size=0 system=system @@ -1028,9 +1039,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -1044,8 +1056,9 @@ pio=system.membus.default [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=true -file= in_addr_map=true latency=30000 latency_var=0 @@ -1065,17 +1078,19 @@ system=system [system.realview.a9scu] type=A9SCU +clock=1 pio_addr=520093696 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268451840 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -1119,16 +1134,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=2 disks=system.cf0 io_shift=1 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=2 pci_dev=7 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.realview system=system config=system.iobus.master[8] @@ -1141,8 +1155,6 @@ amba_id=1315089 clock=41667 gic=system.realview.gic int_num=55 -max_backoff_delay=10000000 -min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 system=system @@ -1153,17 +1165,19 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268632064 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake +clock=1 fake_mem=true pio_addr=1073741824 -pio_latency=1000 +pio_latency=100000 pio_size=536870912 ret_bad_addr=false ret_data16=65535 @@ -1177,6 +1191,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic +clock=1 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -1190,39 +1205,43 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268513280 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268517376 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268521472 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=52 is_mouse=false pio_addr=268460032 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[5] @@ -1230,21 +1249,23 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=53 is_mouse=true pio_addr=268464128 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake +clock=1 fake_mem=false pio_addr=520101888 -pio_latency=1000 +pio_latency=100000 pio_size=4095 ret_bad_addr=false ret_data16=65535 @@ -1263,23 +1284,25 @@ gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268455936 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 @@ -1290,9 +1313,10 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl +clock=1 idreg=0 pio_addr=268435456 -pio_latency=1000 +pio_latency=100000 proc_id0=201326592 proc_id1=201327138 system=system @@ -1301,11 +1325,12 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 +clock=1 gic=system.realview.gic int_delay=100000 int_num=42 pio_addr=268529664 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] @@ -1313,73 +1338,80 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268492800 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=269357056 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=true pio_addr=268439552 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268488704 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=36 int_num1=36 pio_addr=268505088 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=37 int_num1=37 pio_addr=268509184 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[3] [system.realview.uart] type=Pl011 +clock=1 end_on_eot=false gic=system.realview.gic int_delay=100000 int_num=44 pio_addr=268472320 -pio_latency=1000 +pio_latency=100000 platform=system.realview system=system terminal=system.terminal @@ -1388,36 +1420,40 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268476416 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268480512 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268484608 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268500992 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[15] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 523f8a126..04178bb32 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -13,7 +13,6 @@ warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 904402304..4c598b20c 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:40:00 -gem5 started Jul 27 2012 02:25:35 -gem5 executing on zizzer +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:18:35 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2582310281500 because m5_exit instruction encountered +Exiting @ tick 2616878893500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 37534da99..8459be5ac 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,16 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.617165 # Number of seconds simulated -sim_ticks 2617165375500 # Number of ticks simulated -final_tick 2617165375500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.616879 # Number of seconds simulated +sim_ticks 2616878893500 # Number of ticks simulated +final_tick 2616878893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89131 # Simulator instruction rate (inst/s) -host_op_rate 114699 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3698456604 # Simulator tick rate (ticks/s) -host_mem_usage 391036 # Number of bytes of host memory used -host_seconds 707.64 # Real time elapsed on the host -sim_insts 63072219 # Number of instructions simulated -sim_ops 81165616 # Number of ops (including micro ops) simulated +host_inst_rate 63327 # Simulator instruction rate (inst/s) +host_op_rate 81506 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2627232906 # Simulator tick rate (ticks/s) +host_mem_usage 387740 # Number of bytes of host memory used +host_seconds 996.06 # Real time elapsed on the host +sim_insts 63077499 # Number of instructions simulated +sim_ops 81184436 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 397632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4358324 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 424512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5245616 # Number of bytes read from this memory +system.physmem.bytes_read::total 131538596 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 397632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 424512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4254848 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7283984 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6213 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6633 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81989 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15301853 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66482 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823766 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46280525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 73 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 151949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1665466 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 162221 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2004531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50265450 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 151949 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 162221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1625925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1151041 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2783462 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1625925 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46280525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 151949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1671963 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 465 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 162221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3155573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53048913 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -29,310 +84,237 @@ system.realview.nvmem.bw_inst_read::total 171 # I system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 388160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4317812 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 434112 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5305072 # Number of bytes read from this memory -system.physmem.bytes_read::total 131557540 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 388160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 434112 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4272576 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7301712 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6783 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82918 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302149 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66759 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824043 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46275459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 148313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1649805 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 440 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 165871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2027030 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50267186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 148313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 165871 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314184 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1632520 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1150915 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2789931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1632520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46275459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 148313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1656300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 440 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 165871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3177945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53057118 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72943 # number of replacements -system.l2c.tagsinuse 53116.867697 # Cycle average of tags in use -system.l2c.total_refs 1971460 # Total number of references to valid blocks. -system.l2c.sampled_refs 138142 # Sample count of references to valid blocks. -system.l2c.avg_refs 14.271257 # Average number of references to valid blocks. +system.l2c.replacements 72648 # number of replacements +system.l2c.tagsinuse 53148.103120 # Cycle average of tags in use +system.l2c.total_refs 1925510 # Total number of references to valid blocks. +system.l2c.sampled_refs 137845 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.968660 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37786.311031 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.267723 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000236 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4199.901742 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2938.535340 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 12.943065 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.004375 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4043.458423 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4131.445760 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.576573 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000065 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064085 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.044838 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000197 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061698 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.063041 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.810499 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 37150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4929 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 329878 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 130970 # number of ReadReq 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0.241327 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.094138 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.241327 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.094138 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40388.960103 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40423.935251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40727.858238 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.058335 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40026.889669 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40027.883460 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40021.546261 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40011.054422 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40017.066086 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41076.199160 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40760.780552 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40900.455825 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40410.677291 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40410.900474 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40736.731792 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.269702 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.514601 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40031.563774 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.165184 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40101.018676 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40049.055233 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41089.568002 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40731.544467 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40893.132300 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41113.873567 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41013.500037 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40750 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40988.868952 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40735.440094 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40874.097629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -537,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7439931 # DTB read hits -system.cpu0.dtb.read_misses 24509 # DTB read misses -system.cpu0.dtb.write_hits 4439969 # DTB write hits -system.cpu0.dtb.write_misses 3332 # DTB write misses +system.cpu0.dtb.read_hits 9084291 # DTB read hits +system.cpu0.dtb.read_misses 36586 # DTB read misses +system.cpu0.dtb.write_hits 5291622 # DTB write hits +system.cpu0.dtb.write_misses 6420 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2072 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1349 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2157 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7464440 # DTB read accesses -system.cpu0.dtb.write_accesses 4443301 # DTB write accesses +system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9120877 # DTB read accesses +system.cpu0.dtb.write_accesses 5298042 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 11879900 # DTB hits -system.cpu0.dtb.misses 27841 # DTB misses -system.cpu0.dtb.accesses 11907741 # DTB accesses -system.cpu0.itb.inst_hits 3552097 # ITB inst hits -system.cpu0.itb.inst_misses 3937 # ITB inst misses +system.cpu0.dtb.hits 14375913 # DTB hits +system.cpu0.dtb.misses 43006 # DTB misses +system.cpu0.dtb.accesses 14418919 # DTB accesses +system.cpu0.itb.inst_hits 4432740 # ITB inst hits +system.cpu0.itb.inst_misses 5766 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -566,538 +536,542 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1380 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1406 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 929 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1571 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 3556034 # ITB inst accesses -system.cpu0.itb.hits 3552097 # DTB hits -system.cpu0.itb.misses 3937 # DTB misses -system.cpu0.itb.accesses 3556034 # DTB accesses -system.cpu0.numCycles 63548405 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4438506 # ITB inst accesses +system.cpu0.itb.hits 4432740 # DTB hits +system.cpu0.itb.misses 5766 # DTB misses +system.cpu0.itb.accesses 4438506 # DTB accesses +system.cpu0.numCycles 73427885 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 5090505 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 3902323 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 231356 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3310708 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2517095 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6227156 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4741082 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 330435 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3793257 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3054809 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 576022 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 23707 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 10651881 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 26843573 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5090505 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3093117 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 6356133 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1209317 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 66372 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20477375 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5743 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 36616 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 72183 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 198 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 3550824 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 136175 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2156 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 38533087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.905766 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.281431 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 703344 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 32160 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12941361 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 33277959 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6227156 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3758153 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7819599 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1599392 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 82441 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 23494459 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 62047 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 92342 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 197 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4430967 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 174323 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2958 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 45648361 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.940627 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.320252 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 32183362 83.52% 83.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 497864 1.29% 84.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 649099 1.68% 86.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 569855 1.48% 87.98% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 713173 1.85% 89.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 461238 1.20% 91.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 562037 1.46% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 306432 0.80% 93.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2590027 6.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 37836918 82.89% 82.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 627349 1.37% 84.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 824369 1.81% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 703980 1.54% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 786046 1.72% 89.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 579188 1.27% 90.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 721067 1.58% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 372009 0.81% 93.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3197435 7.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 38533087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.080104 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.422411 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 11016691 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20495843 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 5693231 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512184 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 815138 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 784502 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 52422 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 33794983 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 170156 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 815138 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 11512212 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6110309 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12456624 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 5662288 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1976516 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 32836773 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1958 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 434728 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1081609 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 147 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 32827027 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 148293172 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 148253410 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 39762 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 25938752 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 6888275 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 379434 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 344458 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4684493 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 6313022 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 4948082 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 931233 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 932024 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 31038582 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 848484 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 31613010 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 68951 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5311616 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10469723 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 281141 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 38533087 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.820412 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.447904 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 45648361 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.084806 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.453206 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 13430389 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 23511343 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 7018661 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 602696 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1085272 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 979924 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65913 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 41505511 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 215463 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1085272 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 14040409 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6748642 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 14460031 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6960379 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2353628 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 40289777 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2418 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 473813 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1332712 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 81 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40678861 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 182059364 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 182024641 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34723 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31700311 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8978549 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 462421 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 418498 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5663645 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7939186 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5895346 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1154000 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1239736 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 38066358 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 944329 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 38270432 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 91181 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6810597 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14485199 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 255192 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 45648361 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.838375 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.464052 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 25332313 65.74% 65.74% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5318332 13.80% 79.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2653261 6.89% 86.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2120070 5.50% 91.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1758280 4.56% 96.49% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 743996 1.93% 98.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 416585 1.08% 99.51% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 146664 0.38% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 43586 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 29755811 65.18% 65.18% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6343756 13.90% 79.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3236490 7.09% 86.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2520305 5.52% 91.69% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2106581 4.61% 96.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 935116 2.05% 98.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 513948 1.13% 99.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 183643 0.40% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 52711 0.12% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 38533087 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 45648361 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 17185 1.90% 1.90% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.05% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 1.95% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 711308 78.54% 80.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 176706 19.51% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27042 2.53% 2.53% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 464 0.04% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.57% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 835512 78.03% 80.60% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207702 19.40% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 39793 0.13% 0.13% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 18975009 60.02% 60.15% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 42063 0.13% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 2 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 627 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.28% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 7818427 24.73% 85.02% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 4737084 14.98% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22977707 60.04% 60.18% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 50299 0.13% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9565645 24.99% 85.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5623724 14.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 31613010 # Type of FU issued -system.cpu0.iq.rate 0.497463 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 905651 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028648 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 102751361 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 37203152 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 29110459 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 9929 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 5392 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 4352 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 32473546 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 5322 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 253493 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 38270432 # Type of FU issued +system.cpu0.iq.rate 0.521198 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070720 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.027978 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 123385364 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45829388 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35329971 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8465 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4764 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3918 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 39284390 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 323676 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1084760 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3550 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 10332 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 476904 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1511954 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3775 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13508 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 616210 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1893731 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4858 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149507 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5450 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 815138 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4299477 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 104449 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 31945570 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 72737 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 6313022 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 4948082 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 576088 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 33936 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17434 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 10332 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 115531 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 108245 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 223776 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 31278568 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 7699224 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 334442 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1085272 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4652854 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 126877 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 39130245 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 91852 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7939186 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5895346 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 610877 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 49621 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 17387 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13508 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 175421 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 130280 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 305701 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37846246 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9402583 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 424186 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 58504 # number of nop insts executed -system.cpu0.iew.exec_refs 12394115 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4158454 # Number of branches executed -system.cpu0.iew.exec_stores 4694891 # Number of stores executed -system.cpu0.iew.exec_rate 0.492201 # Inst execution rate -system.cpu0.iew.wb_sent 31120630 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 29114811 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 15418480 # num instructions producing a value -system.cpu0.iew.wb_consumers 29202336 # num instructions consuming a value +system.cpu0.iew.exec_nop 119558 # number of nop insts executed +system.cpu0.iew.exec_refs 14967440 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4996145 # Number of branches executed +system.cpu0.iew.exec_stores 5564857 # Number of stores executed +system.cpu0.iew.exec_rate 0.515421 # Inst execution rate +system.cpu0.iew.wb_sent 37628600 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35333889 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18696932 # num instructions producing a value +system.cpu0.iew.wb_consumers 35648829 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.458152 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.527988 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.481205 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.524475 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5043051 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 567343 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 195875 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 37746791 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.699150 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.656907 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6705821 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 689137 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 265687 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 44599494 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.717911 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.673991 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 27673007 73.31% 73.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5099673 13.51% 86.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1632700 4.33% 91.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 816219 2.16% 93.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 659263 1.75% 95.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 376754 1.00% 96.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 343613 0.91% 96.97% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 170043 0.45% 97.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 975519 2.58% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32451965 72.76% 72.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6077972 13.63% 86.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1948934 4.37% 90.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1034999 2.32% 93.08% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 805126 1.81% 94.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 506776 1.14% 96.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 402342 0.90% 96.93% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 201836 0.45% 97.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1169544 2.62% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 37746791 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 19900047 # Number of instructions committed -system.cpu0.commit.committedOps 26390683 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 44599494 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24278814 # Number of instructions committed +system.cpu0.commit.committedOps 32018477 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 9699440 # Number of memory references committed -system.cpu0.commit.loads 5228262 # Number of loads committed -system.cpu0.commit.membars 194354 # Number of memory barriers committed -system.cpu0.commit.branches 3620828 # Number of branches committed -system.cpu0.commit.fp_insts 4336 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 23422561 # Number of committed integer instructions. -system.cpu0.commit.function_calls 422942 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 975519 # number cycles where commit BW limit reached +system.cpu0.commit.refs 11706368 # Number of memory references committed +system.cpu0.commit.loads 6427232 # Number of loads committed +system.cpu0.commit.membars 234590 # Number of memory barriers committed +system.cpu0.commit.branches 4349138 # Number of branches committed +system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 28284672 # Number of committed integer instructions. +system.cpu0.commit.function_calls 500279 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1169544 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 67501483 # The number of ROB reads -system.cpu0.rob.rob_writes 63684069 # The number of ROB writes -system.cpu0.timesIdled 366948 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25015318 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5170100782 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 19875493 # Number of Instructions Simulated -system.cpu0.committedOps 26366129 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 19875493 # Number of Instructions Simulated -system.cpu0.cpi 3.197325 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.197325 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.312761 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.312761 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 145756307 # number of integer regfile reads -system.cpu0.int_regfile_writes 28747856 # number of integer regfile writes -system.cpu0.fp_regfile_reads 4243 # number of floating regfile reads -system.cpu0.fp_regfile_writes 404 # number of floating regfile writes -system.cpu0.misc_regfile_reads 38262536 # number of misc regfile reads -system.cpu0.misc_regfile_writes 444175 # number of misc regfile writes -system.cpu0.icache.replacements 335591 # number of replacements -system.cpu0.icache.tagsinuse 511.578004 # Cycle average of tags in use -system.cpu0.icache.total_refs 3187209 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 336103 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.482834 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7275076000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.578004 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999176 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999176 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3187209 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3187209 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3187209 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3187209 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3187209 # number of overall hits -system.cpu0.icache.overall_hits::total 3187209 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 363477 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 363477 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 363477 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 363477 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 363477 # number of overall misses -system.cpu0.icache.overall_misses::total 363477 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5925752494 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5925752494 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5925752494 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5925752494 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5925752494 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5925752494 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 3550686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 3550686 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 3550686 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 3550686 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 3550686 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 3550686 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.102368 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.102368 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.102368 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.102368 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.102368 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.102368 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16302.964133 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16302.964133 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16302.964133 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16302.964133 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16302.964133 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1276494 # number of cycles access was blocked +system.cpu0.rob.rob_reads 81269635 # The number of ROB reads +system.cpu0.rob.rob_writes 78536158 # The number of ROB writes +system.cpu0.timesIdled 427323 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 27779524 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5160286096 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24198072 # Number of Instructions Simulated +system.cpu0.committedOps 31937735 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24198072 # Number of Instructions Simulated +system.cpu0.cpi 3.034452 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 3.034452 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.329549 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.329549 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 176614966 # number of integer regfile reads +system.cpu0.int_regfile_writes 35097459 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3370 # number of floating regfile reads +system.cpu0.fp_regfile_writes 922 # number of floating regfile writes +system.cpu0.misc_regfile_reads 47564974 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527822 # number of misc regfile writes +system.cpu0.icache.replacements 405114 # number of replacements +system.cpu0.icache.tagsinuse 511.561657 # Cycle average of tags in use +system.cpu0.icache.total_refs 3991755 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 405626 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.840974 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 7272099000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.561657 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3991755 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3991755 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3991755 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3991755 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3991755 # number of overall hits +system.cpu0.icache.overall_hits::total 3991755 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 439070 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 439070 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 439070 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 439070 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 439070 # number of overall misses +system.cpu0.icache.overall_misses::total 439070 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7078203996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7078203996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7078203996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7078203996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7078203996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7078203996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4430825 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4430825 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4430825 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4430825 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4430825 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4430825 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099094 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.099094 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099094 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.099094 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099094 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.099094 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16120.900986 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 16120.900986 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 16120.900986 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 16120.900986 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1491997 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 156 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8182.653846 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 8776.452941 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 27366 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 27366 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 27366 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 27366 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 27366 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 27366 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 336111 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 336111 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 336111 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 336111 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 336111 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 336111 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4556806494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4556806494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4556806494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4556806494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4556806494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4556806494 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8394000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8394000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8394000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8394000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.094661 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.094661 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.094661 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.094661 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13557.445290 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13557.445290 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13557.445290 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33429 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 33429 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 33429 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 33429 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 33429 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 33429 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405641 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 405641 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 405641 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 405641 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 405641 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 405641 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5425368997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5425368997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5425368997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5425368997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5425368997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5425368997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8328000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8328000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8328000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8328000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091550 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.091550 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.091550 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13374.804315 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 225959 # number of replacements -system.cpu0.dcache.tagsinuse 476.340528 # Cycle average of tags in use -system.cpu0.dcache.total_refs 7674381 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 226327 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.908376 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 51455000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.340528 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.930353 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.930353 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 4719087 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 4719087 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 2610456 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 2610456 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 155489 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 155489 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 152427 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 152427 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7329543 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 7329543 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7329543 # number of overall hits -system.cpu0.dcache.overall_hits::total 7329543 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 331165 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 331165 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1441313 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1441313 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8607 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8607 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7989 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7989 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1772478 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1772478 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1772478 # number of overall misses -system.cpu0.dcache.overall_misses::total 1772478 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6024148000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6024148000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 68192376390 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 68192376390 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 105659500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 105659500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 91795500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 91795500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 74216524390 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 74216524390 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 74216524390 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 74216524390 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5050252 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5050252 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4051769 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4051769 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 164096 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 164096 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160416 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 160416 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9102021 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9102021 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9102021 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9102021 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.065574 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.065574 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.355724 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.355724 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.052451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.052451 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.049802 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.049802 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.194735 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.194735 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.194735 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.194735 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18190.774991 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18190.774991 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 47312.676976 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 47312.676976 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12275.996282 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12275.996282 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11490.236575 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11490.236575 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41871.619501 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41871.619501 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41871.619501 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 5649995 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1774500 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1210 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 93 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4669.417355 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 19080.645161 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275935 # number of replacements +system.cpu0.dcache.tagsinuse 476.765535 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9559328 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276447 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.579243 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 51426000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 476.765535 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.931183 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.931183 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5939119 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5939119 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3227738 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3227738 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174834 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174834 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171593 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171593 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9166857 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9166857 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9166857 # number of overall hits +system.cpu0.dcache.overall_hits::total 9166857 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 401304 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 401304 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1595717 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1595717 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8980 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8980 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7781 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7781 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1997021 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1997021 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1997021 # number of overall misses +system.cpu0.dcache.overall_misses::total 1997021 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7282608500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 7282608500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71716653343 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 71716653343 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113510500 # number of LoadLockedReq miss cycles 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+system.cpu0.dcache.ReadReq_miss_rate::total 0.063293 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330824 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.330824 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048854 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048854 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043379 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043379 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178882 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.178882 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178882 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.178882 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18147.360854 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 18147.360854 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44943.215710 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44943.215710 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12640.367483 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12640.367483 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11562.267061 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11562.267061 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39558.553387 # average overall miss latency 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-system.cpu0.dcache.writebacks::writebacks 209818 # number of writebacks -system.cpu0.dcache.writebacks::total 209818 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 177491 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 177491 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1323875 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1323875 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 700 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1501366 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1501366 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1501366 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1501366 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 153674 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 153674 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 117438 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 117438 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 7907 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 7907 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7979 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7979 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 271112 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 271112 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 271112 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 271112 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2311816775 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2311816775 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4408331005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4408331005 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 70347504 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 70347504 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 66656537 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66656537 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6720147780 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6720147780 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6720147780 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6720147780 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 12100601500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 12100601500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1292553399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1292553399 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 13393154899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 13393154899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030429 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030429 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.028984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028984 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048185 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.048185 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.049739 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.049739 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029786 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029786 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029786 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15043.642874 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15043.642874 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37537.517711 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37537.517711 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8896.864045 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8896.864045 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8353.996365 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8353.996365 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24787.349066 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24787.349066 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256111 # number of writebacks +system.cpu0.dcache.writebacks::total 256111 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211639 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 211639 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1464558 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1464558 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 529 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 529 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1676197 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1676197 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1676197 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1676197 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189665 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189665 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131159 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131159 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7774 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7774 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 320824 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 320824 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 320824 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 320824 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2812273446 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2812273446 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4676498504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4676498504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79208005 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79208005 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65545528 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65545528 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7488771950 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7488771950 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7488771950 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7488771950 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13454662000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13454662000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1295219899 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1295219899 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14749881899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14749881899 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029914 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029914 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027192 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027192 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043340 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043340 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028738 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028738 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14827.582559 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14827.582559 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35655.185721 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35655.185721 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9372.619217 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9372.619217 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8431.377412 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8431.377412 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1107,27 +1081,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 45088968 # DTB read hits -system.cpu1.dtb.read_misses 60619 # DTB read misses -system.cpu1.dtb.write_hits 7938217 # DTB write hits -system.cpu1.dtb.write_misses 15813 # DTB write misses +system.cpu1.dtb.read_hits 43437526 # DTB read hits +system.cpu1.dtb.read_misses 44897 # DTB read misses +system.cpu1.dtb.write_hits 7020721 # DTB write hits +system.cpu1.dtb.write_misses 11707 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2729 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3748 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 541 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2363 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 4220 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 316 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 727 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 45149587 # DTB read accesses -system.cpu1.dtb.write_accesses 7954030 # DTB write accesses +system.cpu1.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43482423 # DTB read accesses +system.cpu1.dtb.write_accesses 7032428 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 53027185 # DTB hits -system.cpu1.dtb.misses 76432 # DTB misses -system.cpu1.dtb.accesses 53103617 # DTB accesses -system.cpu1.itb.inst_hits 10093689 # ITB inst hits -system.cpu1.itb.inst_misses 8052 # ITB inst misses +system.cpu1.dtb.hits 50458247 # DTB hits +system.cpu1.dtb.misses 56604 # DTB misses +system.cpu1.dtb.accesses 50514851 # DTB accesses +system.cpu1.itb.inst_hits 9182577 # ITB inst hits +system.cpu1.itb.inst_misses 6227 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1136,542 +1110,538 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1586 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2426 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1649 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10101741 # ITB inst accesses -system.cpu1.itb.hits 10093689 # DTB hits -system.cpu1.itb.misses 8052 # DTB misses -system.cpu1.itb.accesses 10101741 # DTB accesses -system.cpu1.numCycles 430376404 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9188804 # ITB inst accesses +system.cpu1.itb.hits 9182577 # DTB hits +system.cpu1.itb.misses 6227 # DTB misses +system.cpu1.itb.accesses 9188804 # DTB accesses +system.cpu1.numCycles 420121858 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 11102078 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 9036479 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 529963 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 7542756 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 6181694 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9688118 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7965440 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 469703 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6737081 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5659691 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 958293 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 57467 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 24500240 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 78456444 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 11102078 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 7139987 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 16800094 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 5031478 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 107954 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 84138717 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5959 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 105572 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 161210 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 156 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 10091008 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 896138 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 4286 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 129269647 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.735584 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.091589 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 834304 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 51249 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 22081738 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 71759711 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9688118 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6493995 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 15294978 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4586075 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 88967 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 80951772 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5897 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 52783 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 142728 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 9180482 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 856181 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3761 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 121742103 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.711584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.060066 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 112479856 87.01% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 952035 0.74% 87.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1186228 0.92% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2188812 1.69% 90.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1732150 1.34% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 728800 0.56% 92.26% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2428875 1.88% 94.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 531185 0.41% 94.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 7041706 5.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 106455334 87.44% 87.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 840434 0.69% 88.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1014558 0.83% 88.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2075766 1.71% 90.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1622971 1.33% 92.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 608124 0.50% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2270082 1.86% 94.37% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 458736 0.38% 94.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6396098 5.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 129269647 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.025796 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.182297 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 26260600 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 83914684 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15106265 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 652780 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3335318 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1450901 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 116510 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 88966869 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 389379 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3335318 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 27931781 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34696050 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 44327698 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 14003132 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4975668 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 82212740 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 21319 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 759400 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3532141 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33925 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 86942184 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 378153831 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 378105448 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 48383 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 55944710 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 30997473 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 570448 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 494970 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 9410070 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15640035 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 9547074 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1284923 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1813164 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 74425843 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1310750 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 98630822 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 132915 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 20366425 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 57377380 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 269048 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 129269647 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.762985 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.495609 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 121742103 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.023060 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.170807 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 23726811 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 80682083 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13746238 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 564864 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 3022107 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1180909 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 102849 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 80937245 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 340282 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 3022107 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 25270664 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33976360 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 42200569 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12677087 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4595316 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 74576204 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 20275 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 711120 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3286160 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33636 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 79110058 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 343673709 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 343614714 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58995 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50196787 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28913271 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 480316 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 419400 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8402630 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 14031046 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8540774 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1078770 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1484758 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 67259946 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1207834 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 91753969 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 112690 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18841154 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 53684147 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 287920 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 121742103 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.753675 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.492082 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 94766617 73.31% 73.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10139907 7.84% 81.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 5158815 3.99% 85.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4427747 3.43% 88.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 11055431 8.55% 97.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2157635 1.67% 98.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1155512 0.89% 99.68% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 316791 0.25% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 91192 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 89993106 73.92% 73.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 9114072 7.49% 81.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4553910 3.74% 85.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4000568 3.29% 88.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10707495 8.80% 97.23% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1970764 1.62% 98.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1044074 0.86% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 282783 0.23% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75331 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 129269647 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 121742103 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 39597 0.49% 0.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1008 0.01% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7696421 95.46% 95.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 325487 4.04% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 28572 0.36% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 997 0.01% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7569076 95.94% 96.31% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 290938 3.69% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 326092 0.33% 0.33% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 43501050 44.10% 44.44% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 69634 0.07% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 16 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 6 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1718 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 44.51% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 46384595 47.03% 91.54% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 8347697 8.46% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313802 0.34% 0.34% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 39340328 42.88% 43.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61412 0.07% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.28% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1696 0.00% 43.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44630775 48.64% 91.93% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7405942 8.07% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 98630822 # Type of FU issued -system.cpu1.iq.rate 0.229173 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 8062513 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.081744 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 334791339 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 96121166 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 62008917 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11647 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6672 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5500 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 106361230 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6013 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 441985 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 91753969 # Type of FU issued +system.cpu1.iq.rate 0.218398 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7889583 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.085986 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 313294010 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 87318397 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 55594578 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14739 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6796 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 99322053 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7697 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 360033 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4452276 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 7115 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 25628 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1723414 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 4037305 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4422 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 18147 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1519259 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 32221586 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1050708 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31965400 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1049364 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3335318 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26012639 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 434151 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 75941872 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 151121 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15640035 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 9547074 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 940187 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 96009 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 15502 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 25628 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 268769 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 233332 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 502101 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 95691641 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 45532774 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2939181 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 3022107 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25590166 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 410250 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 68573370 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132853 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 14031046 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8540774 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 897358 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 85617 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 14991 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 18147 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 245880 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 172266 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 418146 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 88914677 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43821187 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2839292 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 205279 # number of nop insts executed -system.cpu1.iew.exec_refs 53793996 # number of memory reference insts executed -system.cpu1.iew.exec_branches 8312135 # Number of branches executed -system.cpu1.iew.exec_stores 8261222 # Number of stores executed -system.cpu1.iew.exec_rate 0.222344 # Inst execution rate -system.cpu1.iew.wb_sent 94462198 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 62014417 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 34071785 # num instructions producing a value -system.cpu1.iew.wb_consumers 60996509 # num instructions consuming a value +system.cpu1.iew.exec_nop 105590 # number of nop insts executed +system.cpu1.iew.exec_refs 51148287 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7278596 # Number of branches executed +system.cpu1.iew.exec_stores 7327100 # Number of stores executed +system.cpu1.iew.exec_rate 0.211640 # Inst execution rate +system.cpu1.iew.wb_sent 87750200 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 55601374 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30754041 # num instructions producing a value +system.cpu1.iew.wb_consumers 54503523 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.144093 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.558586 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.132346 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.564258 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 20655264 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1041702 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 445913 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 125990352 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.435949 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.396620 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 18816555 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 919914 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 368704 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 118768431 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.415231 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.371949 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 106643597 84.64% 84.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9506424 7.55% 92.19% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2528568 2.01% 94.20% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1530167 1.21% 95.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1425850 1.13% 96.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 711007 0.56% 97.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1063442 0.84% 97.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 518210 0.41% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 2063087 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 101503583 85.46% 85.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8523872 7.18% 92.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2201888 1.85% 94.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1303888 1.10% 95.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1288434 1.08% 96.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 587085 0.49% 97.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 997227 0.84% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 495127 0.42% 98.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1867327 1.57% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 125990352 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 43322553 # Number of instructions committed -system.cpu1.commit.committedOps 54925314 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 118768431 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38949066 # Number of instructions committed +system.cpu1.commit.committedOps 49316340 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 19011419 # Number of memory references committed -system.cpu1.commit.loads 11187759 # Number of loads committed -system.cpu1.commit.membars 242679 # Number of memory barriers committed -system.cpu1.commit.branches 7019269 # Number of branches committed -system.cpu1.commit.fp_insts 5428 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 48550450 # Number of committed integer instructions. -system.cpu1.commit.function_calls 633769 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 2063087 # number cycles where commit BW limit reached +system.cpu1.commit.refs 17015256 # Number of memory references committed +system.cpu1.commit.loads 9993741 # Number of loads committed +system.cpu1.commit.membars 202364 # Number of memory barriers committed +system.cpu1.commit.branches 6138465 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 43706861 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556456 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1867327 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 198211439 # The number of ROB reads -system.cpu1.rob.rob_writes 154591902 # The number of ROB writes -system.cpu1.timesIdled 1579473 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 301106757 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4803892671 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 43196726 # Number of Instructions Simulated -system.cpu1.committedOps 54799487 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 43196726 # Number of Instructions Simulated -system.cpu1.cpi 9.963172 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 9.963172 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.100370 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.100370 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 429674423 # number of integer regfile reads -system.cpu1.int_regfile_writes 64872300 # number of integer regfile writes -system.cpu1.fp_regfile_reads 3964 # number of floating regfile reads -system.cpu1.fp_regfile_writes 1982 # number of floating regfile writes -system.cpu1.misc_regfile_reads 101230364 # number of misc regfile reads -system.cpu1.misc_regfile_writes 513642 # number of misc regfile writes -system.cpu1.icache.replacements 694768 # number of replacements -system.cpu1.icache.tagsinuse 498.623067 # Cycle average of tags in use -system.cpu1.icache.total_refs 9339186 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 695280 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.432266 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 75785789000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.623067 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.973873 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.973873 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 9339186 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9339186 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9339186 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9339186 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9339186 # number of overall hits -system.cpu1.icache.overall_hits::total 9339186 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 751768 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 751768 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 751768 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 751768 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 751768 # number of overall misses -system.cpu1.icache.overall_misses::total 751768 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11830653994 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 11830653994 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 11830653994 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 11830653994 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 11830653994 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 11830653994 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10090954 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10090954 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10090954 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10090954 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10090954 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10090954 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.074499 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.074499 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.074499 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.074499 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.074499 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.074499 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15737.107717 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15737.107717 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15737.107717 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15737.107717 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15737.107717 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1257996 # number of cycles access was blocked +system.cpu1.rob.rob_reads 183919327 # The number of ROB reads +system.cpu1.rob.rob_writes 139377269 # The number of ROB writes +system.cpu1.timesIdled 1519096 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 298379755 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4813097636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38879427 # Number of Instructions Simulated +system.cpu1.committedOps 49246701 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38879427 # Number of Instructions Simulated +system.cpu1.cpi 10.805763 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.805763 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092543 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092543 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 397952991 # number of integer regfile reads +system.cpu1.int_regfile_writes 58412580 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4851 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2298 # number of floating regfile writes +system.cpu1.misc_regfile_reads 91535746 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429838 # number of misc regfile writes +system.cpu1.icache.replacements 621848 # number of replacements +system.cpu1.icache.tagsinuse 498.728003 # Cycle average of tags in use +system.cpu1.icache.total_refs 8507924 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 622360 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.670422 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 75775782000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.728003 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974078 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974078 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8507924 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8507924 # number of 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overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15754.788797 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1171995 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 215 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 180 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 5851.144186 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 6511.083333 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed 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average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13013.148824 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13013.148824 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50115 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 50115 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 50115 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 50115 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 50115 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 50115 # number of overall MSHR hits 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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 413009 # number of replacements -system.cpu1.dcache.tagsinuse 487.394187 # Cycle average of tags in use -system.cpu1.dcache.total_refs 14990250 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 413521 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 36.250275 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 71474582000 # Cycle when the warmup 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19470.778726 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39937.824582 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39937.824582 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11925.787615 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11925.787615 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8777.926886 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8777.926886 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 35531.548109 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35531.548109 # average overall miss latency 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of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95119500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 95119500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 74372850729 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 74372850729 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 74372850729 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 74372850729 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9022033 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9022033 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5851260 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5851260 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119382 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 119382 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 111685 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14873293 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14873293 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14873293 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14873293 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045833 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045833 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273041 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273041 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119733 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119733 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097730 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097730 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135218 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135218 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135218 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135218 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19855.530512 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19855.530512 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41412.782733 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 41412.782733 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11672.799776 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11672.799776 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8714.567109 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8714.567109 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 36980.444290 # average overall miss latency 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-system.cpu1.dcache.writebacks::total 373664 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 211355 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 211355 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1568704 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1568704 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1302 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1302 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1780059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1780059 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1780059 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1780059 # number of overall MSHR hits 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443932 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 443932 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 4040609191 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 4040609191 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5818534579 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5818534579 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 114031007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 114031007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61142007 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61142007 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9859143770 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9859143770 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9859143770 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9859143770 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 170666816500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 170666816500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40957900116 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40957900116 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 211624716616 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 211624716616 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025954 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025954 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.026669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.026669 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.097337 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.097337 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.082653 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.082653 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026234 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026234 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026234 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15108.469904 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15108.469904 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32967.695867 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32967.695867 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8493.297110 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8493.297110 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5661.296944 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5661.296944 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22208.680091 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22208.680091 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 328923 # number of writebacks +system.cpu1.dcache.writebacks::total 328923 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180962 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 180962 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1434656 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1434656 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1453 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1615618 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1615618 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1615618 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1615618 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 232544 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 232544 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162978 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 162978 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12841 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12841 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 395522 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 395522 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 395522 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 395522 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3583215887 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3583215887 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5542320073 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5542320073 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104521007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104521007 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61064509 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61064509 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9125535960 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9125535960 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9125535960 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9125535960 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169307109000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169307109000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40930247169 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40930247169 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210237356169 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210237356169 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025775 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025775 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107562 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107562 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097677 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097677 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026593 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026593 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15408.765167 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15408.765167 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34006.553480 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34006.553480 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8139.631415 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8139.631415 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5597.626639 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5597.626639 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1693,18 +1663,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323290279244 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323290279244 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323290279244 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1322950372611 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1322950372611 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 36101 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43807 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 61677 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53930 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 9e6ff3218..e428e398a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -10,13 +10,15 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +clock=1 +dtb_filename= early_kernel_symbols=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -37,12 +39,11 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge +clock=1 delay=50000 -nack_delay=4000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 -write_ack=false master=system.iobus.slave[0] slave=system.membus.master[0] @@ -63,7 +64,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu] @@ -134,7 +135,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -168,16 +168,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -196,8 +198,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -469,16 +471,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=32768 subblock_size=0 system=system @@ -500,8 +504,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -527,16 +531,18 @@ type=BaseCache addr_ranges=0:268435455 assoc=8 block_size=64 +clock=1 forward_snoops=false hash_delay=1 +hit_latency=50000 is_top_level=false -latency=50000 max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=50000 size=1024 subblock_size=0 system=system @@ -552,16 +558,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=92 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=4194304 subblock_size=0 system=system @@ -586,9 +594,10 @@ slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] type=IsaFake +clock=1 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -602,8 +611,9 @@ pio=system.membus.default [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=true -file= in_addr_map=true latency=30000 latency_var=0 @@ -623,17 +633,19 @@ system=system [system.realview.a9scu] type=A9SCU +clock=1 pio_addr=520093696 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268451840 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[21] @@ -677,16 +689,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1 config_latency=20000 ctrl_offset=2 disks=system.cf0 io_shift=1 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=2 pci_dev=7 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=system.realview system=system config=system.iobus.master[8] @@ -699,8 +710,6 @@ amba_id=1315089 clock=41667 gic=system.realview.gic int_num=55 -max_backoff_delay=10000000 -min_backoff_delay=4000 pio_addr=268566528 pio_latency=10000 system=system @@ -711,17 +720,19 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268632064 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake +clock=1 fake_mem=true pio_addr=1073741824 -pio_latency=1000 +pio_latency=100000 pio_size=536870912 ret_bad_addr=false ret_data16=65535 @@ -735,6 +746,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic +clock=1 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -748,39 +760,43 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268513280 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268517376 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268521472 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=52 is_mouse=false pio_addr=268460032 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[5] @@ -788,21 +804,23 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 +clock=1 gic=system.realview.gic int_delay=1000000 int_num=53 is_mouse=true pio_addr=268464128 -pio_latency=1000 +pio_latency=100000 system=system vnc=system.vncserver pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake +clock=1 fake_mem=false pio_addr=520101888 -pio_latency=1000 +pio_latency=100000 pio_size=4095 ret_bad_addr=false ret_data16=65535 @@ -821,23 +839,25 @@ gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 pio_addr=520095232 -pio_latency=1000 +pio_latency=100000 system=system pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268455936 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 @@ -848,9 +868,10 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl +clock=1 idreg=0 pio_addr=268435456 -pio_latency=1000 +pio_latency=100000 proc_id0=201326592 proc_id1=201327138 system=system @@ -859,11 +880,12 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 +clock=1 gic=system.realview.gic int_delay=100000 int_num=42 pio_addr=268529664 -pio_latency=1000 +pio_latency=100000 system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[23] @@ -871,73 +893,80 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268492800 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=269357056 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=true pio_addr=268439552 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268488704 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=36 int_num1=36 pio_addr=268505088 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 +clock=1 clock0=1000000 clock1=1000000 gic=system.realview.gic int_num0=37 int_num1=37 pio_addr=268509184 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[3] [system.realview.uart] type=Pl011 +clock=1 end_on_eot=false gic=system.realview.gic int_delay=100000 int_num=44 pio_addr=268472320 -pio_latency=1000 +pio_latency=100000 platform=system.realview system=system terminal=system.terminal @@ -946,36 +975,40 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268476416 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268480512 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268484608 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 +clock=1 ignore_access=false pio_addr=268500992 -pio_latency=1000 +pio_latency=100000 system=system pio=system.iobus.master[15] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index ab2c07a7f..affb69ad6 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -13,7 +13,6 @@ warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c9f3d2864..304caa505 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:40:00 -gem5 started Jul 27 2012 02:23:14 -gem5 executing on zizzer +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:10:34 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2503329223500 because m5_exit instruction encountered +Exiting @ tick 2537929870500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 5e48f5c5e..5eb2280fd 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.538087 # Number of seconds simulated -sim_ticks 2538087368500 # Number of ticks simulated -final_tick 2538087368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.537930 # Number of seconds simulated +sim_ticks 2537929870500 # Number of ticks simulated +final_tick 2537929870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 89486 # Simulator instruction rate (inst/s) -host_op_rate 115106 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3747392596 # Simulator tick rate (ticks/s) -host_mem_usage 390008 # Number of bytes of host memory used -host_seconds 677.29 # Real time elapsed on the host -sim_insts 60608307 # Number of instructions simulated -sim_ops 77960925 # Number of ops (including micro ops) simulated +host_inst_rate 62423 # Simulator instruction rate (inst/s) +host_op_rate 80294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2613828720 # Simulator tick rate (ticks/s) +host_mem_usage 387060 # Number of bytes of host memory used +host_seconds 970.96 # Real time elapsed on the host +sim_insts 60609996 # Number of instructions simulated +sim_ops 77962726 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 799104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9092048 # Number of bytes read from this memory -system.physmem.bytes_read::total 131005648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 799104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784192 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 4160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 798976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9090320 # Number of bytes read from this memory +system.physmem.bytes_read::total 131004112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3779648 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800264 # Number of bytes written to this memory +system.physmem.bytes_written::total 6795720 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 61 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12486 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142097 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293461 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59128 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 65 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12484 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142070 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293437 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59057 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813146 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47717242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3582244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51615894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1490962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1188325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2679287 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1490962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47717242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4770569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54295181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813075 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47720203 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3581785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51618492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314814 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489264 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1188398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2677663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47720203 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 314814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4770184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54296154 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -61,149 +61,153 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 64372 # number of replacements -system.l2c.tagsinuse 51362.522219 # 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mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.540621 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.090136 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000766 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000164 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012482 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.222573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.090136 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 44000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 41057.250283 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40475.056370 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40786.813429 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40096.746575 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40096.746575 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40840.036322 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40840.036322 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40098.360656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 48000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41042.964560 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40812.444363 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40830.445755 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40841.095634 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40841.095634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40323.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 41057.250283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40813.999152 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40833.079373 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -332,27 +336,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51778790 # DTB read hits -system.cpu.dtb.read_misses 81353 # DTB read misses -system.cpu.dtb.write_hits 11881898 # DTB write hits -system.cpu.dtb.write_misses 18166 # DTB write misses +system.cpu.dtb.read_hits 51757171 # DTB read hits +system.cpu.dtb.read_misses 78755 # DTB read misses +system.cpu.dtb.write_hits 11824944 # DTB write hits +system.cpu.dtb.write_misses 17612 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4472 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 3264 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 614 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4306 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 3128 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 514 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1261 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51860143 # DTB read accesses -system.cpu.dtb.write_accesses 11900064 # DTB write accesses +system.cpu.dtb.perms_faults 1187 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51835926 # DTB read accesses +system.cpu.dtb.write_accesses 11842556 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63660688 # DTB hits -system.cpu.dtb.misses 99519 # DTB misses -system.cpu.dtb.accesses 63760207 # DTB accesses -system.cpu.itb.inst_hits 13142674 # ITB inst hits -system.cpu.itb.inst_misses 12012 # ITB inst misses +system.cpu.dtb.hits 63582115 # DTB hits +system.cpu.dtb.misses 96367 # DTB misses +system.cpu.dtb.accesses 63678482 # DTB accesses +system.cpu.itb.inst_hits 13115769 # ITB inst hits +system.cpu.itb.inst_misses 12252 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -361,538 +365,538 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2661 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2604 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 3477 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3277 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 13154686 # ITB inst accesses -system.cpu.itb.hits 13142674 # DTB hits -system.cpu.itb.misses 12012 # DTB misses -system.cpu.itb.accesses 13154686 # DTB accesses -system.cpu.numCycles 487300785 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 13128021 # ITB inst accesses +system.cpu.itb.hits 13115769 # DTB hits +system.cpu.itb.misses 12252 # DTB misses +system.cpu.itb.accesses 13128021 # DTB accesses +system.cpu.numCycles 487049956 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 15530766 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12471723 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 754243 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 10651914 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 8369263 # Number of BTB hits +system.cpu.BPredUnit.lookups 15265836 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12253522 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 790029 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 10231069 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 8383104 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1449848 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 80901 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 33379389 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 101786531 # Number of instructions fetch has processed -system.cpu.fetch.Branches 15530766 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9819111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 22320239 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6081203 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 158853 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 102204493 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2684 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133854 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 208007 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 300 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13138430 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1021608 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 6374 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.771886 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.134900 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1454061 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 83540 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 33339940 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 101517104 # Number of instructions fetch has processed +system.cpu.fetch.Branches 15265836 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9837165 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 22278409 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6025504 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 157129 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 102031349 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2877 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 112878 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 209522 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13111736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1022555 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 6694 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.770946 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.133351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 140287148 86.28% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1367954 0.84% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1761574 1.08% 88.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2654240 1.63% 89.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2359914 1.45% 91.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1143060 0.70% 91.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2915951 1.79% 93.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 808451 0.50% 94.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 9292210 5.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 140010343 86.28% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1387058 0.85% 87.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1759256 1.08% 88.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2673832 1.65% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2324399 1.43% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1142133 0.70% 92.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2914571 1.80% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 802946 0.49% 94.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9257450 5.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 162590502 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.031871 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.208878 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35559403 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 101873570 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 20035841 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1111053 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4010635 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2099297 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 175058 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 118316110 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 572190 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4010635 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37673170 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 40477243 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 54791602 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18894911 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6742941 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110777712 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 22948 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1162010 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4487085 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 30869 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 115617141 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 507045226 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 506952458 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 92768 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78747095 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 36870045 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 898908 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 797965 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13562847 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 21065168 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13875966 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1948101 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2609238 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 101350555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2059934 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 126492219 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 199079 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24669987 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 65519424 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 514717 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 162590502 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.777980 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.488111 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 162271988 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.031343 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.208433 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35519413 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 101672639 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 20003488 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1109197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3967251 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2027366 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 175080 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118004769 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 577706 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3967251 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37625250 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40424922 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 54666118 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18858904 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6729543 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110552041 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 22802 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1145502 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4490712 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 31851 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 115544038 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 506134218 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 506042308 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 91910 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78748778 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 36795259 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 893517 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 798182 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13541663 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 21062832 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13840935 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1956455 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2555240 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 101213239 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2059558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 126297159 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 200424 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24661368 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 65776088 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 514288 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 162271988 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.778305 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.488656 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 116448984 71.62% 71.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 14892562 9.16% 80.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7379275 4.54% 85.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6334493 3.90% 89.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12627372 7.77% 96.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2807487 1.73% 98.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1536769 0.95% 99.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 438389 0.27% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 125171 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 116217920 71.62% 71.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14878353 9.17% 80.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7338383 4.52% 85.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6288492 3.88% 89.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12644772 7.79% 96.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2813043 1.73% 98.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1525517 0.94% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 444905 0.27% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 120603 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 162590502 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 162271988 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 53974 0.61% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.61% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371302 94.73% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 411522 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 53198 0.60% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8363826 94.73% 95.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412000 4.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60100206 47.51% 47.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 95387 0.08% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 12 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 53417810 42.23% 90.11% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12512990 9.89% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 59965938 47.48% 47.77% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 95633 0.08% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 14 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 6 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2112 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 53400637 42.28% 90.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12469145 9.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 126492219 # Type of FU issued -system.cpu.iq.rate 0.259577 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8836801 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.069860 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 424687081 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128101552 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87467188 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22890 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12894 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10336 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 134953294 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12060 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 646395 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 126297159 # Type of FU issued +system.cpu.iq.rate 0.259310 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8829028 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.069907 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 423968404 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 127951101 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87290001 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23313 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12742 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10305 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 134750106 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12415 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 633498 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 5345399 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 11042 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 35020 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2075549 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 5342526 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 8187 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30812 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2040125 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107217 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1052457 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107208 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1052465 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4010635 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30068216 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 540743 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 103665600 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 220216 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 21065168 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13875966 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1468298 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 126232 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 40886 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 35020 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 376820 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 332740 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 709560 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 123288257 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 52469499 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3203962 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3967251 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30033054 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 539777 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 103499292 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 223830 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 21062832 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13840935 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1467584 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 130279 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 41269 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30812 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 412836 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 293063 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 705899 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 123087993 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 52445768 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3209166 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 255111 # number of nop insts executed -system.cpu.iew.exec_refs 64862578 # number of memory reference insts executed -system.cpu.iew.exec_branches 11930392 # Number of branches executed -system.cpu.iew.exec_stores 12393079 # Number of stores executed -system.cpu.iew.exec_rate 0.253002 # Inst execution rate -system.cpu.iew.wb_sent 121911839 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87477524 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47523827 # num instructions producing a value -system.cpu.iew.wb_consumers 86459839 # num instructions consuming a value +system.cpu.iew.exec_nop 226495 # number of nop insts executed +system.cpu.iew.exec_refs 64783153 # number of memory reference insts executed +system.cpu.iew.exec_branches 11753944 # Number of branches executed +system.cpu.iew.exec_stores 12337385 # Number of stores executed +system.cpu.iew.exec_rate 0.252721 # Inst execution rate +system.cpu.iew.wb_sent 121723565 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87300306 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47490892 # num instructions producing a value +system.cpu.iew.wb_consumers 86410198 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179514 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.549664 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179243 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.549598 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24732278 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1545217 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 625816 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158662310 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.492312 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.459485 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24569978 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1545270 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 617808 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158387180 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.493178 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.461668 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 130458831 82.22% 82.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13994447 8.82% 91.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3942201 2.48% 93.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2235545 1.41% 94.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2018631 1.27% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1062301 0.67% 96.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1402549 0.88% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 657941 0.41% 98.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2889864 1.82% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 130224510 82.22% 82.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13962931 8.82% 91.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3932666 2.48% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2224869 1.40% 94.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2020992 1.28% 96.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1058227 0.67% 96.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1402359 0.89% 97.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 664028 0.42% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2896598 1.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158662310 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60758688 # Number of instructions committed -system.cpu.commit.committedOps 78111306 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 158387180 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60760377 # Number of instructions committed +system.cpu.commit.committedOps 78113107 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27520186 # Number of memory references committed -system.cpu.commit.loads 15719769 # Number of loads committed -system.cpu.commit.membars 413359 # Number of memory barriers committed -system.cpu.commit.branches 10163898 # Number of branches committed +system.cpu.commit.refs 27521116 # Number of memory references committed +system.cpu.commit.loads 15720306 # Number of loads committed +system.cpu.commit.membars 413361 # Number of memory barriers committed +system.cpu.commit.branches 10025135 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69148075 # Number of committed integer instructions. -system.cpu.commit.function_calls 996262 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2889864 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 69149691 # Number of committed integer instructions. +system.cpu.commit.function_calls 996276 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2896598 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 256700614 # The number of ROB reads -system.cpu.rob.rob_writes 209796185 # The number of ROB writes -system.cpu.timesIdled 1906230 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 324710283 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4588785915 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60608307 # Number of Instructions Simulated -system.cpu.committedOps 77960925 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60608307 # Number of Instructions Simulated -system.cpu.cpi 8.040165 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.040165 # CPI: Total CPI of All Threads -system.cpu.ipc 0.124376 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.124376 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 558050322 # number of integer regfile reads -system.cpu.int_regfile_writes 90161620 # number of integer regfile writes -system.cpu.fp_regfile_reads 8290 # number of floating regfile reads -system.cpu.fp_regfile_writes 2914 # number of floating regfile writes -system.cpu.misc_regfile_reads 134103665 # number of misc regfile reads -system.cpu.misc_regfile_writes 913390 # number of misc regfile writes -system.cpu.icache.replacements 991554 # number of replacements -system.cpu.icache.tagsinuse 511.576119 # Cycle average of tags in use -system.cpu.icache.total_refs 12061582 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 992066 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 12.158044 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 7225354000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.576119 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.999172 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.999172 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12061582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12061582 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12061582 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12061582 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12061582 # number of overall hits -system.cpu.icache.overall_hits::total 12061582 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1076715 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1076715 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1076715 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1076715 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1076715 # number of overall misses -system.cpu.icache.overall_misses::total 1076715 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16664677991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16664677991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16664677991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16664677991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16664677991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13138297 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13138297 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13138297 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13138297 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13138297 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081952 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081952 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081952 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081952 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081952 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15477.334291 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15477.334291 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15477.334291 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15477.334291 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2769993 # number of cycles access was blocked +system.cpu.rob.rob_reads 256258159 # The number of ROB reads +system.cpu.rob.rob_writes 209428063 # The number of ROB writes +system.cpu.timesIdled 1906854 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 324777968 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4588721746 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60609996 # Number of Instructions Simulated +system.cpu.committedOps 77962726 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60609996 # Number of Instructions Simulated +system.cpu.cpi 8.035802 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.035802 # CPI: Total CPI of All Threads +system.cpu.ipc 0.124443 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.124443 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 557221649 # number of integer regfile reads +system.cpu.int_regfile_writes 90065135 # number of integer regfile writes +system.cpu.fp_regfile_reads 8220 # number of floating regfile reads +system.cpu.fp_regfile_writes 2852 # number of floating regfile writes +system.cpu.misc_regfile_reads 133714329 # number of misc regfile reads +system.cpu.misc_regfile_writes 913466 # number of misc regfile writes +system.cpu.icache.replacements 990831 # number of replacements +system.cpu.icache.tagsinuse 511.552497 # Cycle average of tags in use +system.cpu.icache.total_refs 12036161 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 991343 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 12.141268 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 7225774000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.552497 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999126 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999126 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 12036161 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 12036161 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 12036161 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 12036161 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 12036161 # number of overall hits +system.cpu.icache.overall_hits::total 12036161 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1075440 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1075440 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1075440 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1075440 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1075440 # number of overall misses +system.cpu.icache.overall_misses::total 1075440 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16637783989 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16637783989 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16637783989 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16637783989 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16637783989 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13111601 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13111601 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13111601 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13111601 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13111601 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082022 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082022 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082022 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082022 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082022 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15470.676178 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15470.676178 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15470.676178 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15470.676178 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2693492 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 446 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 350 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 6210.746637 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 7695.691429 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84611 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 84611 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 84611 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 84611 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 84611 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 992104 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 992104 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 992104 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 992104 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 992104 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12645073993 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12645073993 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12645073993 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 8007500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 8007500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075512 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.075512 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.075512 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12745.714152 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12745.714152 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12745.714152 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12745.714152 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84051 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84051 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84051 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84051 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84051 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84051 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 991389 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 991389 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 991389 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 991389 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 991389 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 991389 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12620585492 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12620585492 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12620585492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12620585492 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12620585492 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12620585492 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7938500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 7938500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.075612 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.075612 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.075612 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.075612 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12730.205290 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12730.205290 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12730.205290 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12730.205290 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643955 # number of replacements -system.cpu.dcache.tagsinuse 511.991455 # Cycle average of tags in use -system.cpu.dcache.total_refs 21739303 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644467 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.732221 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 50940000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.991455 # Average occupied blocks per requestor +system.cpu.dcache.replacements 645511 # number of replacements +system.cpu.dcache.tagsinuse 511.991460 # Cycle average of tags in use +system.cpu.dcache.total_refs 21729121 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 646023 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.635213 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 50910000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 511.991460 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999983 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999983 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13908098 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13908098 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258651 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258651 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 283641 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 283641 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285792 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285792 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21166749 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21166749 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21166749 # number of overall hits -system.cpu.dcache.overall_hits::total 21166749 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 765710 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 765710 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2993785 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2993785 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13813 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13813 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3759495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3759495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3759495 # number of overall misses -system.cpu.dcache.overall_misses::total 3759495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 14876538000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 14876538000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 129441839072 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 129441839072 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224157500 # 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number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 297454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 297454 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285808 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285808 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24926244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24926244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24926244 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24926244 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052182 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052182 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292007 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292007 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046437 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046437 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.150825 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.150825 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.150825 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.150825 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19428.423293 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19428.423293 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43236.852036 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 43236.852036 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16228.009846 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16228.009846 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22437.500000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 22437.500000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38387.702889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38387.702889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38387.702889 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33577415 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7376000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7440 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 283 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4513.093414 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 26063.604240 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13899785 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13899785 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7254429 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7254429 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 285860 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 285860 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 285827 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 285827 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21154214 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21154214 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21154214 # number of overall hits +system.cpu.dcache.overall_hits::total 21154214 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 767038 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 767038 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2998364 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2998364 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13689 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13689 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3765402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3765402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3765402 # number of overall misses +system.cpu.dcache.overall_misses::total 3765402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14912254500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14912254500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 129601345080 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 129601345080 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 222071000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 222071000 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 314500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 314500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 144513599580 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 144513599580 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 144513599580 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 144513599580 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14666823 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14666823 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10252793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10252793 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 299549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 299549 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 285840 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 285840 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24919616 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24919616 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24919616 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24919616 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052297 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052297 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292444 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292444 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045699 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045699 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000045 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.151102 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.151102 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.151102 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.151102 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19441.350363 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19441.350363 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43224.019859 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43224.019859 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16222.587479 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 24192.307692 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38379.328311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38379.328311 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 34382405 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7145000 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7505 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4581.266489 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25070.175439 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 608347 # number of writebacks -system.cpu.dcache.writebacks::total 608347 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379574 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 379574 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2744878 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2744878 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1442 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3124452 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3124452 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3124452 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3124452 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 386136 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 386136 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248907 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 248907 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 635043 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 635043 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 635043 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6270140101 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9248914453 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 164305000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 305000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15519054554 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15519054554 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182411169000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41923418941 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 224334587941 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026315 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024278 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041590 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025477 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025477 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16238.165053 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37158.113082 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13281.464716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 19062.500000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24437.801147 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24437.801147 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 609524 # number of writebacks +system.cpu.dcache.writebacks::total 609524 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 379381 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 379381 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2749244 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3128625 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3128625 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3128625 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 387657 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 387657 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249120 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 249120 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12214 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 636777 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 636777 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 636777 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6303506404 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9254265450 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 162323500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 271500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15557771854 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15557771854 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182409475000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 41932970674 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 224342445674 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026431 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024298 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.040775 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025553 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16260.525165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37147.822134 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13289.954151 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.615385 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24432.056833 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24432.056833 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -914,16 +918,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1323585371203 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323585371203 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1323585371203 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1323990187654 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1323990187654 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1323990187654 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88038 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 88040 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini index 3e3a921c2..9953e7dde 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,12 +513,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout index 71d01f629..21a8a9bfd 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:22:13 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:54:44 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -38,4 +38,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 164812294500 because target called exit() +Exiting @ tick 164735271500 because target called exit() diff --git a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt index c74978b2c..3e2378b89 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.164804 # Number of seconds simulated -sim_ticks 164803697500 # Number of ticks simulated -final_tick 164803697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.164735 # Number of seconds simulated +sim_ticks 164735271500 # Number of ticks simulated +final_tick 164735271500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 225505 # Simulator instruction rate (inst/s) -host_op_rate 238286 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65194032 # Simulator tick rate (ticks/s) -host_mem_usage 234780 # Number of bytes of host memory used -host_seconds 2527.90 # Real time elapsed on the host -sim_insts 570052730 # Number of instructions simulated -sim_ops 602360936 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1769280 # Number of bytes read from this memory -system.physmem.bytes_read::total 1816896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 202944 # Number of bytes written to this memory -system.physmem.bytes_written::total 202944 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 27645 # Number of read requests responded to by this memory -system.physmem.num_reads::total 28389 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 3171 # Number of write requests responded to by this memory -system.physmem.num_writes::total 3171 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 288926 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 10735681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 11024607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 288926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 288926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1231429 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1231429 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1231429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 288926 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 10735681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 12256036 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 151833 # Simulator instruction rate (inst/s) +host_op_rate 160438 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43876980 # Simulator tick rate (ticks/s) +host_mem_usage 229232 # Number of bytes of host memory used +host_seconds 3754.48 # Real time elapsed on the host +sim_insts 570052715 # Number of instructions simulated +sim_ops 602360921 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1771392 # Number of bytes read from this memory +system.physmem.bytes_read::total 1819904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 204096 # Number of bytes written to this memory +system.physmem.bytes_written::total 204096 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 27678 # Number of read requests responded to by this memory +system.physmem.num_reads::total 28436 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 3189 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3189 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 294485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 10752961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 11047446 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 294485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 294485 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1238933 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1238933 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1238933 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 294485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 10752961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 12286379 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 48 # Number of system calls -system.cpu.numCycles 329607396 # number of cpu cycles simulated +system.cpu.numCycles 329470544 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 85521262 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 80324005 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2361364 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 47163773 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 46836425 # Number of BTB hits +system.cpu.BPredUnit.lookups 85543194 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 80343428 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2410851 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 47247808 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 46879382 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1442496 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 971 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 68931742 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 669855776 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85521262 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48278921 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 130072968 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 13495551 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 119465420 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 1438508 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 957 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 68858387 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 669531966 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85543194 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48317890 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 130053558 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 13436601 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 119467619 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 697 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 67497575 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 806206 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 329517095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166390 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.195660 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 664 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 67410579 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 785974 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 329380053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166154 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.195076 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 199444353 60.53% 60.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 20947099 6.36% 66.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4950101 1.50% 68.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 14318334 4.35% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8976585 2.72% 75.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9434873 2.86% 78.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 4385962 1.33% 79.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 5814434 1.76% 81.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 61245354 18.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 199326735 60.52% 60.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 20925869 6.35% 66.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4976270 1.51% 68.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 14401478 4.37% 72.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8915823 2.71% 75.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9447821 2.87% 78.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 4394131 1.33% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 5797396 1.76% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 61194530 18.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 329517095 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.259464 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.032284 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 93615293 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96153951 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108189677 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 20513543 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 11044631 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4783839 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 1715 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 706162861 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6102 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 11044631 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 107837587 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 14124315 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 49845 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 114419609 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 82041108 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 697343102 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 59702950 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20121716 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 628 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 723953896 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3241969745 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3241969617 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 329380053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.259638 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.032145 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 93515183 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 96161670 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108196547 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 20508331 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10998322 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4720780 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 1591 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 705885224 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5921 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 10998322 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 107743564 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 14112964 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 43222 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 114413091 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 82068890 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 697152675 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 157 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 59727344 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 20123270 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 641 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 723862465 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3241326776 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3241326648 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 128 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 627419205 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 96534691 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 6461 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 6411 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 169960309 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172942863 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 80636505 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 21738448 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28392401 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 682081084 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 4755 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 646873471 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1427255 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 79546312 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 198336630 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1822 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 329517095 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.963095 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.726025 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 627419181 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 96443284 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2057 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2011 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 169978483 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 172921644 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 80622072 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 21488970 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 28010178 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 681988292 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3275 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 646797787 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1412727 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 79459503 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 198007283 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 345 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 329380053 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.963682 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.727918 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 69073062 20.96% 20.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 85428169 25.93% 46.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 76011979 23.07% 69.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 40983157 12.44% 82.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 28619491 8.69% 91.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 15088313 4.58% 95.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5676552 1.72% 97.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6597944 2.00% 99.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2038428 0.62% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 69019799 20.95% 20.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 85512996 25.96% 46.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 75829369 23.02% 69.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 41034711 12.46% 82.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 28570777 8.67% 91.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15062101 4.57% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5699719 1.73% 97.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6474655 1.97% 99.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2175926 0.66% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 329517095 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 329380053 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 205689 5.35% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2625601 68.27% 73.62% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1014507 26.38% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 206481 5.38% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2616685 68.13% 73.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1017800 26.50% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 403948716 62.45% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6566 0.00% 62.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 403890666 62.44% 62.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6567 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.45% # Type of FU issued @@ -239,157 +239,157 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 62.45% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 166134463 25.68% 88.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 76783723 11.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 166105526 25.68% 88.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 76795025 11.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 646873471 # Type of FU issued -system.cpu.iq.rate 1.962558 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3845797 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.005945 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1628537053 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 761643882 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 638542497 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 646797787 # Type of FU issued +system.cpu.iq.rate 1.963143 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3840966 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.005938 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1628229284 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 761462946 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 638497717 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 650719248 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 650638733 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 30433842 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 30397502 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 23990041 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 126515 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11992 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10415263 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 23968825 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 126112 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 12134 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10400833 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 12768 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 35443 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 12732 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 35377 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 11044631 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 670742 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80165 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 682151912 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 669326 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172942863 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 80636505 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3402 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 21938 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3947 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11992 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1313002 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1582154 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2895156 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 642705109 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 164002272 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4168362 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10998322 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 671065 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 80095 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 681994740 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 717531 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 172921644 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 80622072 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1925 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21947 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3973 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 12134 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1389665 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1520287 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2909952 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 642597340 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 163964037 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4200447 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 66073 # number of nop insts executed -system.cpu.iew.exec_refs 239994615 # number of memory reference insts executed -system.cpu.iew.exec_branches 74670654 # Number of branches executed -system.cpu.iew.exec_stores 75992343 # Number of stores executed -system.cpu.iew.exec_rate 1.949911 # Inst execution rate -system.cpu.iew.wb_sent 640039570 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 638542513 # cumulative count of insts written-back -system.cpu.iew.wb_producers 419139421 # num instructions producing a value -system.cpu.iew.wb_consumers 650719166 # num instructions consuming a value +system.cpu.iew.exec_nop 3173 # number of nop insts executed +system.cpu.iew.exec_refs 239958391 # number of memory reference insts executed +system.cpu.iew.exec_branches 74720339 # Number of branches executed +system.cpu.iew.exec_stores 75994354 # Number of stores executed +system.cpu.iew.exec_rate 1.950394 # Inst execution rate +system.cpu.iew.wb_sent 639963641 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 638497733 # cumulative count of insts written-back +system.cpu.iew.wb_producers 419111890 # num instructions producing a value +system.cpu.iew.wb_consumers 650388459 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.937282 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.644117 # average fanout of values written-back +system.cpu.iew.wb_rate 1.937951 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.644402 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 79800581 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 2933 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2421751 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 318472465 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.891407 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.233429 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 79643282 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 2930 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2409350 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 318381732 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.891946 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.233867 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 93877002 29.48% 29.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 104551194 32.83% 62.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43288621 13.59% 75.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8793504 2.76% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 26039044 8.18% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 12759663 4.01% 90.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7570973 2.38% 93.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1268002 0.40% 93.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 20324462 6.38% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 93812247 29.47% 29.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 104551370 32.84% 62.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43266938 13.59% 75.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8778657 2.76% 78.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 26036096 8.18% 86.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 12762730 4.01% 90.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7569326 2.38% 93.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1269179 0.40% 93.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 20335189 6.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 318472465 # Number of insts commited each cycle -system.cpu.commit.committedInsts 570052781 # Number of instructions committed -system.cpu.commit.committedOps 602360987 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 318381732 # Number of insts commited each cycle +system.cpu.commit.committedInsts 570052766 # Number of instructions committed +system.cpu.commit.committedOps 602360972 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 219174064 # Number of memory references committed -system.cpu.commit.loads 148952822 # Number of loads committed +system.cpu.commit.refs 219174058 # Number of memory references committed +system.cpu.commit.loads 148952819 # Number of loads committed system.cpu.commit.membars 1328 # Number of memory barriers committed -system.cpu.commit.branches 70828829 # Number of branches committed +system.cpu.commit.branches 70892750 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 533523547 # Number of committed integer instructions. +system.cpu.commit.int_insts 533523535 # Number of committed integer instructions. system.cpu.commit.function_calls 997573 # Number of function calls committed. -system.cpu.commit.bw_lim_events 20324462 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 20335189 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 980308959 # The number of ROB reads -system.cpu.rob.rob_writes 1375400190 # The number of ROB writes -system.cpu.timesIdled 6717 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 90301 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 570052730 # Number of Instructions Simulated -system.cpu.committedOps 602360936 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 570052730 # Number of Instructions Simulated -system.cpu.cpi 0.578205 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.578205 # CPI: Total CPI of All Threads -system.cpu.ipc 1.729490 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.729490 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3210477235 # number of integer regfile reads -system.cpu.int_regfile_writes 664240650 # number of integer regfile writes +system.cpu.rob.rob_reads 980050185 # The number of ROB reads +system.cpu.rob.rob_writes 1375038514 # The number of ROB writes +system.cpu.timesIdled 6612 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 90491 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 570052715 # Number of Instructions Simulated +system.cpu.committedOps 602360921 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 570052715 # Number of Instructions Simulated +system.cpu.cpi 0.577965 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.577965 # CPI: Total CPI of All Threads +system.cpu.ipc 1.730208 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.730208 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3210034168 # number of integer regfile reads +system.cpu.int_regfile_writes 664124835 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 905174301 # number of misc regfile reads -system.cpu.misc_regfile_writes 3114 # number of misc regfile writes -system.cpu.icache.replacements 52 # number of replacements -system.cpu.icache.tagsinuse 687.184912 # Cycle average of tags in use -system.cpu.icache.total_refs 67496491 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 806 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 83742.544665 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 904851739 # number of misc regfile reads +system.cpu.misc_regfile_writes 3108 # number of misc regfile writes +system.cpu.icache.replacements 59 # number of replacements +system.cpu.icache.tagsinuse 698.555131 # Cycle average of tags in use +system.cpu.icache.total_refs 67409471 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 828 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 81412.404589 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 687.184912 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.335540 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.335540 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 67496491 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 67496491 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 67496491 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 67496491 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 67496491 # number of overall hits -system.cpu.icache.overall_hits::total 67496491 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1084 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1084 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1084 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1084 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1084 # number of overall misses -system.cpu.icache.overall_misses::total 1084 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38240500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38240500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38240500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38240500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38240500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38240500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 67497575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 67497575 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 67497575 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 67497575 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 67497575 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 67497575 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 698.555131 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.341091 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.341091 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 67409471 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 67409471 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 67409471 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 67409471 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 67409471 # number of overall hits +system.cpu.icache.overall_hits::total 67409471 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1108 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1108 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1108 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1108 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1108 # number of overall misses +system.cpu.icache.overall_misses::total 1108 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 38972000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 38972000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 38972000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 38972000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 38972000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 38972000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 67410579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 67410579 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 67410579 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 67410579 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 67410579 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 67410579 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35277.214022 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35277.214022 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35277.214022 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35277.214022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35277.214022 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35277.214022 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35173.285199 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35173.285199 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35173.285199 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35173.285199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35173.285199 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35173.285199 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,146 +398,146 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 278 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 278 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 278 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 278 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 278 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 278 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 806 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 806 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 806 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 806 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 806 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 806 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28447000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 28447000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28447000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 28447000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28447000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 28447000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 280 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29096500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29096500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000012 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000012 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000012 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35294.044665 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35294.044665 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 1553 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 1553 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 201726220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 201726220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 201726220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 201726220 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002278 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002278 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.036905 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.036905 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.012331 # 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miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014188 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014188 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12251.183883 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12251.183883 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15795.642625 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 15795.642625 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 10886.363636 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 10886.363636 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15422.463033 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15422.463033 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15422.463033 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15422.463033 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 30346130 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 47000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2896 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10475.010359 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 10478.636050 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 23500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 420959 # number of writebacks -system.cpu.dcache.writebacks::total 420959 # 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mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062209 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063768 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.923077 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062209 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063768 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32786.290323 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31971.608545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32069.040347 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37802.588641 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37802.588641 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32786.290323 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36647.360644 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36546.172285 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32786.290323 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36647.360644 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36546.172285 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 5489 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 6247 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 22189 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 22189 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 27678 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 28436 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 27678 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 28436 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24864000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 175443000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 200307000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 838740285 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 838740285 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24864000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1014183285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1039047285 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24864000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1014183285 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1039047285 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.915459 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.027824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.031534 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.089787 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.089787 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.915459 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.062281 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063868 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.915459 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.062281 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063868 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32802.110818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31962.652578 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32064.510965 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37799.823561 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37799.823561 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32802.110818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36642.217104 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36539.853882 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32802.110818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36642.217104 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36539.853882 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini index ad449ce69..c50a349bb 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout index 2afc8e322..21bacf71f 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:38:20 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:41:05 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt index d2a90d0bb..b109fcbb9 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.301191 # Nu sim_ticks 301191365000 # Number of ticks simulated final_tick 301191365000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3330708 # Simulator instruction rate (inst/s) -host_op_rate 3519478 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1759805795 # Simulator tick rate (ticks/s) -host_mem_usage 224176 # Number of bytes of host memory used -host_seconds 171.15 # Real time elapsed on the host +host_inst_rate 2514683 # Simulator instruction rate (inst/s) +host_op_rate 2657205 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1328652667 # Simulator tick rate (ticks/s) +host_mem_usage 218896 # Number of bytes of host memory used +host_seconds 226.69 # Real time elapsed on the host sim_insts 570051636 # Number of instructions simulated sim_ops 602359842 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 2280298100 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 602359842 # Nu system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1995305 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls system.cpu.num_int_insts 533522631 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2770242967 # number of times the integer registers were read diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini index a10276e4b..e485b6133 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,12 +182,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/gzip +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/gzip gid=100 input=cin max_stack_size=67108864 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout index 149dba9b1..2c7022400 100755 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:28:47 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:37:42 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt index 79ebe936b..7bce23d96 100644 --- a/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.795271 # Nu sim_ticks 795270546000 # Number of ticks simulated final_tick 795270546000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 873454 # Simulator instruction rate (inst/s) -host_op_rate 922399 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1221783566 # Simulator tick rate (ticks/s) -host_mem_usage 232680 # Number of bytes of host memory used -host_seconds 650.91 # Real time elapsed on the host +host_inst_rate 1274959 # Simulator instruction rate (inst/s) +host_op_rate 1346403 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1783406999 # Simulator tick rate (ticks/s) +host_mem_usage 227740 # Number of bytes of host memory used +host_seconds 445.93 # Real time elapsed on the host sim_insts 568539335 # Number of instructions simulated sim_ops 600398272 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39104 # Number of bytes read from this memory @@ -85,7 +85,7 @@ system.cpu.committedOps 600398272 # Nu system.cpu.num_int_alu_accesses 533522631 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 1995305 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 67017094 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 67050634 # number of instructions that are conditional controls system.cpu.num_int_insts 533522631 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 3212467067 # number of times the integer registers were read diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index a0763b2c7..9dfc48f3b 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,14 +513,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index 48d145b85..62518a9bb 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:39:45 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:53:48 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 28553466500 because target called exit() +Exiting @ tick 28505597000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index 757fbcd2c..1a08f1a5c 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.028553 # Number of seconds simulated -sim_ticks 28553466500 # Number of ticks simulated -final_tick 28553466500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.028506 # Number of seconds simulated +sim_ticks 28505597000 # Number of ticks simulated +final_tick 28505597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 181848 # Simulator instruction rate (inst/s) -host_op_rate 183154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57311644 # Simulator tick rate (ticks/s) -host_mem_usage 367800 # Number of bytes of host memory used -host_seconds 498.21 # Real time elapsed on the host +host_inst_rate 145688 # Simulator instruction rate (inst/s) +host_op_rate 146734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 45838175 # Simulator tick rate (ticks/s) +host_mem_usage 362080 # Number of bytes of host memory used +host_seconds 621.87 # Real time elapsed on the host sim_insts 90599368 # Number of instructions simulated sim_ops 91249921 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 45312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 947584 # Number of bytes read from this memory -system.physmem.bytes_read::total 992896 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 45312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 45312 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 708 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14806 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15514 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1586918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 33186303 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34773221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1586918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1586918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1586918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 33186303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 34773221 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 45568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 947648 # Number of bytes read from this memory +system.physmem.bytes_read::total 993216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 45568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 45568 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 712 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14807 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15519 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1598563 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33244278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34842842 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1598563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1598563 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1598563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33244278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 34842842 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,320 +70,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 57106934 # number of cpu cycles simulated +system.cpu.numCycles 57011195 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 27012699 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22277532 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 889694 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11653286 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 11426819 # Number of BTB hits +system.cpu.BPredUnit.lookups 27014403 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 22277078 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 889929 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11548760 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 11430884 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 72452 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 358 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 14542606 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 129803697 # Number of instructions fetch has processed -system.cpu.fetch.Branches 27012699 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11499271 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 24399920 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 5015488 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 14039908 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 73122 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 372 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 14508892 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 129672886 # Number of instructions fetch has processed +system.cpu.fetch.Branches 27014403 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11504006 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 24367767 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4991272 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 14021743 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 27 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 14144138 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 347071 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 57042317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.294103 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.179417 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 14122126 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 347107 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 56945823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.293943 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.179113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 32680363 57.29% 57.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3435885 6.02% 63.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2022812 3.55% 66.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1588688 2.79% 69.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1698003 2.98% 72.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 3014546 5.28% 77.91% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1479172 2.59% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1109191 1.94% 82.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10013657 17.55% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 32616008 57.28% 57.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3437208 6.04% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2033940 3.57% 66.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1577922 2.77% 69.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1684600 2.96% 72.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 3016320 5.30% 77.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1478308 2.60% 80.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1110359 1.95% 82.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 9991158 17.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 57042317 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.473020 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.272994 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17762369 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 11471319 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 22339470 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1418238 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 4050921 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4486769 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 9087 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 127953392 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 42856 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 4050921 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 19506799 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5508085 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 206847 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 21544530 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6225135 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 124612804 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1000 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 540301 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4835980 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 10850 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 145164650 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 542855215 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 542847680 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7535 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 56945823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.473844 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.274516 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17727827 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11442534 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 22314035 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1422886 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 4038541 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4486849 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 8989 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 127753929 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 42812 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 4038541 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 19463622 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5507295 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 178125 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 21532560 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6225680 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 124585344 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1117 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 540744 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4833961 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 11275 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 145162652 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 542774349 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 542766580 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7769 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107429498 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 37735152 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18216 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18214 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 14341922 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 29837938 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5556896 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2142306 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1236219 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 119143027 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 22051 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 105690693 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 78779 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27699280 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68606056 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 11919 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 57042317 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.852847 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.854849 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 37733154 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 6541 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 6539 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 14204519 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29836795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5560829 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2097523 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1243222 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 119152184 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 10385 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 105702713 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79311 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 27697349 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68611569 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 253 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 56945823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.856198 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.856170 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17381718 30.47% 30.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13049544 22.88% 53.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 8518143 14.93% 68.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6991208 12.26% 80.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5292177 9.28% 89.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2744999 4.81% 94.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2144277 3.76% 98.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 490134 0.86% 99.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 430117 0.75% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17311609 30.40% 30.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13029602 22.88% 53.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 8527913 14.98% 68.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6948954 12.20% 80.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5271164 9.26% 89.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2793517 4.91% 94.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2152448 3.78% 98.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 481434 0.85% 99.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 429182 0.75% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 57042317 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 56945823 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 40944 6.13% 6.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 27 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 349072 52.27% 58.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 277751 41.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 40477 6.05% 6.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 27 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 349114 52.21% 58.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 279085 41.74% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 74708862 70.69% 70.69% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10518 0.01% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 221 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 275 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 74715129 70.68% 70.68% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10969 0.01% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 1 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 226 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.69% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 287 0.00% 70.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 70.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 70.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 25829491 24.44% 95.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5141321 4.86% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 25832645 24.44% 95.13% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5143450 4.87% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 105690693 # Type of FU issued -system.cpu.iq.rate 1.850751 # Inst issue rate -system.cpu.iq.fu_busy_cnt 667794 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.006318 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 269169203 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 146866507 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 102954305 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1073 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1626 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 453 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 106357959 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 528 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 425504 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 105702713 # Type of FU issued +system.cpu.iq.rate 1.854069 # Inst issue rate +system.cpu.iq.fu_busy_cnt 668703 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.006326 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 269098152 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 146861999 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 102960296 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1111 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1652 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 475 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 106370866 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 550 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 430808 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7262058 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7178 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4608 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 810138 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7260915 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7599 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 4486 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 814071 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 165527 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 165011 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 4050921 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 893670 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 117044 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 119201460 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 342636 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 29837938 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5556896 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18147 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 49262 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 15777 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4608 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 477903 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 486113 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 964016 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 104633146 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25499061 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1057547 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 4038541 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 891747 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 116973 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 119175285 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 342275 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29836795 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5560829 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6480 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 49074 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 15714 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 4486 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 478618 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 473981 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 952599 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 104642381 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25500898 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1060332 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 36382 # number of nop insts executed -system.cpu.iew.exec_refs 30575453 # number of memory reference insts executed -system.cpu.iew.exec_branches 21352915 # Number of branches executed -system.cpu.iew.exec_stores 5076392 # Number of stores executed -system.cpu.iew.exec_rate 1.832232 # Inst execution rate -system.cpu.iew.wb_sent 103240911 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 102954758 # cumulative count of insts written-back -system.cpu.iew.wb_producers 61949538 # num instructions producing a value -system.cpu.iew.wb_consumers 102898807 # num instructions consuming a value +system.cpu.iew.exec_nop 12716 # number of nop insts executed +system.cpu.iew.exec_refs 30579562 # number of memory reference insts executed +system.cpu.iew.exec_branches 21366362 # Number of branches executed +system.cpu.iew.exec_stores 5078664 # Number of stores executed +system.cpu.iew.exec_rate 1.835471 # Inst execution rate +system.cpu.iew.wb_sent 103249709 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 102960771 # cumulative count of insts written-back +system.cpu.iew.wb_producers 61941288 # num instructions producing a value +system.cpu.iew.wb_consumers 102916553 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.802842 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.602043 # average fanout of values written-back +system.cpu.iew.wb_rate 1.805975 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.601859 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 27941572 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 27915285 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10132 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 892650 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 52991397 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.722214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.475842 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 881077 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 52907283 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.724952 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.476924 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23013346 43.43% 43.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13498664 25.47% 68.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4267920 8.05% 76.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3605539 6.80% 83.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1555941 2.94% 86.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 706178 1.33% 88.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 916105 1.73% 89.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 261507 0.49% 90.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5166197 9.75% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22917585 43.32% 43.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13525297 25.56% 68.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4253401 8.04% 76.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3602316 6.81% 83.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1554565 2.94% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 724715 1.37% 88.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 894547 1.69% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 264490 0.50% 90.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5170367 9.77% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 52991397 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 52907283 # Number of insts commited each cycle system.cpu.commit.committedInsts 90611977 # Number of instructions committed system.cpu.commit.committedOps 91262530 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 27322638 # Number of memory references committed system.cpu.commit.loads 22575880 # Number of loads committed system.cpu.commit.membars 3888 # Number of memory barriers committed -system.cpu.commit.branches 18722474 # Number of branches committed +system.cpu.commit.branches 18734218 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. system.cpu.commit.int_insts 72533330 # Number of committed integer instructions. system.cpu.commit.function_calls 56148 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5166197 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5170367 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 167023568 # The number of ROB reads -system.cpu.rob.rob_writes 242480145 # The number of ROB writes -system.cpu.timesIdled 16985 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 64617 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 166908997 # The number of ROB reads +system.cpu.rob.rob_writes 242415249 # The number of ROB writes +system.cpu.timesIdled 17140 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 65372 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90599368 # Number of Instructions Simulated system.cpu.committedOps 91249921 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 90599368 # Number of Instructions Simulated -system.cpu.cpi 0.630324 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.630324 # CPI: Total CPI of All Threads -system.cpu.ipc 1.586486 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.586486 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 497500268 # number of integer regfile reads -system.cpu.int_regfile_writes 120842597 # number of integer regfile writes -system.cpu.fp_regfile_reads 229 # number of floating regfile reads -system.cpu.fp_regfile_writes 593 # number of floating regfile writes -system.cpu.misc_regfile_reads 183620284 # number of misc regfile reads +system.cpu.cpi 0.629267 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.629267 # CPI: Total CPI of All Threads +system.cpu.ipc 1.589150 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.589150 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 497539806 # number of integer regfile reads +system.cpu.int_regfile_writes 120848373 # number of integer regfile writes +system.cpu.fp_regfile_reads 239 # number of floating regfile reads +system.cpu.fp_regfile_writes 624 # number of floating regfile writes +system.cpu.misc_regfile_reads 183493284 # number of misc regfile reads system.cpu.misc_regfile_writes 11612 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 638.455928 # Cycle average of tags in use -system.cpu.icache.total_refs 14143171 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 734 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 19268.625341 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 636.231301 # Cycle average of tags in use +system.cpu.icache.total_refs 14121140 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 738 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 19134.336043 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 638.455928 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.311746 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.311746 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 14143171 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14143171 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 14143171 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14143171 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 14143171 # number of overall hits -system.cpu.icache.overall_hits::total 14143171 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 967 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 967 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 967 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 967 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 967 # number of overall misses -system.cpu.icache.overall_misses::total 967 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 35020500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 35020500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 35020500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 35020500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 35020500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 35020500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 14144138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 14144138 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 14144138 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 14144138 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 14144138 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 14144138 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000068 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000068 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000068 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000068 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000068 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000068 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36215.615305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36215.615305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36215.615305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36215.615305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36215.615305 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 636.231301 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.310660 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.310660 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 14121140 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 14121140 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 14121140 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 14121140 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 14121140 # number of overall hits +system.cpu.icache.overall_hits::total 14121140 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 986 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 986 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 986 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 986 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 986 # number of overall misses +system.cpu.icache.overall_misses::total 986 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 35670500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 35670500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 35670500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 35670500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 35670500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 35670500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 14122126 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 14122126 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 14122126 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 14122126 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 14122126 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 14122126 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000070 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000070 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000070 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000070 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000070 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000070 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36176.977688 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36176.977688 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36176.977688 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36176.977688 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36176.977688 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,246 +392,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 233 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 233 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 233 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 233 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 233 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 233 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 734 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 734 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 734 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26444000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 26444000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26444000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 26444000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26444000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 26444000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 738 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 738 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 738 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 738 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26658000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26658000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26658000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26658000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26658000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26658000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36027.247956 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36027.247956 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36027.247956 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36027.247956 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36121.951220 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36121.951220 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36121.951220 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36121.951220 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 943512 # number of replacements -system.cpu.dcache.tagsinuse 3689.791275 # Cycle average of tags in use -system.cpu.dcache.total_refs 28381642 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 947608 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 29.950826 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 8154700000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3689.791275 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.900828 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.900828 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 23801988 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23801988 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4567984 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4567984 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 5869 # 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number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4568472 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 5862 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 5862 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5801 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5801 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 28369972 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28369972 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28369972 # number of overall hits -system.cpu.dcache.overall_hits::total 28369972 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1060525 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1060525 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 166997 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 166997 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 28366732 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28366732 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28366732 # number of overall hits +system.cpu.dcache.overall_hits::total 28366732 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1060889 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1060889 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 166509 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 166509 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 8 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 8 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1227522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1227522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1227522 # number of overall misses -system.cpu.dcache.overall_misses::total 1227522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21965060500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21965060500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6217004264 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6217004264 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 153500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 153500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28182064764 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28182064764 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28182064764 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28182064764 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24862513 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24862513 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1227398 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1227398 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1227398 # number of overall misses +system.cpu.dcache.overall_misses::total 1227398 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 21973475500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 21973475500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6211010261 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6211010261 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 161000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 161000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28184485761 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28184485761 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28184485761 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28184485761 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24859149 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24859149 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5877 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 5877 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5870 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 5870 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5801 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5801 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 29597494 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 29597494 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 29597494 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 29597494 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042656 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.042656 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.035269 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001361 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001361 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_accesses::cpu.data 29594130 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 29594130 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 29594130 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 29594130 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042676 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042676 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.035166 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.035166 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.001363 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.001363 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.041474 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.041474 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.041474 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.041474 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20711.497136 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20711.497136 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37228.239214 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37228.239214 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19187.500000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22958.500755 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22958.500755 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22958.500755 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 78852438 # number of cycles access was blocked +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20712.322873 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 20712.322873 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37301.348642 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37301.348642 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20125 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20125 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22962.792640 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22962.792640 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22962.792640 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 78891432 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 9147 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 9153 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8620.579206 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8619.188463 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 942869 # number of writebacks -system.cpu.dcache.writebacks::total 942869 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148009 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 148009 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131905 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 131905 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 942894 # number of writebacks +system.cpu.dcache.writebacks::total 942894 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 148366 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 148366 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 131394 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 131394 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 8 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 8 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 279914 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 279914 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 279914 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 279914 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912516 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 912516 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35092 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 35092 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 947608 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 947608 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 947608 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 947608 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16755802500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16755802500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1751499399 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1751499399 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18507301899 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18507301899 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18507301899 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18507301899 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036702 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036702 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007411 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007411 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.032016 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032016 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.032016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18362.201320 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18362.201320 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49911.643651 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49911.643651 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19530.546280 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 19530.546280 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 279760 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 279760 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 279760 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 279760 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 912523 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 912523 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 35115 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 35115 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 947638 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 947638 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 947638 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 947638 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16758552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 16758552000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1752488893 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1752488893 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18511040893 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18511040893 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18511040893 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18511040893 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.036708 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.036708 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007416 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007416 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18365.073538 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18365.073538 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49907.130656 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49907.130656 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.873581 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19533.873581 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 10958.956435 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1839863 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 15497 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 118.723818 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 10969.237336 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1839897 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 15502 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 118.687718 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 10102.128367 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 622.173685 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 234.654384 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.308292 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.018987 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.007161 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.334441 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::writebacks 10112.492667 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 621.566782 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 235.177887 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.308609 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.018969 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.007177 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.334755 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 912088 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 912112 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 942869 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 942869 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 20704 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 20704 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 912096 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 912120 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 942894 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 942894 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 20725 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 20725 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932792 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 932816 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932821 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 932845 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 24 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932792 # number of overall hits -system.cpu.l2cache.overall_hits::total 932816 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 710 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 281 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 991 # number of ReadReq misses +system.cpu.l2cache.overall_hits::cpu.data 932821 # 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average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34385.173719 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34491.951581 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35759.103641 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34430.890194 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34491.951581 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -649,50 +649,50 @@ system.cpu.l2cache.demand_mshr_hits::total 12 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 12 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 708 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 979 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 712 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 984 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14535 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14535 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 708 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14806 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 712 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14807 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 15519 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 712 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14807 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 15519 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23240000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9198500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32438500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 453435000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 453435000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23240000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 462633500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 485873500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23240000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 462633500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 485873500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000298 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001078 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412223 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412223 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.016359 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964578 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.016364 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964770 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.016359 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32607.344633 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33704.797048 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32911.133810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.353629 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.353629 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32607.344633 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31242.266649 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31304.563620 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.016364 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32640.449438 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33818.014706 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32965.955285 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31196.078431 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31196.078431 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32640.449438 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31244.242588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31308.299504 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index 0837df787..c70c9e062 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,14 +95,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index f567cacf4..fa062edc0 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:44:35 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 14:03:25 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 6111a0118..42f3c00f3 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054241 # Nu sim_ticks 54240661000 # Number of ticks simulated final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3184418 # Simulator instruction rate (inst/s) -host_op_rate 3207282 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1906403630 # Simulator tick rate (ticks/s) -host_mem_usage 357244 # Number of bytes of host memory used -host_seconds 28.45 # Real time elapsed on the host +host_inst_rate 2374877 # Simulator instruction rate (inst/s) +host_op_rate 2391929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1421759359 # Simulator tick rate (ticks/s) +host_mem_usage 351688 # Number of bytes of host memory used +host_seconds 38.15 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91252960 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 91252960 # Nu system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 396912478 # number of times the integer registers were read diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 172c79802..9c2aed7c6 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,14 +182,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=mcf mcf.in -cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/projects/pd/randd/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index 092850ece..364027fbc 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:40:44 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:45:02 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 4b16c09c3..3cd60c7e5 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.148268 # Nu sim_ticks 148267705000 # Number of ticks simulated final_tick 148267705000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1021914 # Simulator instruction rate (inst/s) -host_op_rate 1029241 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1672798092 # Simulator tick rate (ticks/s) -host_mem_usage 365748 # Number of bytes of host memory used -host_seconds 88.63 # Real time elapsed on the host +host_inst_rate 1153616 # Simulator instruction rate (inst/s) +host_op_rate 1161887 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1888384270 # Simulator tick rate (ticks/s) +host_mem_usage 360564 # Number of bytes of host memory used +host_seconds 78.52 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory @@ -78,7 +78,7 @@ system.cpu.committedOps 91226312 # Nu system.cpu.num_int_alu_accesses 72525674 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15548925 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 15549034 # number of instructions that are conditional controls system.cpu.num_int_insts 72525674 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions system.cpu.num_int_register_reads 464563355 # number of times the integer registers were read diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index d7217517d..0d4631b4b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -512,9 +518,9 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -535,8 +541,9 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index 2e50d7c5a..ccc3391a2 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 26 2012 21:40:00 -gem5 started Jul 27 2012 01:18:01 -gem5 executing on zizzer +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:11:01 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 213305827500 because target called exit() +Exiting @ tick 205972871500 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c461f7be8..5b82c90b2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.213288 # Number of seconds simulated -sim_ticks 213288042000 # Number of ticks simulated -final_tick 213288042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.205973 # Number of seconds simulated +sim_ticks 205972871500 # Number of ticks simulated +final_tick 205972871500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 175103 # Simulator instruction rate (inst/s) -host_op_rate 197255 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 73380577 # Simulator tick rate (ticks/s) -host_mem_usage 239036 # Number of bytes of host memory used -host_seconds 2906.60 # Real time elapsed on the host -sim_insts 508955143 # Number of instructions simulated -sim_ops 573341703 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 218176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10017792 # Number of bytes read from this memory -system.physmem.bytes_read::total 10235968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 218176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 218176 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6680384 # Number of bytes written to this memory -system.physmem.bytes_written::total 6680384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3409 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 156528 # Number of read requests responded to by this memory -system.physmem.num_reads::total 159937 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 104381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 104381 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1022917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 46968372 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47991289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1022917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1022917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 31320950 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 31320950 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 31320950 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1022917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 46968372 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 79312238 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 120709 # Simulator instruction rate (inst/s) +host_op_rate 135980 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48850733 # Simulator tick rate (ticks/s) +host_mem_usage 233344 # Number of bytes of host memory used +host_seconds 4216.37 # Real time elapsed on the host +sim_insts 508955133 # Number of instructions simulated +sim_ops 573341693 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10022656 # Number of bytes read from this memory +system.physmem.bytes_read::total 10241664 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6678912 # Number of bytes written to this memory +system.physmem.bytes_written::total 6678912 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 156604 # Number of read requests responded to by this memory +system.physmem.num_reads::total 160026 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 104358 # Number of write requests responded to by this memory +system.physmem.num_writes::total 104358 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1063286 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 48660078 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49723364 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1063286 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1063286 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 32426173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 32426173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 32426173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1063286 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 48660078 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 82149537 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,319 +77,319 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 426576085 # number of cpu cycles simulated +system.cpu.numCycles 411945744 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 180740413 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 143314852 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 7747678 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 94843879 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 87610894 # Number of BTB hits +system.cpu.BPredUnit.lookups 184506499 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 144023121 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 7811219 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 98943918 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 90574887 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 12444215 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 117322 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 121008241 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 797329554 # Number of instructions fetch has processed -system.cpu.fetch.Branches 180740413 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 100055109 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 177305493 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 41694280 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 95788373 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 733 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 114354334 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2502299 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 425002999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.155911 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.022478 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 12841570 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 116417 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 119775248 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 774733961 # Number of instructions fetch has processed +system.cpu.fetch.Branches 184506499 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 103416457 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 173948363 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 37641339 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 87608822 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 852 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 115427194 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2630422 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 410365766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.121718 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.964259 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 247710334 58.28% 58.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14399236 3.39% 61.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 20683472 4.87% 66.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22949546 5.40% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 21027590 4.95% 76.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13189722 3.10% 79.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13290408 3.13% 83.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 12169042 2.86% 85.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 59583649 14.02% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 236430239 57.61% 57.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14468090 3.53% 61.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 23474699 5.72% 66.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 23086036 5.63% 72.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 21070083 5.13% 77.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13375231 3.26% 80.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13311792 3.24% 84.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 12219273 2.98% 87.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52930323 12.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 425002999 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.423700 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.869138 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 133837358 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 89905115 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 165211809 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5224015 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 30824702 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26552626 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 78407 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 873532911 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 312665 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 30824702 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 144300164 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8880120 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 66226908 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 159798205 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14972900 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 818719964 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1527 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2831804 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8232958 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 169 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 966624126 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3574819006 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3574814464 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4542 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 672200163 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 294423963 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5324035 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5323684 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 70502461 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 172694215 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 75173419 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 27528293 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15558221 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 763633649 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 6775757 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 672560408 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1538791 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 194774219 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 494406883 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3054641 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 425002999 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.582484 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.714723 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 410365766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.447890 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.880670 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 130418481 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 81705760 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 163995815 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5288696 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 28957014 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26711151 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 78514 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 846352874 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 312360 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 28957014 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 138753027 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8994220 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 57785261 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 160771479 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15104765 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 816103533 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1687 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2833405 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8341364 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 82 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 971919658 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3572964194 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3572962534 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1660 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 672200147 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 299719511 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 3043063 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 3043057 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 48313295 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 173521024 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 75304332 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 27654560 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15950244 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 766864948 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4467940 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 673990845 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1544807 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 195857289 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 503525509 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 746826 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 410365766 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.642415 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.726112 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 161186473 37.93% 37.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 79207972 18.64% 56.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71181654 16.75% 73.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 52720158 12.40% 85.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 30652473 7.21% 92.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16004592 3.77% 96.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9408207 2.21% 98.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3385200 0.80% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1256270 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148669222 36.23% 36.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 76514251 18.65% 54.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 69467282 16.93% 71.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 54325200 13.24% 85.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31258060 7.62% 92.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 16137199 3.93% 96.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9372373 2.28% 98.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3363475 0.82% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1258704 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 425002999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 410365766 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 468819 4.82% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6672896 68.60% 73.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2585103 26.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 465577 4.81% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6648335 68.74% 73.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2557266 26.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 451779647 67.17% 67.17% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 385833 0.06% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 224 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 155287999 23.09% 90.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 65106702 9.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 452813787 67.18% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 386318 0.06% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 122 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.24% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 155728522 23.11% 90.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 65062093 9.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 672560408 # Type of FU issued -system.cpu.iq.rate 1.576648 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9726818 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014462 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1781388941 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 965987028 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 652168068 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 483 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 954 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 673990845 # Type of FU issued +system.cpu.iq.rate 1.636116 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9671178 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014349 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1769563162 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 967995399 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 653126941 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 279 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 382 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 682286983 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 243 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8456716 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 683661882 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8511001 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 45921176 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 43296 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 808281 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 17569458 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 46747987 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 44107 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 809559 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 17700373 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19481 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1162 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19520 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1145 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 30824702 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4157242 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 268994 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 776579176 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1213475 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 172694215 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 75173419 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5287043 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 138286 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 7916 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 808281 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4709079 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 6438741 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11147820 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 662598495 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 151749553 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9961913 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 28957014 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4178303 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 271851 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 772908179 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1249751 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 173521024 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 75304332 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2979209 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 139047 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8399 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 809559 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4765794 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4187317 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8953111 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 663675930 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 152077702 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10314915 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 6169770 # number of nop insts executed -system.cpu.iew.exec_refs 215449893 # number of memory reference insts executed -system.cpu.iew.exec_branches 137324622 # Number of branches executed -system.cpu.iew.exec_stores 63700340 # Number of stores executed -system.cpu.iew.exec_rate 1.553295 # Inst execution rate -system.cpu.iew.wb_sent 657360539 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 652168084 # cumulative count of insts written-back -system.cpu.iew.wb_producers 375706484 # num instructions producing a value -system.cpu.iew.wb_consumers 644527400 # num instructions consuming a value +system.cpu.iew.exec_nop 1575291 # number of nop insts executed +system.cpu.iew.exec_refs 215744053 # number of memory reference insts executed +system.cpu.iew.exec_branches 139807568 # Number of branches executed +system.cpu.iew.exec_stores 63666351 # Number of stores executed +system.cpu.iew.exec_rate 1.611076 # Inst execution rate +system.cpu.iew.wb_sent 658363692 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 653126957 # cumulative count of insts written-back +system.cpu.iew.wb_producers 376897633 # num instructions producing a value +system.cpu.iew.wb_consumers 649094102 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.528844 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.582918 # average fanout of values written-back +system.cpu.iew.wb_rate 1.585468 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.580652 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 201913792 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 3721116 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9922149 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 394178298 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.457933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.151181 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 198243748 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 3721114 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 7735785 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 381408753 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.506745 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.186982 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 179646663 45.57% 45.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 103047571 26.14% 71.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 36291741 9.21% 80.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18910694 4.80% 85.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16473731 4.18% 89.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8163992 2.07% 91.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6899886 1.75% 93.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3743908 0.95% 94.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 21000112 5.33% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 167968054 44.04% 44.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 103591951 27.16% 71.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 34406436 9.02% 80.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 19105358 5.01% 85.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16473336 4.32% 89.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7646678 2.00% 91.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6906631 1.81% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3084312 0.81% 94.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22225997 5.83% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 394178298 # Number of insts commited each cycle -system.cpu.commit.committedInsts 510299027 # Number of instructions committed -system.cpu.commit.committedOps 574685587 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 381408753 # Number of insts commited each cycle +system.cpu.commit.committedInsts 510299017 # Number of instructions committed +system.cpu.commit.committedOps 574685577 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 184377000 # Number of memory references committed -system.cpu.commit.loads 126773039 # Number of loads committed +system.cpu.commit.refs 184376996 # Number of memory references committed +system.cpu.commit.loads 126773037 # Number of loads committed system.cpu.commit.membars 1488542 # Number of memory barriers committed -system.cpu.commit.branches 120192224 # Number of branches committed +system.cpu.commit.branches 122291783 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 473701629 # Number of committed integer instructions. +system.cpu.commit.int_insts 473701621 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 21000112 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22225997 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1149770427 # The number of ROB reads -system.cpu.rob.rob_writes 1584166126 # The number of ROB writes -system.cpu.timesIdled 75828 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1573086 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 508955143 # Number of Instructions Simulated -system.cpu.committedOps 573341703 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 508955143 # Number of Instructions Simulated -system.cpu.cpi 0.838141 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.838141 # CPI: Total CPI of All Threads -system.cpu.ipc 1.193117 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.193117 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3092127855 # number of integer regfile reads -system.cpu.int_regfile_writes 760494999 # number of integer regfile writes +system.cpu.rob.rob_reads 1132104943 # The number of ROB reads +system.cpu.rob.rob_writes 1574958649 # The number of ROB writes +system.cpu.timesIdled 76497 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1579978 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 508955133 # Number of Instructions Simulated +system.cpu.committedOps 573341693 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 508955133 # Number of Instructions Simulated +system.cpu.cpi 0.809395 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.809395 # CPI: Total CPI of All Threads +system.cpu.ipc 1.235491 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.235491 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3096810735 # number of integer regfile reads +system.cpu.int_regfile_writes 761477780 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 1025229715 # number of misc regfile reads -system.cpu.misc_regfile_writes 4464052 # number of misc regfile writes -system.cpu.icache.replacements 16005 # number of replacements -system.cpu.icache.tagsinuse 1098.211630 # Cycle average of tags in use -system.cpu.icache.total_refs 114334583 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 17866 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6399.562465 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 1003236717 # number of misc regfile reads +system.cpu.misc_regfile_writes 4464048 # number of misc regfile writes +system.cpu.icache.replacements 15737 # number of replacements +system.cpu.icache.tagsinuse 1093.946958 # Cycle average of tags in use +system.cpu.icache.total_refs 115407568 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 17598 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6557.993408 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1098.211630 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.536236 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.536236 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114334583 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114334583 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114334583 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114334583 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114334583 # number of overall hits -system.cpu.icache.overall_hits::total 114334583 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19751 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19751 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19751 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19751 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19751 # number of overall misses -system.cpu.icache.overall_misses::total 19751 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 282522500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 282522500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 282522500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 282522500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 282522500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 282522500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114354334 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114354334 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114354334 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114354334 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114354334 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114354334 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000173 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000173 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000173 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000173 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000173 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000173 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14304.212445 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14304.212445 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14304.212445 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14304.212445 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14304.212445 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14304.212445 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1093.946958 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.534154 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.534154 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 115407568 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 115407568 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 115407568 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 115407568 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 115407568 # number of overall hits +system.cpu.icache.overall_hits::total 115407568 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19626 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19626 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19626 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19626 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19626 # number of overall misses +system.cpu.icache.overall_misses::total 19626 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 282974000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 282974000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 282974000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 282974000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 282974000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 282974000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115427194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115427194 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115427194 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115427194 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115427194 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115427194 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000170 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000170 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000170 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000170 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000170 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000170 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14418.322633 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14418.322633 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14418.322633 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14418.322633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14418.322633 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14418.322633 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -398,258 +398,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1832 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1832 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1832 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1832 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1832 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1832 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17919 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 17919 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 17919 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 17919 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 17919 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 17919 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 184521500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 184521500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 184521500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 184521500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 184521500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 184521500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000157 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000157 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000157 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000157 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000157 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000157 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10297.533344 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10297.533344 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10297.533344 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 10297.533344 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10297.533344 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 10297.533344 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1971 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1971 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1971 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1971 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1971 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1971 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 17655 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000153 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000153 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000153 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000153 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000153 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000153 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10426.479751 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10426.479751 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10426.479751 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 10426.479751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10426.479751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 10426.479751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1188505 # number of replacements -system.cpu.dcache.tagsinuse 4054.525384 # Cycle average of tags in use -system.cpu.dcache.total_refs 194736963 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1192601 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 163.287607 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 4858281000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4054.525384 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.989874 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.989874 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 137587270 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 137587270 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 52684677 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 52684677 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 2232876 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 2232876 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 2232025 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 2232025 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 190271947 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 190271947 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 190271947 # number of overall hits -system.cpu.dcache.overall_hits::total 190271947 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1267361 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1267361 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1554629 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1554629 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 41 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 41 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 2821990 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2821990 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2821990 # number of overall misses -system.cpu.dcache.overall_misses::total 2821990 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 15534754000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 15534754000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33071578000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33071578000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 516500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 516500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48606332000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48606332000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48606332000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48606332000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 138854631 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 138854631 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1189180 # number of replacements +system.cpu.dcache.tagsinuse 4054.532653 # Cycle average of tags in use +system.cpu.dcache.total_refs 194989715 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1193276 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 163.407053 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 4672860000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4054.532653 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.989876 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.989876 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 137842002 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 137842002 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 52682481 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 52682481 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 2233095 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 2233095 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 2232023 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 2232023 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 190524483 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 190524483 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 190524483 # number of overall hits +system.cpu.dcache.overall_hits::total 190524483 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1271675 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1271675 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1556825 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1556825 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 43 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 43 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2828500 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2828500 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2828500 # number of overall misses +system.cpu.dcache.overall_misses::total 2828500 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 15608550500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 15608550500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33157971000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33157971000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 519500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 519500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48766521500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48766521500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48766521500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48766521500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 139113677 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 139113677 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2232917 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 2232917 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232025 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 2232025 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 193093937 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 193093937 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 193093937 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 193093937 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009127 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.009127 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028662 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028662 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000018 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000018 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.014615 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.014615 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.014615 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.014615 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12257.560395 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12257.560395 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21272.971236 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21272.971236 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12597.560976 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12597.560976 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 17224.133324 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 17224.133324 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 17224.133324 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 17224.133324 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 2233138 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 2233138 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 2232023 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 2232023 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 193352983 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 193352983 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 193352983 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 193352983 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009141 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.009141 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028703 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028703 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000019 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000019 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.014629 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.014629 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.014629 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.014629 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12274.009083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12274.009083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21298.457437 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21298.457437 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12081.395349 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12081.395349 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 17241.124801 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 17241.124801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17241.124801 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17241.124801 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3250000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3198500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 557 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 556 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5834.829443 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 5752.697842 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1102963 # number of writebacks -system.cpu.dcache.writebacks::total 1102963 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422886 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 422886 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1206451 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1206451 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1629337 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1629337 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1629337 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1629337 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 844475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 844475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348178 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348178 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1192653 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1192653 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1192653 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1192653 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4797282000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4797282000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4282442001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4282442001 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9079724001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9079724001 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9079724001 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9079724001 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006082 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006419 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006419 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006177 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006177 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006177 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006177 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 5680.786287 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5680.786287 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12299.576656 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12299.576656 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7613.047551 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7613.047551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7613.047551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7613.047551 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1103627 # number of writebacks +system.cpu.dcache.writebacks::total 1103627 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 426551 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 426551 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1208619 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1208619 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 43 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1635170 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1635170 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1635170 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1635170 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 845124 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 845124 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348206 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348206 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1193330 # 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number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9091945501 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006075 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006075 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006420 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006420 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006172 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006172 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006172 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006172 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 5688.773482 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 5688.773482 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12303.712460 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 12303.712460 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7618.970026 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7618.970026 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7618.970026 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7618.970026 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 128744 # number of replacements -system.cpu.l2cache.tagsinuse 26549.966960 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1724517 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 159966 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 10.780522 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 109550119000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 22719.596227 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 306.601446 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3523.769287 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.693347 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.009357 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.107537 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.810241 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 14447 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 787382 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 801829 # 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number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53074 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 56489 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 8 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 103480 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 103480 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3415 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 156554 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 159969 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3415 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 156554 # number of overall misses -system.cpu.l2cache.overall_misses::total 159969 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120654000 # 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Cycle average of tags in use +system.cpu.l2cache.total_refs 1724855 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 160033 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 10.778121 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 106591903000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 22677.867679 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 308.367342 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3517.590417 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.692074 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.009411 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.107348 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.808833 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 14164 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31454.337738 # average ReadReq mshr miss latency +system.cpu.l2cache.writebacks::writebacks 104358 # number of writebacks +system.cpu.l2cache.writebacks::total 104358 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 7 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 7 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 7 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 28 # 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number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4881219000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4991549000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110330000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4881219000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4991549000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194509 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.063164 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.065855 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.074074 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.074074 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.293923 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.293923 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194509 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.131240 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.132159 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194509 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.131240 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.132159 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32241.379310 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31403.118354 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31453.835817 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31047.298995 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31047.298995 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32220.299208 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31168.566208 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31190.983381 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32220.299208 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31168.566208 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31190.983381 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31048.744539 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31048.744539 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32241.379310 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31168.985665 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31191.917614 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32241.379310 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31168.985665 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31191.917614 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index b319ef658..b8f82bdb1 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,14 +95,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index 5020b6420..44b6f8e46 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:45:54 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:53:48 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index d3328d763..c1ae2a092 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.290499 # Nu sim_ticks 290498967000 # Number of ticks simulated final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3026360 # Simulator instruction rate (inst/s) -host_op_rate 3411010 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1735464120 # Simulator tick rate (ticks/s) -host_mem_usage 228428 # Number of bytes of host memory used -host_seconds 167.39 # Real time elapsed on the host +host_inst_rate 2312706 # Simulator instruction rate (inst/s) +host_op_rate 2606651 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1326219887 # Simulator tick rate (ticks/s) +host_mem_usage 222284 # Number of bytes of host memory used +host_seconds 219.04 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 570968167 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 570968167 # Nu system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2465023683 # number of times the integer registers were read diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index ffe909bf7..b61e69811 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,14 +182,14 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=parser 2.1.dict -batch -cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/projects/pd/randd/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 384283516..256134bc2 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:48:14 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:31:48 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index b8350e4f6..3143a40a6 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.720346 # Nu sim_ticks 720345914000 # Number of ticks simulated final_tick 720345914000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 808443 # Simulator instruction rate (inst/s) -host_op_rate 910979 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1153216038 # Simulator tick rate (ticks/s) -host_mem_usage 236932 # Number of bytes of host memory used -host_seconds 624.64 # Real time elapsed on the host +host_inst_rate 1112468 # Simulator instruction rate (inst/s) +host_op_rate 1253563 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1586896277 # Simulator tick rate (ticks/s) +host_mem_usage 231144 # Number of bytes of host memory used +host_seconds 453.93 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 178368 # Number of bytes read from this memory @@ -85,7 +85,7 @@ system.cpu.committedOps 569034839 # Nu system.cpu.num_int_alu_accesses 470727695 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 19311615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 94894804 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 94895872 # number of instructions that are conditional controls system.cpu.num_int_insts 470727695 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions system.cpu.num_int_register_reads 2844375179 # number of times the integer registers were read diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index e98d14637..ca4ea2a9a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,12 +513,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index 7d2acfcbb..2e2e5579e 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:48:29 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 13:21:28 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.070000 -Exiting @ tick 71229334000 because target called exit() +Exiting @ tick 70907303500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 17a63d224..57c2e3ca3 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.071229 # Number of seconds simulated -sim_ticks 71229334000 # Number of ticks simulated -final_tick 71229334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.070907 # Number of seconds simulated +sim_ticks 70907303500 # Number of ticks simulated +final_tick 70907303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127900 # Simulator instruction rate (inst/s) -host_op_rate 163512 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33364795 # Simulator tick rate (ticks/s) -host_mem_usage 243124 # Number of bytes of host memory used -host_seconds 2134.87 # Real time elapsed on the host -sim_insts 273048466 # Number of instructions simulated -sim_ops 349076190 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 195712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 273280 # Number of bytes read from this memory -system.physmem.bytes_read::total 468992 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 195712 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 195712 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3058 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 4270 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2747632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3836622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6584254 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2747632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2747632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2747632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3836622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6584254 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 128530 # Simulator instruction rate (inst/s) +host_op_rate 164318 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 33377575 # Simulator tick rate (ticks/s) +host_mem_usage 237852 # Number of bytes of host memory used +host_seconds 2124.40 # Real time elapsed on the host +sim_insts 273048456 # Number of instructions simulated +sim_ops 349076180 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 194688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 272448 # Number of bytes read from this memory +system.physmem.bytes_read::total 467136 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 194688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 194688 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3042 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 4257 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7299 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2745669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3842312 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6587981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2745669 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2745669 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2745669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3842312 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6587981 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,107 +70,107 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 142458669 # number of cpu cycles simulated +system.cpu.numCycles 141814608 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 36827289 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 22021149 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 2124112 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 21185272 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 17907212 # Number of BTB hits +system.cpu.BPredUnit.lookups 43021564 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 21750711 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 2101631 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 27856122 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 17838153 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 7048127 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 9776 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 41164597 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 330015965 # Number of instructions fetch has processed -system.cpu.fetch.Branches 36827289 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24955339 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 74037174 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 8640903 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 20677414 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 3984 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 39570950 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 662120 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 142347473 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.981638 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.456068 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 6966793 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 7520 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40921334 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 328638556 # Number of instructions fetch has processed +system.cpu.fetch.Branches 43021564 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24804946 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 73672457 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 8389816 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 20828697 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 32 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 3338 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 39391876 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 684935 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 141703595 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.981779 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.454940 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69001909 48.47% 48.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 7430233 5.22% 53.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 5888428 4.14% 57.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 6296154 4.42% 62.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 5019761 3.53% 65.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 4223315 2.97% 68.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3223904 2.26% 71.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 4316057 3.03% 74.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 36947712 25.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 68712087 48.49% 48.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 7380491 5.21% 53.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 5816522 4.10% 57.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6226633 4.39% 62.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4949598 3.49% 65.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 4317646 3.05% 68.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3315601 2.34% 71.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4325062 3.05% 74.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 36659955 25.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 142347473 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.258512 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.316573 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 47914284 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 15959399 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 69656008 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2423234 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6394548 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 7585679 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 70199 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 416758303 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 209359 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6394548 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 53729037 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1556343 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 362126 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 66198989 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14106430 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 406180848 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 80 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1648620 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 10123493 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1169 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 445266108 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2397137405 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1309627482 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1087509923 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 384584986 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 60681122 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 19329 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 19327 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 35836582 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 105837544 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 93231927 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 4645950 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5672170 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 392964645 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 30275 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 378555721 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1363581 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 42910046 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 113514871 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5793 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 142347473 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.659378 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.045296 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 141703595 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.303365 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.317382 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 47754995 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16062481 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 69284862 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2393411 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6207846 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 7495010 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 70679 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 414601239 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 219868 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6207846 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 53518393 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1558450 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341275 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 65839797 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14237834 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 404012192 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 94 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1667987 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 10221278 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1168 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 443337202 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2387138833 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1300349332 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1086789501 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 384584970 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 58752232 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 14504 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 14503 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 35673328 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 105504454 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 93209227 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 4624259 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5728531 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 391940261 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 25587 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 377964584 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1402397 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 41905319 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 110211682 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1107 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 141703595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.667290 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.042913 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 29227228 20.53% 20.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 20574959 14.45% 34.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 20845821 14.64% 49.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18255784 12.82% 62.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 24133952 16.95% 79.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16055098 11.28% 90.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9008550 6.33% 97.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 3309478 2.32% 99.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 936603 0.66% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 28741246 20.28% 20.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 20522205 14.48% 34.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 20900588 14.75% 49.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18202387 12.85% 62.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 24092550 17.00% 79.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15957128 11.26% 90.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9055746 6.39% 97.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 3310234 2.34% 99.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 921511 0.65% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 142347473 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 141703595 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9705 0.05% 0.05% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4696 0.03% 0.08% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9264 0.05% 0.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4697 0.03% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.08% # attempts to use FU when none available @@ -189,201 +189,201 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.08% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.08% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.08% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 48154 0.27% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.35% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 7801 0.04% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 391 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 194497 1.08% 1.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 4577 0.03% 1.50% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 241305 1.34% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9433836 52.57% 55.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 7998969 44.58% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 45902 0.26% 0.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 7808 0.04% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 380 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 3 0.00% 0.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 193577 1.08% 1.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 5090 0.03% 1.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 240664 1.34% 2.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9480378 52.69% 55.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 8006063 44.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 128679498 33.99% 33.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2178469 0.58% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 3 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.57% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6838580 1.81% 36.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8699925 2.30% 38.67% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3453303 0.91% 39.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1605459 0.42% 40.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 21250786 5.61% 45.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7183426 1.90% 47.52% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7137674 1.89% 49.41% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.45% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 102689873 27.13% 76.58% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 88663438 23.42% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 128177934 33.91% 33.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2174662 0.58% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 34.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6842006 1.81% 36.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 36.30% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8692020 2.30% 38.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3461453 0.92% 39.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1621602 0.43% 39.94% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 21340607 5.65% 45.59% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7172753 1.90% 47.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7136617 1.89% 49.37% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175287 0.05% 49.42% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 102440165 27.10% 76.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 88729478 23.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 378555721 # Type of FU issued -system.cpu.iq.rate 2.657302 # Inst issue rate -system.cpu.iq.fu_busy_cnt 17943934 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.047401 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 668132849 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 303460922 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 252722845 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 250633581 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 132457901 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 118739342 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 267290872 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 129208783 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10791540 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 377964584 # Type of FU issued +system.cpu.iq.rate 2.665202 # Inst issue rate +system.cpu.iq.fu_busy_cnt 17993826 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.047607 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 665793984 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 301139104 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 252255785 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 251235002 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 132745901 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 118864658 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266433376 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 129525034 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 10838927 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11186447 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 112704 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14184 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 10853987 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 10853359 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 121041 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14368 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 10831289 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 9836 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 124 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 20682 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 118 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6394548 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 40816 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2257 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 393044352 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1233465 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 105837544 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 93231927 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 19117 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 279 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 239 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14184 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1686736 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 558131 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 2244867 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 373775544 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 101165584 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 4780177 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 6207846 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 63522 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8302 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 391975437 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1065471 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 105504454 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 93209227 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 14418 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 255 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 232 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14368 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1674842 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 501476 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 2176318 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 373329400 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 101074307 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 4635184 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 49432 # number of nop insts executed -system.cpu.iew.exec_refs 188551589 # number of memory reference insts executed -system.cpu.iew.exec_branches 32411941 # Number of branches executed -system.cpu.iew.exec_stores 87386005 # Number of stores executed -system.cpu.iew.exec_rate 2.623747 # Inst execution rate -system.cpu.iew.wb_sent 372264339 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 371462187 # cumulative count of insts written-back -system.cpu.iew.wb_producers 184812981 # num instructions producing a value -system.cpu.iew.wb_consumers 367833213 # num instructions consuming a value +system.cpu.iew.exec_nop 9589 # number of nop insts executed +system.cpu.iew.exec_refs 188479981 # number of memory reference insts executed +system.cpu.iew.exec_branches 38700000 # Number of branches executed +system.cpu.iew.exec_stores 87405674 # Number of stores executed +system.cpu.iew.exec_rate 2.632517 # Inst execution rate +system.cpu.iew.wb_sent 371919298 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 371120443 # cumulative count of insts written-back +system.cpu.iew.wb_producers 184768812 # num instructions producing a value +system.cpu.iew.wb_consumers 367722333 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.607508 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.502437 # average fanout of values written-back +system.cpu.iew.wb_rate 2.616941 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.502468 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 43967644 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 24482 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 2096481 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 135952926 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.567630 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.653370 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 42898696 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 24480 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 2031740 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 135495750 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.576293 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.655015 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 38639864 28.42% 28.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 29020043 21.35% 49.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13541053 9.96% 59.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11234412 8.26% 67.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 13804382 10.15% 78.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7226420 5.32% 83.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4033022 2.97% 86.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3906183 2.87% 89.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 14547547 10.70% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 38151746 28.16% 28.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 29172803 21.53% 49.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13488501 9.95% 59.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11127648 8.21% 67.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 13794811 10.18% 78.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7272808 5.37% 83.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 3959931 2.92% 86.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3978843 2.94% 89.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 14548659 10.74% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 135952926 # Number of insts commited each cycle -system.cpu.commit.committedInsts 273049078 # Number of instructions committed -system.cpu.commit.committedOps 349076802 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 135495750 # Number of insts commited each cycle +system.cpu.commit.committedInsts 273049068 # Number of instructions committed +system.cpu.commit.committedOps 349076792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 177029037 # Number of memory references committed -system.cpu.commit.loads 94651097 # Number of loads committed +system.cpu.commit.refs 177029033 # Number of memory references committed +system.cpu.commit.loads 94651095 # Number of loads committed system.cpu.commit.membars 11033 # Number of memory barriers committed -system.cpu.commit.branches 30523992 # Number of branches committed +system.cpu.commit.branches 36549058 # Number of branches committed system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions. -system.cpu.commit.int_insts 279594003 # Number of committed integer instructions. +system.cpu.commit.int_insts 279593995 # Number of committed integer instructions. system.cpu.commit.function_calls 6225112 # Number of function calls committed. -system.cpu.commit.bw_lim_events 14547547 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 14548659 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 514447302 # The number of ROB reads -system.cpu.rob.rob_writes 792488332 # The number of ROB writes -system.cpu.timesIdled 3380 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 111196 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 273048466 # Number of Instructions Simulated -system.cpu.committedOps 349076190 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 273048466 # Number of Instructions Simulated -system.cpu.cpi 0.521734 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.521734 # CPI: Total CPI of All Threads -system.cpu.ipc 1.916686 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.916686 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1784924885 # number of integer regfile reads -system.cpu.int_regfile_writes 236340288 # number of integer regfile writes -system.cpu.fp_regfile_reads 189697402 # number of floating regfile reads -system.cpu.fp_regfile_writes 133438574 # number of floating regfile writes -system.cpu.misc_regfile_reads 991950959 # number of misc regfile reads -system.cpu.misc_regfile_writes 34426479 # number of misc regfile writes -system.cpu.icache.replacements 14092 # number of replacements -system.cpu.icache.tagsinuse 1857.122291 # Cycle average of tags in use -system.cpu.icache.total_refs 39554212 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 15988 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2473.993745 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 512920056 # The number of ROB reads +system.cpu.rob.rob_writes 790163258 # The number of ROB writes +system.cpu.timesIdled 3290 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 111013 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 273048456 # Number of Instructions Simulated +system.cpu.committedOps 349076180 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 273048456 # Number of Instructions Simulated +system.cpu.cpi 0.519375 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.519375 # CPI: Total CPI of All Threads +system.cpu.ipc 1.925390 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.925390 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1783222925 # number of integer regfile reads +system.cpu.int_regfile_writes 236048544 # number of integer regfile writes +system.cpu.fp_regfile_reads 189858898 # number of floating regfile reads +system.cpu.fp_regfile_writes 133648833 # number of floating regfile writes +system.cpu.misc_regfile_reads 990710631 # number of misc regfile reads +system.cpu.misc_regfile_writes 34426475 # number of misc regfile writes +system.cpu.icache.replacements 13954 # number of replacements +system.cpu.icache.tagsinuse 1852.950065 # Cycle average of tags in use +system.cpu.icache.total_refs 39375254 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 15846 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 2484.870251 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1857.122291 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.906798 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.906798 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 39554212 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 39554212 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 39554212 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 39554212 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 39554212 # number of overall hits -system.cpu.icache.overall_hits::total 39554212 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 16738 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 16738 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 16738 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 16738 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 16738 # number of overall misses -system.cpu.icache.overall_misses::total 16738 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 211077500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 211077500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 211077500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 211077500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 211077500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 211077500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 39570950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 39570950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 39570950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 39570950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 39570950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 39570950 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000423 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000423 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000423 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000423 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000423 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000423 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12610.676305 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12610.676305 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12610.676305 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12610.676305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12610.676305 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12610.676305 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1852.950065 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.904761 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.904761 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 39375254 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 39375254 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 39375254 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 39375254 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 39375254 # number of overall hits +system.cpu.icache.overall_hits::total 39375254 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 16622 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 16622 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 16622 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 16622 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 16622 # number of overall misses +system.cpu.icache.overall_misses::total 16622 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 210340000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 210340000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 210340000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 210340000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 210340000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 210340000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 39391876 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 39391876 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 39391876 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 39391876 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 39391876 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 39391876 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000422 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000422 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000422 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000422 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000422 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000422 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12654.313560 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12654.313560 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12654.313560 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12654.313560 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12654.313560 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12654.313560 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -392,90 +392,90 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 750 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 750 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 750 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 750 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 750 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 750 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15988 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15988 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15988 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15988 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15988 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15988 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 140340000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 140340000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 140340000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 140340000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 140340000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 140340000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000404 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000404 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000404 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000404 # 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number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 138958000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 138958000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 138958000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000402 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000402 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000402 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000402 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8768.725942 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8768.725942 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8768.725942 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8768.725942 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8768.725942 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8768.725942 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1419 # number of replacements -system.cpu.dcache.tagsinuse 3123.008839 # Cycle average of tags in use -system.cpu.dcache.total_refs 172229353 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 4629 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37206.600346 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1429 # number of replacements +system.cpu.dcache.tagsinuse 3114.485618 # Cycle average of tags in use +system.cpu.dcache.total_refs 172071632 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 4623 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37220.772658 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 3123.008839 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.762453 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.762453 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 90171250 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 90171250 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82031303 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82031303 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 13543 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 13543 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 13257 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 13257 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 172202553 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 172202553 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 172202553 # number of overall hits -system.cpu.dcache.overall_hits::total 172202553 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3872 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3872 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 21357 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 21357 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 3114.485618 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.760372 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.760372 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 90013475 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 90013475 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82031354 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82031354 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 13548 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 13548 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 13255 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 13255 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 172044829 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 172044829 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 172044829 # number of overall hits +system.cpu.dcache.overall_hits::total 172044829 # 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number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 828692500 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 25188 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 25188 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 25188 # number of overall misses +system.cpu.dcache.overall_misses::total 25188 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 139835000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 139835000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 825940000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 825940000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 968625000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 968625000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 968625000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 968625000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90175122 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90175122 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 965775000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 965775000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 965775000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 965775000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90017357 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90017357 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052660 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052660 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13545 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 13545 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 13257 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 13257 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 172227782 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 172227782 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 172227782 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 172227782 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13550 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 13550 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 13255 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 13255 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 172070017 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 172070017 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 172070017 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 172070017 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000043 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000043 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000260 # miss rate for WriteReq accesses @@ -486,52 +486,52 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000146 system.cpu.dcache.demand_miss_rate::total 0.000146 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000146 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000146 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36139.591942 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36139.591942 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38801.915063 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38801.915063 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36021.380732 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36021.380732 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38765.605933 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38765.605933 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38393.317214 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38393.317214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38393.317214 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38393.317214 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38342.663173 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38342.663173 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38342.663173 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38342.663173 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 334500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 306000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 12 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 27875 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 25500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1036 # number of writebacks -system.cpu.dcache.writebacks::total 1036 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2060 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2060 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18540 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18540 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 1044 # number of writebacks +system.cpu.dcache.writebacks::total 1044 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2066 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2066 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18499 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18499 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 20600 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 20600 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 20600 # 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number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95488500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 98125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145839000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 243964000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 98125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145839000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 243964000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191268 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.811706 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.254396 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993612 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993612 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191268 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922445 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.355435 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191268 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922445 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.355435 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32087.965991 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34252.040816 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32790.525618 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34103.035714 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34103.035714 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32087.965991 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34154.332553 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33292.030568 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32087.965991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34154.332553 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33292.030568 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 18 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 38 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 18 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 38 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 18 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 38 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 56 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3042 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1466 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4508 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2791 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 2791 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3042 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 4257 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7299 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3042 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 4257 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7299 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97581500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 50217500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 147799000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95213500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95213500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97581500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145431000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 243012500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97581500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145431000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 243012500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.191961 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.808159 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.255252 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993592 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993592 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.191961 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.920831 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.356571 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.191961 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.920831 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.356571 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32078.073636 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34254.774898 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32785.936114 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34114.475099 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34114.475099 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32078.073636 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 34162.790698 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33293.944376 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32078.073636 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 34162.790698 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33293.944376 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 8af4db376..26e87cc9e 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 0dc5c6cdd..64d803bbc 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:54:17 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:08:07 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 4a3f2e632..4b5d20337 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.212344 # Nu sim_ticks 212344043000 # Number of ticks simulated final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2237295 # Simulator instruction rate (inst/s) -host_op_rate 2860273 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1739965936 # Simulator tick rate (ticks/s) -host_mem_usage 232696 # Number of bytes of host memory used -host_seconds 122.04 # Real time elapsed on the host +host_inst_rate 1672295 # Simulator instruction rate (inst/s) +host_op_rate 2137948 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1300559764 # Simulator tick rate (ticks/s) +host_mem_usage 226736 # Number of bytes of host memory used +host_seconds 163.27 # Real time elapsed on the host sim_insts 273037663 # Number of instructions simulated sim_ops 349065399 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 349065399 # Nu system.cpu.num_int_alu_accesses 279584918 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18087061 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 18105897 # number of instructions that are conditional controls system.cpu.num_int_insts 279584918 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_int_register_reads 1887652153 # number of times the integer registers were read diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index 0fa8c3883..d9e3f9f38 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,12 +182,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index 091d7545a..38cd602c6 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 16:02:17 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 13:57:28 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 3487a1e4f..7b678cb0b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.525920 # Nu sim_ticks 525920061000 # Number of ticks simulated final_tick 525920061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 966127 # Simulator instruction rate (inst/s) -host_op_rate 1235157 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1862970627 # Simulator tick rate (ticks/s) -host_mem_usage 241076 # Number of bytes of host memory used -host_seconds 282.30 # Real time elapsed on the host +host_inst_rate 787177 # Simulator instruction rate (inst/s) +host_op_rate 1006377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1517904458 # Simulator tick rate (ticks/s) +host_mem_usage 235608 # Number of bytes of host memory used +host_seconds 346.48 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory @@ -78,7 +78,7 @@ system.cpu.committedOps 348687122 # Nu system.cpu.num_int_alu_accesses 279584917 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses system.cpu.num_func_calls 12448615 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18087060 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 18105896 # number of instructions that are conditional controls system.cpu.num_int_insts 279584917 # number of integer instructions system.cpu.num_fp_insts 114216705 # number of float instructions system.cpu.num_int_register_reads 2212913168 # number of times the integer registers were read diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index 69901d605..39878e8d2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,12 +513,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index bf499b85a..278fe40f3 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 16:07:10 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:46:31 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 735462942500 because target called exit() +Exiting @ tick 653190727500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 6cef7cd16..b1563a03b 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.737495 # Number of seconds simulated -sim_ticks 737494828500 # Number of ticks simulated -final_tick 737494828500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.653191 # Number of seconds simulated +sim_ticks 653190727500 # Number of ticks simulated +final_tick 653190727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 117861 # Simulator instruction rate (inst/s) -host_op_rate 160511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62787760 # Simulator tick rate (ticks/s) -host_mem_usage 243784 # Number of bytes of host memory used -host_seconds 11745.84 # Real time elapsed on the host -sim_insts 1384378545 # Number of instructions simulated -sim_ops 1885333297 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 209536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 94516480 # Number of bytes read from this memory -system.physmem.bytes_read::total 94726016 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 209536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 209536 # Number of instructions bytes read from this memory +host_inst_rate 90710 # Simulator instruction rate (inst/s) +host_op_rate 123535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 42799734 # Simulator tick rate (ticks/s) +host_mem_usage 235092 # Number of bytes of host memory used +host_seconds 15261.56 # Real time elapsed on the host +sim_insts 1384379220 # Number of instructions simulated +sim_ops 1885333972 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 203328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 94517952 # Number of bytes read from this memory +system.physmem.bytes_read::total 94721280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 203328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 203328 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230336 # Number of bytes written to this memory system.physmem.bytes_written::total 4230336 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3274 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1476820 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1480094 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 3177 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1476843 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1480020 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66099 # Number of write requests responded to by this memory system.physmem.num_writes::total 66099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 284119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 128158838 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 128442956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 284119 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 284119 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 5736089 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 5736089 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 5736089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 284119 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 128158838 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 134179045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 311284 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 144701919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 145013204 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 311284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 311284 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 6476418 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6476418 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 6476418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 311284 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 144701919 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 151489621 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,320 +77,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1411 # Number of system calls -system.cpu.numCycles 1474989658 # number of cpu cycles simulated +system.cpu.numCycles 1306381456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 524417855 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 399374260 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 35885746 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 373085909 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 286974367 # Number of BTB hits +system.cpu.BPredUnit.lookups 451886525 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 356592173 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 33205003 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 281633187 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 237475635 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 58521049 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 2814397 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 448543327 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2629766387 # Number of instructions fetch has processed -system.cpu.fetch.Branches 524417855 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 345495416 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 712413372 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 224871613 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 101150257 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2305 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 27764 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 417868916 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 11061583 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1445533834 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.549178 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.166303 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 53725762 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 2808142 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 371691213 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2329385713 # Number of instructions fetch has processed +system.cpu.fetch.Branches 451886525 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 291201397 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 621090552 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 170450530 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 138693587 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 29461 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 349470928 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 11301689 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1268700671 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.542231 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.167897 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 733184926 50.72% 50.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 55708468 3.85% 54.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 112020823 7.75% 62.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 70937824 4.91% 67.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 82697525 5.72% 72.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 53946539 3.73% 76.68% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 34097920 2.36% 79.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36269848 2.51% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 266669961 18.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 647656502 51.05% 51.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 44886599 3.54% 54.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 100617653 7.93% 62.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 60404416 4.76% 67.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 73875113 5.82% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 44960792 3.54% 76.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 31035484 2.45% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 30635125 2.41% 81.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 234628987 18.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1445533834 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.355540 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.782905 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 495848393 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 80424598 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 675057973 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 10827570 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 183375300 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 81502199 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 23236 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3555990026 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 53741 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 183375300 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 535002639 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 31838463 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 561864 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 645033334 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 49722234 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3433849661 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 240 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 4442600 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 40377333 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 1619 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 3343633011 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 16242490520 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 15601606149 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 640884371 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1993152818 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1350480193 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 55128 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 50419 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 136573484 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1056851261 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 578467186 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 33770671 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 40675012 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 3200649154 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 58384 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2726502260 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 25388775 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1314914344 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3030342592 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 35409 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1445533834 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.886156 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.918040 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1268700671 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.345907 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.783082 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 423570129 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 110130146 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 579255946 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 18563929 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 137180521 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 50568077 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 14826 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3119517279 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 28937 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 137180521 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 460603750 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 40419610 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 499687 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 558753819 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 71243284 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3033648086 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 193 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 4887381 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56133943 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 1685 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2996122982 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 14446186472 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13843342856 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 602843616 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1993153898 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 1002969084 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 28984 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 24876 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 185421286 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 977548256 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 509159433 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 36902722 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 39166460 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2862588309 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 35911 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2484024411 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13118317 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 964784903 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2432051802 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12801 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1268700671 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.957928 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.885204 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 525278081 36.34% 36.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 201262430 13.92% 50.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 215918123 14.94% 65.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 180162301 12.46% 77.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 154926049 10.72% 88.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 101550700 7.03% 95.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 47554041 3.29% 98.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10922133 0.76% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7959976 0.55% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 413577866 32.60% 32.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 194484687 15.33% 47.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 205713957 16.21% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 171271635 13.50% 77.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 131142170 10.34% 87.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 97400688 7.68% 95.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 37845090 2.98% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 12462379 0.98% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4802199 0.38% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1445533834 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1268700671 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1492509 1.56% 1.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 23896 0.02% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 56884483 59.48% 61.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 37239793 38.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 960888 1.05% 1.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 23894 0.03% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.07% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 55821815 60.83% 61.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 34963808 38.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1265251443 46.41% 46.41% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11240550 0.41% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.82% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.05% 46.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.87% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 6876520 0.25% 47.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 5507594 0.20% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 50 0.00% 47.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23397304 0.86% 48.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 48.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 900321510 33.02% 81.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 512531999 18.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1133289530 45.62% 45.62% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11232040 0.45% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 46.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 1375289 0.06% 46.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 6876506 0.28% 46.41% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 5503108 0.22% 46.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 46.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 23588545 0.95% 47.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.58% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.58% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 841636528 33.88% 81.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 460522863 18.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2726502260 # Type of FU issued -system.cpu.iq.rate 1.848489 # Inst issue rate -system.cpu.iq.fu_busy_cnt 95640681 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.035078 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6886689526 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4415187143 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2498660773 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 132878284 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 100500200 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 59720745 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2753616267 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 68526674 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 71560936 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2484024411 # Type of FU issued +system.cpu.iq.rate 1.901454 # Inst issue rate +system.cpu.iq.fu_busy_cnt 91770405 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.036944 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6213658406 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 3738455000 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2292430207 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 127979809 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 89021624 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 58699426 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2509271154 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 66523662 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 80303664 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 425462489 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 295662 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1252623 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 301470298 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 346159349 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5258 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1403998 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 232162410 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 183375300 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 17460814 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1976242 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3200787719 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6982578 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1056851261 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 578467186 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 47271 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1974574 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 647 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1252623 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 36804150 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 9241017 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 46045167 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2625801566 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 846122172 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 100700694 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 137180521 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 17480517 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1686547 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2862638347 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 10688123 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 977548256 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 509159433 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 24752 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1673918 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2091 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1403998 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 34817527 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1757167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 36574694 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2405136648 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 795998932 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 78887763 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80181 # number of nop insts executed -system.cpu.iew.exec_refs 1330053445 # number of memory reference insts executed -system.cpu.iew.exec_branches 359055744 # Number of branches executed -system.cpu.iew.exec_stores 483931273 # Number of stores executed -system.cpu.iew.exec_rate 1.780217 # Inst execution rate -system.cpu.iew.wb_sent 2586917302 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2558381518 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1475385900 # num instructions producing a value -system.cpu.iew.wb_consumers 2766219416 # num instructions consuming a value +system.cpu.iew.exec_nop 14127 # number of nop insts executed +system.cpu.iew.exec_refs 1234173393 # number of memory reference insts executed +system.cpu.iew.exec_branches 329367580 # Number of branches executed +system.cpu.iew.exec_stores 438174461 # Number of stores executed +system.cpu.iew.exec_rate 1.841068 # Inst execution rate +system.cpu.iew.wb_sent 2376887575 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2351129633 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1360698402 # num instructions producing a value +system.cpu.iew.wb_consumers 2562363668 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.734508 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.533358 # average fanout of values written-back +system.cpu.iew.wb_rate 1.799727 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.531033 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1315443833 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 22975 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 41404056 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1262158536 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.493746 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.206193 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 977293768 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 23110 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 33191422 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1131520152 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.666205 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.368466 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 581725846 46.09% 46.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 316852279 25.10% 71.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 102044776 8.08% 79.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 79824424 6.32% 85.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 53115957 4.21% 89.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 24396464 1.93% 91.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 17091653 1.35% 93.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8923952 0.71% 93.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 78183185 6.19% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 484597847 42.83% 42.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 298921465 26.42% 69.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 90821305 8.03% 77.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 72269012 6.39% 83.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 45034307 3.98% 87.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 23256378 2.06% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 15793077 1.40% 91.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 9817791 0.87% 91.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 91008970 8.04% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1262158536 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1384389561 # Number of instructions committed -system.cpu.commit.committedOps 1885344313 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1131520152 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1384390236 # Number of instructions committed +system.cpu.commit.committedOps 1885344988 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 908385660 # Number of memory references committed -system.cpu.commit.loads 631388772 # Number of loads committed +system.cpu.commit.refs 908385930 # Number of memory references committed +system.cpu.commit.loads 631388907 # Number of loads committed system.cpu.commit.membars 9986 # Number of memory barriers committed -system.cpu.commit.branches 291350135 # Number of branches committed +system.cpu.commit.branches 299636121 # Number of branches committed system.cpu.commit.fp_insts 52289415 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1653705231 # Number of committed integer instructions. +system.cpu.commit.int_insts 1653705771 # Number of committed integer instructions. system.cpu.commit.function_calls 41577833 # Number of function calls committed. -system.cpu.commit.bw_lim_events 78183185 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 91008970 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 4384745152 # The number of ROB reads -system.cpu.rob.rob_writes 6584968170 # The number of ROB writes -system.cpu.timesIdled 1343543 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29455824 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1384378545 # Number of Instructions Simulated -system.cpu.committedOps 1885333297 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1384378545 # Number of Instructions Simulated -system.cpu.cpi 1.065453 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.065453 # CPI: Total CPI of All Threads -system.cpu.ipc 0.938568 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.938568 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12950426831 # number of integer regfile reads -system.cpu.int_regfile_writes 2427369394 # number of integer regfile writes -system.cpu.fp_regfile_reads 71525918 # number of floating regfile reads -system.cpu.fp_regfile_writes 50683175 # number of floating regfile writes -system.cpu.misc_regfile_reads 4109052133 # number of misc regfile reads -system.cpu.misc_regfile_writes 13776084 # number of misc regfile writes -system.cpu.icache.replacements 27555 # number of replacements -system.cpu.icache.tagsinuse 1659.051734 # Cycle average of tags in use -system.cpu.icache.total_refs 417829104 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 29252 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14283.779024 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 3903131593 # The number of ROB reads +system.cpu.rob.rob_writes 5862472148 # The number of ROB writes +system.cpu.timesIdled 1341228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 37680785 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1384379220 # Number of Instructions Simulated +system.cpu.committedOps 1885333972 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1384379220 # Number of Instructions Simulated +system.cpu.cpi 0.943659 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.943659 # CPI: Total CPI of All Threads +system.cpu.ipc 1.059705 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.059705 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 11952036932 # number of integer regfile reads +system.cpu.int_regfile_writes 2256711080 # number of integer regfile writes +system.cpu.fp_regfile_reads 70681119 # number of floating regfile reads +system.cpu.fp_regfile_writes 50325350 # number of floating regfile writes +system.cpu.misc_regfile_reads 3723531681 # number of misc regfile reads +system.cpu.misc_regfile_writes 13776354 # number of misc regfile writes +system.cpu.icache.replacements 23459 # number of replacements +system.cpu.icache.tagsinuse 1656.238339 # Cycle average of tags in use +system.cpu.icache.total_refs 349436364 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 25154 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 13891.880576 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1659.051734 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.810084 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.810084 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 417833790 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 417833790 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 417833790 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 417833790 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 417833790 # number of overall hits -system.cpu.icache.overall_hits::total 417833790 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 35126 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 35126 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 35126 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 35126 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 35126 # number of overall misses -system.cpu.icache.overall_misses::total 35126 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 348458500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 348458500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 348458500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 348458500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 348458500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 348458500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 417868916 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 417868916 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 417868916 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 417868916 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 417868916 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 417868916 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000084 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000084 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000084 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9920.244264 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 9920.244264 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 9920.244264 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9920.244264 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 9920.244264 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1656.238339 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.808710 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.808710 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 349440471 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 349440471 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 349440471 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 349440471 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 349440471 # number of overall hits +system.cpu.icache.overall_hits::total 349440471 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 30457 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 30457 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 30457 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 30457 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 30457 # number of overall misses +system.cpu.icache.overall_misses::total 30457 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 315232000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 315232000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 315232000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 315232000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 315232000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 315232000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 349470928 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 349470928 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 349470928 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 349470928 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 349470928 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 349470928 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10350.067308 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10350.067308 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10350.067308 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10350.067308 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10350.067308 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10350.067308 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,110 +399,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 940 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 940 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 940 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 940 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 940 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 940 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 34186 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 34186 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 34186 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 34186 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 34186 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 34186 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 218551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 218551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218551000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 218551000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000082 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000082 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000082 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6392.997133 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6392.997133 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6392.997133 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6392.997133 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 916 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 916 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 916 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 916 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 916 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 916 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 29541 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 29541 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 29541 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 29541 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 29541 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 29541 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 200922000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 200922000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 200922000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 200922000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 200922000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 200922000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000085 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000085 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000085 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000085 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6801.462374 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6801.462374 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6801.462374 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 6801.462374 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6801.462374 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 6801.462374 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1533020 # number of replacements -system.cpu.dcache.tagsinuse 4094.909429 # Cycle average of tags in use -system.cpu.dcache.total_refs 1033013851 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1537116 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 672.046775 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 306710000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4094.909429 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.999734 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.999734 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 756858216 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 756858216 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 276115103 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 276115103 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 11921 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 11921 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 11576 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 11576 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1032973319 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1032973319 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1032973319 # number of overall hits -system.cpu.dcache.overall_hits::total 1032973319 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2483728 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2483728 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 820575 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 820575 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3304303 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3304303 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3304303 # number of overall misses -system.cpu.dcache.overall_misses::total 3304303 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 90046240500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 90046240500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 33963890000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 33963890000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 140000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 140000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 124010130500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 124010130500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 124010130500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 124010130500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 759341944 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 759341944 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.replacements 1533244 # number of replacements +system.cpu.dcache.tagsinuse 4094.802366 # Cycle average of tags in use +system.cpu.dcache.total_refs 977260435 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1537340 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 635.682695 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 300664000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4094.802366 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.999708 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 701107300 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 701107300 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 276115713 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 276115713 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 12426 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 12426 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11711 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11711 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 977223013 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 977223013 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 977223013 # number of overall hits +system.cpu.dcache.overall_hits::total 977223013 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2133926 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2133926 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 819965 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 819965 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2953891 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2953891 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2953891 # number of overall misses +system.cpu.dcache.overall_misses::total 2953891 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 80611211500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 80611211500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 33925562500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 33925562500 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 304000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 304000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 114536774000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 114536774000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 114536774000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 114536774000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 703241226 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 703241226 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 276935678 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 276935678 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11925 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 11925 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 11576 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 11576 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1036277622 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1036277622 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1036277622 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1036277622 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003271 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003271 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002963 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002963 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000335 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000335 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.003189 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.003189 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.003189 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.003189 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36254.469290 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36254.469290 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41390.354325 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41390.354325 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 35000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 35000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37529.890721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37529.890721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37529.890721 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12437 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 12437 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11711 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11711 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 980176904 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 980176904 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 980176904 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 980176904 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003034 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003034 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002961 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002961 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000884 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000884 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.003014 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.003014 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.003014 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.003014 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37776.010743 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 37776.010743 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41374.403176 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41374.403176 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 27636.363636 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 27636.363636 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 38774.881673 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 38774.881673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 38774.881673 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 38774.881673 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 58500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -511,142 +511,142 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 108316 # number of writebacks -system.cpu.dcache.writebacks::total 108316 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1019154 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1019154 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743098 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 743098 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1762252 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1762252 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1762252 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1762252 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464574 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1464574 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 77477 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 77477 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1542051 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1542051 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1542051 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1542051 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50338229502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 50338229502 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2525857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2525857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52864087002 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 52864087002 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52864087002 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 52864087002 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001929 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001929 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000280 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000280 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.001488 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001488 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.001488 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34370.560656 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34370.560656 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32601.384927 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32601.384927 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34281.672268 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34281.672268 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 108418 # number of writebacks +system.cpu.dcache.writebacks::total 108418 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 669125 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 669125 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 743038 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 743038 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 11 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 11 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1412163 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1412163 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1412163 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1412163 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1464801 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1464801 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76927 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76927 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1541728 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1541728 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1541728 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1541728 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 50340349002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 50340349002 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2506118000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2506118000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 52846467002 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 52846467002 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 52846467002 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 52846467002 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002083 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002083 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000278 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.001573 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001573 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.001573 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34366.681209 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 34366.681209 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32577.872529 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32577.872529 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34277.425721 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 34277.425721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34277.425721 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 34277.425721 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 1480259 # number of replacements -system.cpu.l2cache.tagsinuse 32698.440647 # Cycle average of tags in use -system.cpu.l2cache.total_refs 88180 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 1513003 # 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number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46383239000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963243 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.946572 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999392 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999392 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910922 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910922 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.944921 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111924 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960773 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.944921 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32293.219304 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.167012 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.348237 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31000 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.381199 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.381199 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32293.219304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31335.918392 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.035963 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3177 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410766 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1413943 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4385 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 4385 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66077 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66077 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3177 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1476843 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1480020 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3177 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1476843 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1480020 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 102667500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44229330500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 44331998000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 135941000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 135941000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2049093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2049093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 102667500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 46278424000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 46381091500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 102667500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 46278424000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 46381091500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.126302 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.963112 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.948984 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999316 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.999316 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910904 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910904 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.126302 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.960648 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.947216 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.126302 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.960648 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.947216 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32315.864023 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31351.287527 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31353.454842 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31001.368301 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31001.368301 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31010.692071 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31010.692071 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32315.864023 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31336.048585 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31338.151849 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32315.864023 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31336.048585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31338.151849 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index c9a1801d2..6368ff37d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index d3221b5d3..303ba43b2 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:03:08 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:53:48 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 088f25fd3..72c04a2c0 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.945613 # Nu sim_ticks 945613126000 # Number of ticks simulated final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2568124 # Simulator instruction rate (inst/s) -host_op_rate 3497430 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1754178123 # Simulator tick rate (ticks/s) -host_mem_usage 233172 # Number of bytes of host memory used -host_seconds 539.06 # Real time elapsed on the host +host_inst_rate 1877363 # Simulator instruction rate (inst/s) +host_op_rate 2556708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1282347761 # Simulator tick rate (ticks/s) +host_mem_usage 223904 # Number of bytes of host memory used +host_seconds 737.41 # Real time elapsed on the host sim_insts 1384381606 # Number of instructions simulated sim_ops 1885336358 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 1885336358 # Nu system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_func_calls 80372855 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223735905 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_int_register_reads 8601515912 # number of times the integer registers were read diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index 350b3e880..2fc919fb9 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,12 +182,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 2b2490099..eb0b38c6c 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 16:24:15 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:04:21 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 8787dc4d5..06a14cc7a 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.369932 # Nu sim_ticks 2369931974000 # Number of ticks simulated final_tick 2369931974000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1141587 # Simulator instruction rate (inst/s) -host_op_rate 1548644 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1958218374 # Simulator tick rate (ticks/s) -host_mem_usage 241676 # Number of bytes of host memory used -host_seconds 1210.25 # Real time elapsed on the host +host_inst_rate 844398 # Simulator instruction rate (inst/s) +host_op_rate 1145486 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1448435887 # Simulator tick rate (ticks/s) +host_mem_usage 232760 # Number of bytes of host memory used +host_seconds 1636.20 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 144448 # Number of bytes read from this memory @@ -85,7 +85,7 @@ system.cpu.committedOps 1874244941 # Nu system.cpu.num_int_alu_accesses 1653698868 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses system.cpu.num_func_calls 80372855 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 223735905 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 230619738 # number of instructions that are conditional controls system.cpu.num_int_insts 1653698868 # number of integer instructions system.cpu.num_fp_insts 52289415 # number of float instructions system.cpu.num_int_register_reads 10466679913 # number of times the integer registers were read diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 0878a1dc0..b2095b317 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,12 +513,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index c4aefb2c9..726190563 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 16:29:16 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:57:39 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24460150500 because target called exit() +Exiting @ tick 24260940500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index bc1c3c499..fdf8f5a60 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.024450 # Number of seconds simulated -sim_ticks 24450292500 # Number of ticks simulated -final_tick 24450292500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.024261 # Number of seconds simulated +sim_ticks 24260940500 # Number of ticks simulated +final_tick 24260940500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166577 # Simulator instruction rate (inst/s) -host_op_rate 236377 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57425524 # Simulator tick rate (ticks/s) -host_mem_usage 242552 # Number of bytes of host memory used -host_seconds 425.77 # Real time elapsed on the host -sim_insts 70924074 # Number of instructions simulated -sim_ops 100643321 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 328512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8029568 # Number of bytes read from this memory -system.physmem.bytes_read::total 8358080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 328512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 328512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5417984 # Number of bytes written to this memory -system.physmem.bytes_written::total 5417984 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5133 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125462 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130595 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 84656 # Number of write requests responded to by this memory -system.physmem.num_writes::total 84656 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13435913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 328403760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 341839673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 13435913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 13435913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 221591787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 221591787 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 221591787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13435913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 328403760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 563431460 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 115016 # Simulator instruction rate (inst/s) +host_op_rate 163211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39343372 # Simulator tick rate (ticks/s) +host_mem_usage 237732 # Number of bytes of host memory used +host_seconds 616.65 # Real time elapsed on the host +sim_insts 70924159 # Number of instructions simulated +sim_ops 100643406 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 327680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 8028032 # Number of bytes read from this memory +system.physmem.bytes_read::total 8355712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 327680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 327680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5417600 # Number of bytes written to this memory +system.physmem.bytes_written::total 5417600 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 5120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 125438 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130558 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 84650 # Number of write requests responded to by this memory +system.physmem.num_writes::total 84650 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13506484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330903577 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 344410061 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 13506484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 13506484 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 223305440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 223305440 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 223305440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13506484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330903577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 567715501 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,143 +77,143 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 48900586 # number of cpu cycles simulated +system.cpu.numCycles 48521882 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 16947895 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 12979317 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 657239 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 11568375 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7965689 # Number of BTB hits +system.cpu.BPredUnit.lookups 16966170 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 12979168 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 675165 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 11674119 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7996673 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1878366 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 114401 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 12822432 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 87522774 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16947895 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9844055 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 21770954 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2772902 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 11003856 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 41 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 471 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 12059223 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 218909 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 47624951 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582857 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.336628 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1849293 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 114426 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 12701255 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 86893403 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16966170 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9845966 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 21627617 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2635386 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 10974011 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 38 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 407 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 11950097 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 196542 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 47237958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.575337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.329156 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 25875265 54.33% 54.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2171829 4.56% 58.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 2001256 4.20% 63.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2024856 4.25% 67.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 1547627 3.25% 70.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1411228 2.96% 73.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 995461 2.09% 75.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1239299 2.60% 78.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 10358130 21.75% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 25631712 54.26% 54.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2165185 4.58% 58.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 2027432 4.29% 63.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2093511 4.43% 67.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 1492717 3.16% 70.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1413949 2.99% 73.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 984209 2.08% 75.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1226744 2.60% 78.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 10202499 21.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 47624951 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346579 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.789810 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15015037 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9311189 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19956662 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1421851 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1920212 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3461414 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 109087 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 120161085 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 377153 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1920212 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 16781785 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2961677 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 806772 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 19529075 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5625430 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 117632333 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 86 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12238 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4786667 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 232 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 117758479 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 541753123 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 541746251 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 6872 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 99158984 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 18599495 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37350 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37333 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13184553 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 30073818 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 22775187 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3642294 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4290989 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 113312109 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51967 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 108452712 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 348423 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 12547190 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 29979206 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14892 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 47624951 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.277225 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.996410 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 47237958 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.349660 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.790809 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 14870883 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9280138 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19842641 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1415670 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1828626 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3426061 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 108157 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 118947297 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 370581 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1828626 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 16604946 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2957626 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 761420 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 19440844 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 5644496 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 116783060 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 77 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12596 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4803591 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 254 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 117118920 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 537771429 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537766148 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 5281 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 99159120 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 17959800 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 25743 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25726 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13145883 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 29944086 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 22669898 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3682577 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 4376453 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112886356 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 41706 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 108196580 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 320650 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 12119727 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 28466628 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4614 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 47237958 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.290458 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.991605 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11905380 25.00% 25.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 8338489 17.51% 42.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7455711 15.66% 58.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7146400 15.01% 73.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 5525482 11.60% 84.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 3896676 8.18% 92.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1895621 3.98% 96.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 884969 1.86% 98.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 576223 1.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11517306 24.38% 24.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 8382479 17.75% 42.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7488515 15.85% 57.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7167095 15.17% 73.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 5452995 11.54% 84.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 3887775 8.23% 92.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1886175 3.99% 96.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 877063 1.86% 98.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 578555 1.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 47624951 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 47237958 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 113237 4.46% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1413224 55.65% 60.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1012935 39.89% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 110786 4.40% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.40% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1390381 55.25% 59.65% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1015261 40.35% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57358153 52.89% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91504 0.08% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57217754 52.88% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91589 0.08% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 207 0.00% 52.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 191 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.97% # Type of FU issued @@ -239,158 +239,158 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.97% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.97% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 29210718 26.93% 79.91% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21792123 20.09% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 29118364 26.91% 79.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21768675 20.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 108452712 # Type of FU issued -system.cpu.iq.rate 2.217820 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2539396 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023415 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 267417480 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 125938241 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 106420258 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 714 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1140 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 175 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 110991749 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 359 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2211393 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 108196580 # Type of FU issued +system.cpu.iq.rate 2.229851 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2516428 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023258 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 266467665 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 125074926 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 106294504 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 794 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 110712739 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 269 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2177452 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2763421 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7106 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 29349 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2216160 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2633672 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7610 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 29131 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2110854 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 50 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 45 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 49 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1920212 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 926920 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 38130 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 113444221 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 341894 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 30073818 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 22775187 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 35362 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2649 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 29349 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 424803 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 263892 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 688695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 107241565 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 28837233 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1211147 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1828626 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 932107 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 39617 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 112937916 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 341621 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 29944086 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 22669898 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 25185 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2553 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3723 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 29131 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 450221 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 202626 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 652847 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 107016957 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 28768203 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1179623 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 80145 # number of nop insts executed -system.cpu.iew.exec_refs 50314250 # number of memory reference insts executed -system.cpu.iew.exec_branches 14661458 # Number of branches executed -system.cpu.iew.exec_stores 21477017 # Number of stores executed -system.cpu.iew.exec_rate 2.193053 # Inst execution rate -system.cpu.iew.wb_sent 106757510 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 106420433 # cumulative count of insts written-back -system.cpu.iew.wb_producers 53411369 # num instructions producing a value -system.cpu.iew.wb_consumers 103767535 # num instructions consuming a value +system.cpu.iew.exec_nop 9854 # number of nop insts executed +system.cpu.iew.exec_refs 50224831 # number of memory reference insts executed +system.cpu.iew.exec_branches 14719282 # Number of branches executed +system.cpu.iew.exec_stores 21456628 # Number of stores executed +system.cpu.iew.exec_rate 2.205540 # Inst execution rate +system.cpu.iew.wb_sent 106535697 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 106294668 # cumulative count of insts written-back +system.cpu.iew.wb_producers 53446146 # num instructions producing a value +system.cpu.iew.wb_consumers 103592779 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.176261 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.514721 # average fanout of values written-back +system.cpu.iew.wb_rate 2.190654 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.515925 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12796121 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 37075 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 612942 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 45704740 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.202154 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.735561 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 12289679 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 37092 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 569161 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 45409333 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.216482 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.738259 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16269057 35.60% 35.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11908776 26.06% 61.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3615674 7.91% 69.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2919531 6.39% 75.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1872792 4.10% 80.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1908851 4.18% 84.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 687748 1.50% 85.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 590243 1.29% 87.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5932068 12.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15949772 35.12% 35.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11950425 26.32% 61.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3594230 7.92% 69.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2920439 6.43% 75.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1880725 4.14% 79.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1913412 4.21% 84.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 683428 1.51% 85.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 576988 1.27% 86.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5939914 13.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 45704740 # Number of insts commited each cycle -system.cpu.commit.committedInsts 70929626 # Number of instructions committed -system.cpu.commit.committedOps 100648873 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 45409333 # Number of insts commited each cycle +system.cpu.commit.committedInsts 70929711 # Number of instructions committed +system.cpu.commit.committedOps 100648958 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 47869424 # Number of memory references committed -system.cpu.commit.loads 27310397 # Number of loads committed +system.cpu.commit.refs 47869458 # Number of memory references committed +system.cpu.commit.loads 27310414 # Number of loads committed system.cpu.commit.membars 15920 # Number of memory barriers committed -system.cpu.commit.branches 13671916 # Number of branches committed +system.cpu.commit.branches 13744811 # Number of branches committed system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. -system.cpu.commit.int_insts 91485935 # Number of committed integer instructions. +system.cpu.commit.int_insts 91486003 # Number of committed integer instructions. system.cpu.commit.function_calls 1679850 # Number of function calls committed. -system.cpu.commit.bw_lim_events 5932068 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5939914 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 153192367 # The number of ROB reads -system.cpu.rob.rob_writes 228820850 # The number of ROB writes -system.cpu.timesIdled 52344 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 1275635 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 70924074 # Number of Instructions Simulated -system.cpu.committedOps 100643321 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 70924074 # Number of Instructions Simulated -system.cpu.cpi 0.689478 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.689478 # CPI: Total CPI of All Threads -system.cpu.ipc 1.450373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.450373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 516213591 # number of integer regfile reads -system.cpu.int_regfile_writes 104366681 # number of integer regfile writes -system.cpu.fp_regfile_reads 794 # number of floating regfile reads -system.cpu.fp_regfile_writes 662 # number of floating regfile writes -system.cpu.misc_regfile_reads 146023696 # number of misc regfile reads -system.cpu.misc_regfile_writes 38418 # number of misc regfile writes -system.cpu.icache.replacements 30034 # number of replacements -system.cpu.icache.tagsinuse 1814.104659 # Cycle average of tags in use -system.cpu.icache.total_refs 12025772 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 32074 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 374.938330 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 152382757 # The number of ROB reads +system.cpu.rob.rob_writes 227716793 # The number of ROB writes +system.cpu.timesIdled 52521 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 1283924 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 70924159 # Number of Instructions Simulated +system.cpu.committedOps 100643406 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 70924159 # Number of Instructions Simulated +system.cpu.cpi 0.684138 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.684138 # CPI: Total CPI of All Threads +system.cpu.ipc 1.461694 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.461694 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 515060291 # number of integer regfile reads +system.cpu.int_regfile_writes 104149739 # number of integer regfile writes +system.cpu.fp_regfile_reads 734 # number of floating regfile reads +system.cpu.fp_regfile_writes 618 # number of floating regfile writes +system.cpu.misc_regfile_reads 145340198 # number of misc regfile reads +system.cpu.misc_regfile_writes 38452 # number of misc regfile writes +system.cpu.icache.replacements 30556 # number of replacements +system.cpu.icache.tagsinuse 1813.467317 # Cycle average of tags in use +system.cpu.icache.total_refs 11916104 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 32594 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 365.591949 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1814.104659 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.885793 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.885793 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 12025773 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 12025773 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 12025773 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 12025773 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 12025773 # number of overall hits -system.cpu.icache.overall_hits::total 12025773 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 33450 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 33450 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 33450 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 33450 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 33450 # number of overall misses -system.cpu.icache.overall_misses::total 33450 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 407167500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 407167500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 407167500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 407167500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 407167500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 407167500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 12059223 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 12059223 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 12059223 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 12059223 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 12059223 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 12059223 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002774 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.002774 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.002774 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.002774 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.002774 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.002774 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12172.421525 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 12172.421525 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 12172.421525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 12172.421525 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 12172.421525 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 1813.467317 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.885482 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.885482 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 11916104 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 11916104 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 11916104 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 11916104 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 11916104 # number of overall hits +system.cpu.icache.overall_hits::total 11916104 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 33993 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 33993 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 33993 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 33993 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 33993 # number of overall misses +system.cpu.icache.overall_misses::total 33993 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 409410000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 409410000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 409410000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 409410000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 409410000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 409410000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11950097 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11950097 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11950097 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11950097 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11950097 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11950097 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002845 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.002845 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.002845 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.002845 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.002845 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.002845 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12043.950225 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 12043.950225 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 12043.950225 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 12043.950225 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 12043.950225 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -399,254 +399,254 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1320 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1320 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1320 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1320 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1320 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1320 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32130 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 32130 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 32130 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 32130 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 32130 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 32130 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 275291000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 275291000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 275291000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 275291000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 275291000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 275291000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002664 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.002664 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002664 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.002664 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8568.036103 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8568.036103 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8568.036103 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8568.036103 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1348 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1348 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1348 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1348 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1348 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1348 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 32645 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002732 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002732 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002732 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.002732 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002732 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.002732 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8441.537755 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8441.537755 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8441.537755 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 8441.537755 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8441.537755 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 8441.537755 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 158627 # number of replacements -system.cpu.dcache.tagsinuse 4071.845451 # Cycle average of tags in use -system.cpu.dcache.total_refs 44602467 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 162723 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 274.100570 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 272454000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4071.845451 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.994103 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.994103 # 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Cycle average of tags in use +system.cpu.dcache.total_refs 44571992 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 162649 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 274.037910 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 270825000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 4072.119478 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.994170 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.994170 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 26246711 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 26246711 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18285374 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18285374 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 20492 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 20492 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 19225 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 19225 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 44532085 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 44532085 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 44532085 # number of overall hits +system.cpu.dcache.overall_hits::total 44532085 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 107182 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 107182 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1564527 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1564527 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 45 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 45 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1671709 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1671709 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1671709 # number of overall misses +system.cpu.dcache.overall_misses::total 1671709 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2591609000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2591609000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 63424341000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 63424341000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 645500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 645500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 66015950000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 66015950000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 66015950000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 66015950000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 26353893 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 26353893 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20429 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 20429 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 19208 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 19208 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 46234184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 46234184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 46234184 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 46234184 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004052 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004052 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078820 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.078820 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002007 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002007 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036153 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036153 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036153 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036153 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24192.212007 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24192.212007 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40524.306312 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 40524.306312 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14292.682927 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14292.682927 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39479.585927 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39479.585927 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39479.585927 # average overall miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 20537 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 20537 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 19225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 19225 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 46203794 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 46203794 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 46203794 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 46203794 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004067 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004067 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.078818 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.078818 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002191 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002191 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036181 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036181 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036181 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036181 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24179.517083 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24179.517083 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40538.987822 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 40538.987822 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14344.444444 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14344.444444 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 39490.096662 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 39490.096662 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 39490.096662 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 39490.096662 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 210000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 209500 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 19090.909091 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19045.454545 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128131 # number of writebacks -system.cpu.dcache.writebacks::total 128131 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51186 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 51186 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457528 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1457528 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 41 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1508714 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1508714 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1508714 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1508714 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55735 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55735 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107045 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107045 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 162780 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 162780 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 162780 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 162780 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 988383500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3842536000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3842536000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4830919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4830919500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4830919500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4830919500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128129 # number of writebacks +system.cpu.dcache.writebacks::total 128129 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 51511 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 51511 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1457497 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1457497 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 45 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1509008 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1509008 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1509008 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1509008 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55671 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55671 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 162701 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 162701 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 162701 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 162701 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 988702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 988702000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3843974500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3843974500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4832676500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4832676500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4832676500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4832676500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002112 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.003521 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003521 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003521 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17733.623396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17733.623396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35896.454762 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35896.454762 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29677.598599 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 29677.598599 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17759.731278 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17759.731278 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35914.925722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35914.925722 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29702.807604 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29702.807604 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29702.807604 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29702.807604 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 98022 # number of replacements -system.cpu.l2cache.tagsinuse 28617.589348 # Cycle average of tags in use -system.cpu.l2cache.total_refs 86966 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 128812 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.675139 # Average number of references to valid blocks. +system.cpu.l2cache.replacements 97977 # number of replacements +system.cpu.l2cache.tagsinuse 28615.045992 # Cycle average of tags in use +system.cpu.l2cache.total_refs 87467 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 128770 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.679250 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 25792.429972 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 1163.052716 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 1662.106660 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.787122 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.035494 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.050723 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.873340 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 26908 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 32482 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 59390 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128131 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128131 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 11 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4712 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4712 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26908 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 37194 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 64102 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26908 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 37194 # number of overall hits -system.cpu.l2cache.overall_hits::total 64102 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5162 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 23218 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 28380 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 46 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 46 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102311 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102311 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5162 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 125529 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 130691 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5162 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 125529 # number of overall misses -system.cpu.l2cache.overall_misses::total 130691 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 181399000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 833610000 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 125438 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 130558 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164141000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 758230000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 922371000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1129000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1129000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3246844000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3246844000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164141000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4005074000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 4169215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164141000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4005074000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 4169215000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.415566 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320094 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.692308 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.692308 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.956118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.956118 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.668712 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.157108 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771219 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.668712 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32058.789062 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32795.415225 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32661.862606 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31361.111111 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 31361.111111 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31732.872026 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31732.872026 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32058.789062 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31928.713787 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31933.814856 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 5344e06dd..04247a7b5 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index 64d9d48cf..4a0327c7e 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:19:28 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 14:04:14 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 875e92986..420bb3f6b 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.053932 # Nu sim_ticks 53932157000 # Number of ticks simulated final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2430593 # Simulator instruction rate (inst/s) -host_op_rate 3449236 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1848555696 # Simulator tick rate (ticks/s) -host_mem_usage 232076 # Number of bytes of host memory used -host_seconds 29.18 # Real time elapsed on the host +host_inst_rate 1829500 # Simulator instruction rate (inst/s) +host_op_rate 2596230 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1391402909 # Simulator tick rate (ticks/s) +host_mem_usage 226332 # Number of bytes of host memory used +host_seconds 38.76 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 100632428 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 100632428 # Nu system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10711742 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_int_register_reads 452177195 # number of times the integer registers were read diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 4c2746778..4b2d5473a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,12 +182,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index 564b30c1c..b57985d9c 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 16:37:12 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:06:20 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 250f6daa7..c163d61b7 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.133513 # Nu sim_ticks 133513136000 # Number of ticks simulated final_tick 133513136000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1170283 # Simulator instruction rate (inst/s) -host_op_rate 1659492 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2220265254 # Simulator tick rate (ticks/s) -host_mem_usage 240448 # Number of bytes of host memory used -host_seconds 60.13 # Real time elapsed on the host +host_inst_rate 903503 # Simulator instruction rate (inst/s) +host_op_rate 1281191 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1714129830 # Simulator tick rate (ticks/s) +host_mem_usage 235208 # Number of bytes of host memory used +host_seconds 77.89 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 273728 # Number of bytes read from this memory @@ -85,7 +85,7 @@ system.cpu.committedOps 99791654 # Nu system.cpu.num_int_alu_accesses 91472780 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 10711742 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 10748863 # number of instructions that are conditional controls system.cpu.num_int_insts 91472780 # number of integer instructions system.cpu.num_fp_insts 56 # number of float instructions system.cpu.num_int_register_reads 533542872 # number of times the integer registers were read diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index cb0b4a9a4..725d1f37b 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,12 +513,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 963dfaf37..434faed57 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 16:38:23 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:45:19 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 479150606000 because target called exit() +Exiting @ tick 479173106500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 7bf311873..14d5fad91 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,39 +1,39 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.479223 # Number of seconds simulated -sim_ticks 479223482000 # Number of ticks simulated -final_tick 479223482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.479173 # Number of seconds simulated +sim_ticks 479173106500 # Number of ticks simulated +final_tick 479173106500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 194014 # Simulator instruction rate (inst/s) -host_op_rate 216437 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60195599 # Simulator tick rate (ticks/s) -host_mem_usage 234776 # Number of bytes of host memory used -host_seconds 7961.11 # Real time elapsed on the host -sim_insts 1544563028 # Number of instructions simulated -sim_ops 1723073840 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 48448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 156331072 # Number of bytes read from this memory -system.physmem.bytes_read::total 156379520 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 48448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 48448 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71949824 # Number of bytes written to this memory -system.physmem.bytes_written::total 71949824 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 757 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2442673 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2443430 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1124216 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1124216 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 101097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 326217470 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 326318567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101097 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 150138352 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 150138352 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 150138352 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101097 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 326217470 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 476456920 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 135351 # Simulator instruction rate (inst/s) +host_op_rate 150994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41990206 # Simulator tick rate (ticks/s) +host_mem_usage 229432 # Number of bytes of host memory used +host_seconds 11411.54 # Real time elapsed on the host +sim_insts 1544563038 # Number of instructions simulated +sim_ops 1723073850 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 48512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 156363136 # Number of bytes read from this memory +system.physmem.bytes_read::total 156411648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 48512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 71949056 # Number of bytes written to this memory +system.physmem.bytes_written::total 71949056 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 758 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2443174 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2443932 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1124204 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1124204 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 101241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 326318681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 326419922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101241 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 150152534 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 150152534 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 150152534 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 326318681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 476572456 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -77,141 +77,141 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 958446965 # number of cpu cycles simulated +system.cpu.numCycles 958346214 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 302424004 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 248121310 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 16111337 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 166375993 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 157791713 # Number of BTB hits +system.cpu.BPredUnit.lookups 302436824 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 248070487 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 16102737 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 165612861 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 157810575 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 18325977 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 236 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 295072409 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2170601008 # Number of instructions fetch has processed -system.cpu.fetch.Branches 302424004 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 176117690 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 431730569 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 85674794 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 155376778 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 18381050 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 257 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 295095953 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2169970618 # Number of instructions fetch has processed +system.cpu.fetch.Branches 302436824 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 176191625 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 431629876 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 85633501 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 155381037 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 133 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 285867319 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 5539236 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 950955907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.537748 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.221191 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 95 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 285890160 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 5533233 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 950851132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.536857 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.220630 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 519225507 54.60% 54.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23584051 2.48% 57.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 38809935 4.08% 61.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 47901977 5.04% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 41256448 4.34% 70.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 47147738 4.96% 75.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 39135623 4.12% 79.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 18358633 1.93% 81.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 175535995 18.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 519221373 54.61% 54.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23554787 2.48% 57.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38911325 4.09% 61.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 47909996 5.04% 66.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 41216698 4.33% 70.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 47160592 4.96% 75.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 39133251 4.12% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 18348533 1.93% 81.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 175394577 18.45% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 950955907 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.315535 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.264706 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 327119471 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 132830999 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 402990203 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 19239879 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 68775355 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 46282380 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 697 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2359573845 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2428 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 68775355 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 349888082 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 63823546 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 14916 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 397833782 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70620226 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2300864153 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 28671 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 5550118 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 56484879 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 2275806889 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 10620956453 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 10620952653 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3800 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 1706319938 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 569486951 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5312 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5309 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 155780896 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 627644360 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 219694213 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 87145300 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 68089448 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2199982180 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1528 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2020409598 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 4999430 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 472571343 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1103696346 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1357 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 950955907 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.124609 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.914480 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 950851132 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.315582 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.264287 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 327095784 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 132835494 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 402923516 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 19252859 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 68743479 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 46256582 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2358824481 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2518 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 68743479 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 349861256 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 63822770 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14217 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 397782583 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70626827 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2300352404 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 28571 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 5556438 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 56486754 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 21 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 2275431187 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 10618596825 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 10618592524 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4301 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 1706319954 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 569111233 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1538 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1535 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 155721257 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 627567306 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 219602180 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 87405609 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 68407559 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2199673736 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1543 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2020179794 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 4995947 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 472270317 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1103060101 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1370 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 950851132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.124602 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.914321 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 272613444 28.67% 28.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 148967706 15.67% 44.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 160979511 16.93% 61.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 117706760 12.38% 73.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 124599704 13.10% 86.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 74507798 7.84% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 38341084 4.03% 98.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 10540920 1.11% 99.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 2698980 0.28% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 272421375 28.65% 28.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 149099949 15.68% 44.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 161022280 16.93% 61.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 117844218 12.39% 73.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 124393177 13.08% 86.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 74467059 7.83% 94.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 38344308 4.03% 98.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10541348 1.11% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 2717418 0.29% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 950955907 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 950851132 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 849524 3.40% 3.40% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 4750 0.02% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 18987433 76.01% 79.43% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5139841 20.57% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 857125 3.43% 3.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 4796 0.02% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 18987474 76.03% 79.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5123425 20.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1236587791 61.20% 61.20% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 931138 0.05% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1236499214 61.21% 61.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 932103 0.05% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.25% # Type of FU issued @@ -233,164 +233,164 @@ system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.25% # Ty system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 64 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 23 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 12 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 78 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 35 0.00% 61.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 588900248 29.15% 90.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 193990319 9.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 588851338 29.15% 90.40% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 193897003 9.60% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2020409598 # Type of FU issued -system.cpu.iq.rate 2.108004 # Inst issue rate -system.cpu.iq.fu_busy_cnt 24981548 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012365 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5021755668 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2672741554 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1961287360 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 413 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 736 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 160 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2045390937 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 209 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63645440 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2020179794 # Type of FU issued +system.cpu.iq.rate 2.107985 # Inst issue rate +system.cpu.iq.fu_busy_cnt 24972820 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012362 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5021178993 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2672131610 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1961102368 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 494 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 800 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 185 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2045152363 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 251 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 63608304 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 141717590 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 292895 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 189897 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 44847167 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 141640534 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 283255 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 189454 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 44755132 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1141778 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 1142386 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 68775355 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 28059003 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1485687 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2199992043 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 5558489 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 627644360 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 219694213 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1465 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 343629 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 56102 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 189897 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 8602375 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 10226115 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 18828490 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1990642810 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 574277068 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29766788 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 68743479 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 28058898 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1485147 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2199675446 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 5559671 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 627567306 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 219602180 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1479 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 343072 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 56281 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 189454 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 8595611 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 10221674 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 18817285 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1990434220 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 574229120 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29745574 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 8335 # number of nop insts executed -system.cpu.iew.exec_refs 765299887 # number of memory reference insts executed -system.cpu.iew.exec_branches 238409980 # Number of branches executed -system.cpu.iew.exec_stores 191022819 # Number of stores executed -system.cpu.iew.exec_rate 2.076946 # Inst execution rate -system.cpu.iew.wb_sent 1970153008 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1961287520 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1296694675 # num instructions producing a value -system.cpu.iew.wb_consumers 2069023421 # num instructions consuming a value +system.cpu.iew.exec_nop 167 # number of nop insts executed +system.cpu.iew.exec_refs 765174747 # number of memory reference insts executed +system.cpu.iew.exec_branches 238396251 # Number of branches executed +system.cpu.iew.exec_stores 190945627 # Number of stores executed +system.cpu.iew.exec_rate 2.076947 # Inst execution rate +system.cpu.iew.wb_sent 1969970289 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1961102553 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1296676707 # num instructions producing a value +system.cpu.iew.wb_consumers 2069059836 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.046318 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.626718 # average fanout of values written-back +system.cpu.iew.wb_rate 2.046340 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.626699 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 476993558 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 171 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16110924 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 882180553 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.953199 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.727625 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 476677558 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 173 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 16102047 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 882107654 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.953360 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.727618 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 391561558 44.39% 44.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 194873977 22.09% 66.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73868669 8.37% 74.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 35208101 3.99% 78.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 19136047 2.17% 81.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 30738627 3.48% 84.49% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 19218397 2.18% 86.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11310881 1.28% 87.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106264296 12.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 391464028 44.38% 44.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 194903618 22.10% 66.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73864004 8.37% 74.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 35187525 3.99% 78.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 19179450 2.17% 81.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 30712235 3.48% 84.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 19231414 2.18% 86.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11310832 1.28% 87.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106254548 12.05% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 882180553 # Number of insts commited each cycle -system.cpu.commit.committedInsts 1544563046 # Number of instructions committed -system.cpu.commit.committedOps 1723073858 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 882107654 # Number of insts commited each cycle +system.cpu.commit.committedInsts 1544563056 # Number of instructions committed +system.cpu.commit.committedOps 1723073868 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 660773816 # Number of memory references committed -system.cpu.commit.loads 485926770 # Number of loads committed +system.cpu.commit.refs 660773820 # Number of memory references committed +system.cpu.commit.loads 485926772 # Number of loads committed system.cpu.commit.membars 62 # Number of memory barriers committed -system.cpu.commit.branches 213462364 # Number of branches committed +system.cpu.commit.branches 213462429 # Number of branches committed system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. -system.cpu.commit.int_insts 1536941845 # Number of committed integer instructions. +system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions. system.cpu.commit.function_calls 13665177 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106264296 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106254548 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2975983074 # The number of ROB reads -system.cpu.rob.rob_writes 4469074827 # The number of ROB writes -system.cpu.timesIdled 802305 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7491058 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 1544563028 # Number of Instructions Simulated -system.cpu.committedOps 1723073840 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 1544563028 # Number of Instructions Simulated -system.cpu.cpi 0.620530 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.620530 # CPI: Total CPI of All Threads -system.cpu.ipc 1.611527 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.611527 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 9971495260 # number of integer regfile reads -system.cpu.int_regfile_writes 1941105565 # number of integer regfile writes -system.cpu.fp_regfile_reads 174 # number of floating regfile reads -system.cpu.fp_regfile_writes 178 # number of floating regfile writes -system.cpu.misc_regfile_reads 2911260843 # number of misc regfile reads -system.cpu.misc_regfile_writes 126 # number of misc regfile writes -system.cpu.icache.replacements 26 # number of replacements -system.cpu.icache.tagsinuse 632.958434 # Cycle average of tags in use -system.cpu.icache.total_refs 285866178 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 790 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 361855.921519 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 2975603933 # The number of ROB reads +system.cpu.rob.rob_writes 4468410288 # The number of ROB writes +system.cpu.timesIdled 802202 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 7495082 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 1544563038 # Number of Instructions Simulated +system.cpu.committedOps 1723073850 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 1544563038 # Number of Instructions Simulated +system.cpu.cpi 0.620464 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.620464 # CPI: Total CPI of All Threads +system.cpu.ipc 1.611696 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.611696 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 9970442228 # number of integer regfile reads +system.cpu.int_regfile_writes 1940974329 # number of integer regfile writes +system.cpu.fp_regfile_reads 200 # number of floating regfile reads +system.cpu.fp_regfile_writes 218 # number of floating regfile writes +system.cpu.misc_regfile_reads 2910515379 # number of misc regfile reads +system.cpu.misc_regfile_writes 130 # number of misc regfile writes +system.cpu.icache.replacements 28 # number of replacements +system.cpu.icache.tagsinuse 630.233308 # Cycle average of tags in use +system.cpu.icache.total_refs 285889001 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 791 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 361427.308470 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 632.958434 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.309062 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.309062 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 285866178 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 285866178 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 285866178 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 285866178 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 285866178 # number of overall hits -system.cpu.icache.overall_hits::total 285866178 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1141 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1141 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1141 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1141 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1141 # number of overall misses -system.cpu.icache.overall_misses::total 1141 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40467500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40467500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40467500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40467500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40467500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40467500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 285867319 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 285867319 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 285867319 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 285867319 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 285867319 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 285867319 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 630.233308 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.307731 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.307731 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 285889001 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 285889001 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 285889001 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 285889001 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 285889001 # number of overall hits +system.cpu.icache.overall_hits::total 285889001 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1159 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1159 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1159 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1159 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1159 # number of overall misses +system.cpu.icache.overall_misses::total 1159 # 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miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030080 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.030080 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033708 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033708 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.023576 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.023576 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.023576 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.023576 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23993.859729 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 23993.859729 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37819.107373 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37819.107373 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 96 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 96 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 64 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 64 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 677819848 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 677819848 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 677819848 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 677819848 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021350 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021350 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030079 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.030079 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.031250 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.031250 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.023572 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023572 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023572 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023572 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23992.423044 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23992.423044 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37816.280567 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37816.280567 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 39500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 39500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28485.144620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28485.144620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28485.144620 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 2522668245 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 141500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 425263 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 5932.019115 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 23583.333333 # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28483.812569 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28483.812569 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28483.812569 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28483.812569 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2524022061 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 152500 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 425271 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 5935.090944 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19062.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3474615 # number of writebacks -system.cpu.dcache.writebacks::total 3474615 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3059553 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 3059553 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297512 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3297512 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 3474670 # number of writebacks +system.cpu.dcache.writebacks::total 3474670 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3056668 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3056668 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3297283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3297283 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 6357065 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 6357065 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 6357065 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 6357065 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729385 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7729385 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893873 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1893873 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215982528039 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 215982528039 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015298 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015298 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 6353951 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 6353951 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 6353951 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 6353951 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7729919 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7729919 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893923 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1893923 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9623842 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9623842 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9623842 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9623842 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 124459960000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 124459960000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91541598892 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 91541598892 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 216001558892 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 216001558892 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 216001558892 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 216001558892 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015300 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015300 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014197 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014197 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014197 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014197 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16100.450941 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16100.450941 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48332.672803 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48332.672803 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22443.805210 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22443.805210 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22443.805210 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22443.805210 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014198 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014198 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014198 # 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miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36239.445910 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 35999.343322 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35999.456177 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39295.413239 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39295.413239 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36239.445910 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37120.369803 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 37120.096524 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36239.445910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37120.369803 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 37120.096524 # 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number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 792 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9623840 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9624632 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 792 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9623840 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9624632 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958333 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.208670 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438651 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.438651 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958333 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.253868 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.253926 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958333 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.253868 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.253926 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36137.681159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36001.773122 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 36001.837067 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39297.785882 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39297.785882 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36137.681159 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 37122.538148 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 37122.232287 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36137.681159 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 37122.538148 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 37122.232287 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 30309734 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 3559 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 3624 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8439.092723 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8363.613135 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1124216 # number of writebacks -system.cpu.l2cache.writebacks::total 1124216 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1124204 # number of writebacks +system.cpu.l2cache.writebacks::total 1124204 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits @@ -658,50 +662,50 @@ system.cpu.l2cache.demand_mshr_hits::total 8 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611893 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1612650 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830780 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 830780 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2442673 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2443430 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2442673 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2443430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25045000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 52994170500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53019215500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 30019129886 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 30019129886 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25045000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 83013300386 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 83038345386 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25045000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 83013300386 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 83038345386 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208541 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208618 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438667 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438667 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.253888 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958228 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253830 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.253888 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33084.544254 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32876.977876 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32877.075311 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36133.669426 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36133.669426 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33084.544254 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33984.614554 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33984.335703 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 758 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1612403 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1613161 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830771 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 830771 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 758 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2443174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2443932 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 758 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2443174 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2443932 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24996000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 53015079500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 53040075500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 30022059834 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 30022059834 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24996000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 83037139334 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 83062135334 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24996000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 83037139334 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 83062135334 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.957071 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208669 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438651 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438651 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.957071 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253867 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.253925 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.957071 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253867 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.253925 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32976.253298 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 32879.546553 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32879.591994 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36137.587655 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36137.587655 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32976.253298 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33987.402999 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 33987.089385 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32976.253298 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33987.402999 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33987.089385 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index e60a29e1d..b82b134f8 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 5ff891bb9..06746d191 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:21:22 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:26:56 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index 9f9278806..3e4545cce 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.861538 # Nu sim_ticks 861538200000 # Number of ticks simulated final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3167213 # Simulator instruction rate (inst/s) -host_op_rate 3533259 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1766632085 # Simulator tick rate (ticks/s) -host_mem_usage 225200 # Number of bytes of host memory used -host_seconds 487.67 # Real time elapsed on the host +host_inst_rate 2426875 # Simulator instruction rate (inst/s) +host_op_rate 2707358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1353681051 # Simulator tick rate (ticks/s) +host_mem_usage 219056 # Number of bytes of host memory used +host_seconds 636.44 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1723073853 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 1723073853 # Nu system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498327 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_int_register_reads 7861284498 # number of times the integer registers were read diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index d5edd6037..a32ea8ea4 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,12 +182,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 2722378bf..92d2da7b2 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 16:44:36 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 11:53:48 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... spec_init diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 906e755f1..becebde6e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.409361 # Nu sim_ticks 2409361491000 # Number of ticks simulated final_tick 2409361491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1494553 # Simulator instruction rate (inst/s) -host_op_rate 1667935 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2340143235 # Simulator tick rate (ticks/s) -host_mem_usage 233700 # Number of bytes of host memory used -host_seconds 1029.58 # Real time elapsed on the host +host_inst_rate 1043020 # Simulator instruction rate (inst/s) +host_op_rate 1164020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1633141547 # Simulator tick rate (ticks/s) +host_mem_usage 227940 # Number of bytes of host memory used +host_seconds 1475.29 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory @@ -85,7 +85,7 @@ system.cpu.committedOps 1717270334 # Nu system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses system.cpu.num_func_calls 27330256 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 177498327 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls system.cpu.num_int_insts 1536941842 # number of integer instructions system.cpu.num_fp_insts 36 # number of float instructions system.cpu.num_int_register_reads 9304894672 # number of times the integer registers were read diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 3f37afa6e..6abd7ca4a 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -95,7 +96,6 @@ numPhysIntRegs=256 numROBEntries=192 numRobs=1 numThreads=1 -phase=0 predType=tournament profile=0 progress_interval=0 @@ -129,16 +129,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -157,8 +159,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -430,16 +432,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -461,8 +465,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -471,16 +475,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=false -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=2097152 subblock_size=0 system=system @@ -507,12 +513,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -530,13 +536,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index e4047fa1c..b01ca9643 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 16:47:08 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sav -Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 13:57:03 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 76017712000 because target called exit() +122 123 124 Exiting @ tick 76020082000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index abf6c428d..e95f937b3 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.076018 # Number of seconds simulated -sim_ticks 76017712000 # Number of ticks simulated -final_tick 76017712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.076020 # Number of seconds simulated +sim_ticks 76020082000 # Number of ticks simulated +final_tick 76020082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156722 # Simulator instruction rate (inst/s) -host_op_rate 171594 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69131199 # Simulator tick rate (ticks/s) -host_mem_usage 238024 # Number of bytes of host memory used -host_seconds 1099.62 # Real time elapsed on the host -sim_insts 172333351 # Number of instructions simulated -sim_ops 188686833 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 131968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory -system.physmem.bytes_read::total 244160 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 131968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 131968 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2062 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3815 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1736016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1475867 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3211883 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1736016 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1736016 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1736016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1475867 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3211883 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 108434 # Simulator instruction rate (inst/s) +host_op_rate 118724 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47832871 # Simulator tick rate (ticks/s) +host_mem_usage 232824 # Number of bytes of host memory used +host_seconds 1589.29 # Real time elapsed on the host +sim_insts 172333166 # Number of instructions simulated +sim_ops 188686648 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 132416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 112256 # Number of bytes read from this memory +system.physmem.bytes_read::total 244672 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 132416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 132416 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2069 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1754 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3823 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1741856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1476662 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3218518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1741856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1741856 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1741856 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1476662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3218518 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,321 +70,320 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 152035425 # number of cpu cycles simulated +system.cpu.numCycles 152040165 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 96736502 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 76001405 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 6554044 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 46407824 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 44181263 # Number of BTB hits +system.cpu.BPredUnit.lookups 96858484 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 76060964 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 6563923 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 46433794 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 44260375 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 4475583 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 89477 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 40615724 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 388321121 # Number of instructions fetch has processed -system.cpu.fetch.Branches 96736502 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 48656846 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 82257766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 28468285 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7213696 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 8844 # Number of stall cycles due to pending traps +system.cpu.BPredUnit.usedRAS 4475068 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 89115 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 40665802 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 388394971 # Number of instructions fetch has processed +system.cpu.fetch.Branches 96858484 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 48735443 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 82285186 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 28468460 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 7130109 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 7 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9134 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 37645633 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1886253 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 151974828 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.798620 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.154172 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 37715921 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1893970 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 151978869 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.797548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.152738 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 69887899 45.99% 45.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5501348 3.62% 49.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10684945 7.03% 56.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 10435662 6.87% 63.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 8784636 5.78% 69.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 6836908 4.50% 73.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 6295744 4.14% 77.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 8337493 5.49% 83.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 25210193 16.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 69866943 45.97% 45.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5495765 3.62% 49.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 10729414 7.06% 56.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 10452168 6.88% 63.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 8790327 5.78% 69.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 6826108 4.49% 73.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 6308927 4.15% 77.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 8362057 5.50% 83.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 25147160 16.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151974828 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.636276 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.554149 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 46658969 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 5920762 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 76552571 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1116980 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 21725546 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 14796577 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 162492 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 401466473 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 736417 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 21725546 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 52184597 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 714677 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 792157 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 72083528 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 4474323 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 378974639 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 320673 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 3580560 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 14 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 642268895 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1614410837 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1596806412 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 17604425 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 298092667 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 344176228 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 52668 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 52665 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12854506 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 43974668 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16894662 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5833133 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 3767851 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 334792286 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 74530 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 252791404 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 896561 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 144952187 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 373840168 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 23248 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151974828 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.663377 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.758905 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 151978869 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.637059 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.554555 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 46697521 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5834788 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 76594287 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1116884 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 21735389 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 14843189 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 162820 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 401520259 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 676254 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 21735389 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 52210117 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 723485 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 695226 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 72137663 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4476989 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 379210260 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 320036 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 3584710 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 642738695 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1615361151 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1597815620 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17545531 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 298092371 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 344646324 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33437 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 33435 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12677945 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 44005038 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16906133 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5806665 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3723076 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 335023972 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 55533 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 252928025 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 900898 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 145168889 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 374298631 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 4288 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 151978869 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.664232 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.759052 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 58489364 38.49% 38.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 23011540 15.14% 53.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 25193746 16.58% 70.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 20486028 13.48% 83.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12864515 8.46% 92.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6577319 4.33% 96.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 4059001 2.67% 99.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1110893 0.73% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 182422 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 58441388 38.45% 38.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 23049169 15.17% 53.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 25167243 16.56% 70.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 20506081 13.49% 83.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12879623 8.47% 92.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6582625 4.33% 96.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 4058401 2.67% 99.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1110608 0.73% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 183731 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151974828 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 151978869 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 966666 37.58% 37.58% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 5596 0.22% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.80% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 136 0.01% 37.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 25 0.00% 37.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1199658 46.64% 84.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 400010 15.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 958151 37.34% 37.34% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 5590 0.22% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.56% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 95 0.00% 37.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 28 0.00% 37.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.57% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1196632 46.64% 84.21% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 405192 15.79% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 197331718 78.06% 78.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 995910 0.39% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33152 0.01% 78.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.47% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 164284 0.06% 78.53% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 255235 0.10% 78.63% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 76457 0.03% 78.66% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 467994 0.19% 78.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 206483 0.08% 78.93% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 71867 0.03% 78.96% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 38997717 15.43% 94.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 14190267 5.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 197423347 78.06% 78.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 995576 0.39% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33202 0.01% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 163925 0.06% 78.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 254716 0.10% 78.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 76426 0.03% 78.66% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 467079 0.18% 78.84% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 206343 0.08% 78.92% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 71849 0.03% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 39030082 15.43% 94.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 14205161 5.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 252791404 # Type of FU issued -system.cpu.iq.rate 1.662714 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2572091 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010175 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 657257029 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 477588320 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 240562315 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3769259 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2249868 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1852626 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 253473620 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1889875 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 2022881 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 252928025 # Type of FU issued +system.cpu.iq.rate 1.663561 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2565688 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010144 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 657530631 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 478025695 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 240682393 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3770874 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2241416 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1850793 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 253600335 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1893378 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 2031332 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 14119118 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 17181 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 19942 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 4243962 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 14149525 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 17193 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19478 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 4255470 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 21725546 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 15871 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 21735389 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 15851 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 654 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 334925114 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 838955 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 43974668 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16894662 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51980 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 159 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispatchedInsts 335097391 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 841360 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 44005038 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16906133 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 32986 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 165 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 265 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 19942 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4105078 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3945464 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8050542 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 245797206 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 37379001 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6994198 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19478 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4108816 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3932770 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8041586 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 245927260 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 37410682 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7000765 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 58298 # number of nop insts executed -system.cpu.iew.exec_refs 51189045 # number of memory reference insts executed -system.cpu.iew.exec_branches 54004994 # Number of branches executed -system.cpu.iew.exec_stores 13810044 # Number of stores executed -system.cpu.iew.exec_rate 1.616710 # Inst execution rate -system.cpu.iew.wb_sent 243546363 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 242414941 # cumulative count of insts written-back -system.cpu.iew.wb_producers 150055684 # num instructions producing a value -system.cpu.iew.wb_consumers 269132262 # num instructions consuming a value +system.cpu.iew.exec_nop 17886 # number of nop insts executed +system.cpu.iew.exec_refs 51227779 # number of memory reference insts executed +system.cpu.iew.exec_branches 54055496 # Number of branches executed +system.cpu.iew.exec_stores 13817097 # Number of stores executed +system.cpu.iew.exec_rate 1.617515 # Inst execution rate +system.cpu.iew.wb_sent 243665877 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 242533186 # cumulative count of insts written-back +system.cpu.iew.wb_producers 150106940 # num instructions producing a value +system.cpu.iew.wb_consumers 269220391 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.594464 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.557554 # average fanout of values written-back +system.cpu.iew.wb_rate 1.595192 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.557562 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 146223871 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 51282 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6420079 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 130249283 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.448770 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.161298 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 146396335 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 51245 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 6410682 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 130243481 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.448833 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.161152 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 60006705 46.07% 46.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 32087583 24.64% 70.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 13984606 10.74% 81.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 7660285 5.88% 87.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4414959 3.39% 90.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1331514 1.02% 91.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1740633 1.34% 93.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1281617 0.98% 94.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 7741381 5.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 59985952 46.06% 46.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 32109376 24.65% 70.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 13980234 10.73% 81.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 7652770 5.88% 87.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4424001 3.40% 90.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1333573 1.02% 91.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1734640 1.33% 93.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1282307 0.98% 94.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 7740628 5.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 130249283 # Number of insts commited each cycle -system.cpu.commit.committedInsts 172347739 # Number of instructions committed -system.cpu.commit.committedOps 188701221 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 130243481 # Number of insts commited each cycle +system.cpu.commit.committedInsts 172347554 # Number of instructions committed +system.cpu.commit.committedOps 188701036 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 42506250 # Number of memory references committed -system.cpu.commit.loads 29855550 # Number of loads committed +system.cpu.commit.refs 42506176 # Number of memory references committed +system.cpu.commit.loads 29855513 # Number of loads committed system.cpu.commit.membars 22408 # Number of memory barriers committed -system.cpu.commit.branches 40287748 # Number of branches committed +system.cpu.commit.branches 40306340 # Number of branches committed system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. -system.cpu.commit.int_insts 150130481 # Number of committed integer instructions. +system.cpu.commit.int_insts 150130333 # Number of committed integer instructions. system.cpu.commit.function_calls 1848934 # Number of function calls committed. -system.cpu.commit.bw_lim_events 7741381 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 7740628 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 457427793 # The number of ROB reads -system.cpu.rob.rob_writes 691694403 # The number of ROB writes -system.cpu.timesIdled 1790 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 60597 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 172333351 # Number of Instructions Simulated -system.cpu.committedOps 188686833 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 172333351 # Number of Instructions Simulated -system.cpu.cpi 0.882217 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.882217 # CPI: Total CPI of All Threads -system.cpu.ipc 1.133508 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.133508 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1091781968 # number of integer regfile reads -system.cpu.int_regfile_writes 388588148 # number of integer regfile writes -system.cpu.fp_regfile_reads 2914249 # number of floating regfile reads -system.cpu.fp_regfile_writes 2512479 # number of floating regfile writes -system.cpu.misc_regfile_reads 474590594 # number of misc regfile reads -system.cpu.misc_regfile_writes 832168 # number of misc regfile writes -system.cpu.icache.replacements 2661 # number of replacements -system.cpu.icache.tagsinuse 1361.223505 # Cycle average of tags in use -system.cpu.icache.total_refs 37640447 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 4399 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8556.591725 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 457595023 # The number of ROB reads +system.cpu.rob.rob_writes 692049675 # The number of ROB writes +system.cpu.timesIdled 1805 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 61296 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 172333166 # Number of Instructions Simulated +system.cpu.committedOps 188686648 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 172333166 # Number of Instructions Simulated +system.cpu.cpi 0.882246 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.882246 # CPI: Total CPI of All Threads +system.cpu.ipc 1.133471 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.133471 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092342028 # number of integer regfile reads +system.cpu.int_regfile_writes 388769433 # number of integer regfile writes +system.cpu.fp_regfile_reads 2911784 # number of floating regfile reads +system.cpu.fp_regfile_writes 2509539 # number of floating regfile writes +system.cpu.misc_regfile_reads 474699170 # number of misc regfile reads +system.cpu.misc_regfile_writes 832094 # number of misc regfile writes +system.cpu.icache.replacements 2665 # number of replacements +system.cpu.icache.tagsinuse 1365.695198 # Cycle average of tags in use +system.cpu.icache.total_refs 37710725 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 4406 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 8558.948025 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1361.223505 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.664660 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.664660 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 37640447 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 37640447 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 37640447 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 37640447 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 37640447 # number of overall hits -system.cpu.icache.overall_hits::total 37640447 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5186 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5186 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5186 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5186 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5186 # number of overall misses -system.cpu.icache.overall_misses::total 5186 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 114498500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 114498500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 114498500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 114498500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 114498500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 114498500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 37645633 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 37645633 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 37645633 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 37645633 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 37645633 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 37645633 # number of overall (read+write) accesses +system.cpu.icache.occ_blocks::cpu.inst 1365.695198 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.666843 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.666843 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 37710725 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 37710725 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 37710725 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 37710725 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 37710725 # number of overall hits +system.cpu.icache.overall_hits::total 37710725 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5196 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5196 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5196 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5196 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5196 # number of overall misses +system.cpu.icache.overall_misses::total 5196 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 114882000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 114882000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 114882000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 114882000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 114882000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 114882000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 37715921 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 37715921 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 37715921 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 37715921 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 37715921 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 37715921 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000138 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000138 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000138 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000138 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000138 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22078.384111 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 22078.384111 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 22078.384111 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 22078.384111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 22078.384111 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 22078.384111 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22109.699769 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 22109.699769 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 22109.699769 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 22109.699769 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 22109.699769 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 22109.699769 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -393,246 +392,246 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 786 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 786 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 786 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 786 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 786 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 786 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4400 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4400 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4400 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4400 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4400 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4400 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80222500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 80222500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80222500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 80222500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80222500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 80222500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 790 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 790 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 790 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 790 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 790 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 790 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4406 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4406 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4406 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4406 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4406 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4406 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 80533500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 80533500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 80533500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 80533500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 80533500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 80533500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18232.386364 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18232.386364 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18232.386364 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18232.386364 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18232.386364 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18232.386364 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18278.143441 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18278.143441 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18278.143441 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18278.143441 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18278.143441 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18278.143441 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 57 # number of replacements -system.cpu.dcache.tagsinuse 1415.756952 # Cycle average of tags in use -system.cpu.dcache.total_refs 47292959 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1864 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 25371.759120 # Average number of references to valid blocks. +system.cpu.dcache.replacements 59 # number of replacements +system.cpu.dcache.tagsinuse 1417.829919 # Cycle average of tags in use +system.cpu.dcache.total_refs 47315704 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1866 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 25356.754555 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 1415.756952 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.345644 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.345644 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 34877985 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 34877985 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12356653 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12356653 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 29848 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 29848 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 28473 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 28473 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 47234638 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 47234638 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 47234638 # number of overall hits -system.cpu.dcache.overall_hits::total 47234638 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1937 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1937 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 7634 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 7634 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 1417.829919 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.346150 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.346150 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 34900386 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 34900386 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12356583 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12356583 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 30299 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 30299 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 28436 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 28436 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 47256969 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 47256969 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 47256969 # number of overall hits +system.cpu.dcache.overall_hits::total 47256969 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1941 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1941 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 7704 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 7704 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9571 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9571 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9571 # number of overall misses -system.cpu.dcache.overall_misses::total 9571 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 71164500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 71164500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 282690000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 282690000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 9645 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9645 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9645 # number of overall misses +system.cpu.dcache.overall_misses::total 9645 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 71450500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 71450500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 284851500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 284851500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 80500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 80500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 353854500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 353854500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 353854500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 353854500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 34879922 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 34879922 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 356302000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 356302000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 356302000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 356302000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 34902327 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 34902327 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 29850 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 29850 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 28473 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 28473 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 47244209 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 47244209 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 47244209 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 47244209 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30301 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 30301 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 28436 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 28436 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 47266614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 47266614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 47266614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 47266614 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000056 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000617 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000617 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000067 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000067 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000203 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000203 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000203 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000203 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36739.545689 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36739.545689 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37030.390359 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37030.390359 # average WriteReq miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000623 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000623 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000204 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000204 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000204 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000204 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36811.179804 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36811.179804 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36974.493769 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36974.493769 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 40250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 40250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36971.528576 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36971.528576 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36971.528576 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36971.528576 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36941.627786 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36941.627786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 36941.627786 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 36941.627786 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 10000 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 18000 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 9000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 16 # number of writebacks -system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1154 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1154 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6553 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6553 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 18 # number of writebacks +system.cpu.dcache.writebacks::total 18 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1165 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1165 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6614 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6614 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7707 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7707 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7707 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7707 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 783 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 783 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1081 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1081 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26652500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26652500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 38548000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 38548000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 65200500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 65200500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 65200500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 65200500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 7779 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7779 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7779 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 776 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 776 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1090 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1090 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1866 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1866 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1866 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1866 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26418500 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867178 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.528844 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993525 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.993525 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.609036 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.468636 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.940451 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.609036 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32067.895247 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33579.528719 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32442.356804 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31592.178771 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31592.178771 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32067.895247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32361.950941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32203.014417 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1082 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2069 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3823 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2069 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1754 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 3823 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66421500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 22618000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 89039500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 34148500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 34148500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66421500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 56766500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 123188000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66421500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 56766500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 123188000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867097 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.529048 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991751 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.939979 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.609534 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.939979 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.609534 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 32103.189947 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33657.738095 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32484.312295 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31560.536044 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31560.536044 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 32103.189947 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 32364.025086 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32222.861627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32103.189947 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 32364.025086 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32222.861627 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 337b40f6d..0be27d977 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -48,7 +49,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false @@ -68,8 +68,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[4] @@ -84,8 +84,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.membus.slave[3] @@ -95,12 +95,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -117,14 +117,15 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 -master=system.physmem.port[0] +width=8 +master=system.physmem.port slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index 887de4fb8..9558000b2 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 01:29:40 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:39:32 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 0e78b9612..15db555ed 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.103107 # Nu sim_ticks 103106766000 # Number of ticks simulated final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3148564 # Simulator instruction rate (inst/s) -host_op_rate 3447371 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1883953687 # Simulator tick rate (ticks/s) -host_mem_usage 227464 # Number of bytes of host memory used -host_seconds 54.73 # Real time elapsed on the host +host_inst_rate 2085648 # Simulator instruction rate (inst/s) +host_op_rate 2283582 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1247954818 # Simulator tick rate (ticks/s) +host_mem_usage 222132 # Number of bytes of host memory used +host_seconds 82.62 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 188670891 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory @@ -84,7 +84,7 @@ system.cpu.committedOps 188670891 # Nu system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions system.cpu.num_int_register_reads 809396612 # number of times the integer registers were read diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index e101e797a..a0628b862 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -10,6 +10,7 @@ time_sync_spin_threshold=100000000 type=System children=cpu membus physmem boot_osflags=a +clock=1 init_param=0 kernel= load_addr_mask=1099511627775 @@ -47,7 +48,6 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 system=system @@ -61,16 +61,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=262144 subblock_size=0 system=system @@ -89,8 +91,8 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -99,16 +101,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=1000 is_top_level=true -latency=1000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=1000 size=131072 subblock_size=0 system=system @@ -130,8 +134,8 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -max_backoff=100000 -min_backoff=0 +clock=1 +num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -140,16 +144,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=2 block_size=64 +clock=1 forward_snoops=true hash_delay=1 +hit_latency=10000 is_top_level=false -latency=10000 max_miss_count=0 mshrs=10 prefetch_on_access=false prefetcher=Null prioritizeRequests=false repl=Null +response_latency=10000 size=2097152 subblock_size=0 system=system @@ -176,12 +182,12 @@ type=ExeTracer [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing +cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/projects/pd/randd/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -199,13 +205,14 @@ clock=1000 header_cycles=1 use_default_range=false width=8 -master=system.physmem.port[0] +master=system.physmem.port slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleMemory +bandwidth=73.000000 +clock=1 conf_table_reported=false -file= in_addr_map=true latency=30000 latency_var=0 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index fe3f7fc4c..6bb4ad05f 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 17:03:03 -gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing/smred.sav -Couldn't unlink build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 +gem5 compiled Sep 21 2012 11:19:00 +gem5 started Sep 21 2012 12:07:48 +gem5 executing on u200540-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 709a3b23f..ee5d7fbdb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.232090 # Nu sim_ticks 232089948000 # Number of ticks simulated final_tick 232089948000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1678684 # Simulator instruction rate (inst/s) -host_op_rate 1838338 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2267224735 # Simulator tick rate (ticks/s) -host_mem_usage 235976 # Number of bytes of host memory used -host_seconds 102.37 # Real time elapsed on the host +host_inst_rate 1108463 # Simulator instruction rate (inst/s) +host_op_rate 1213886 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1497086914 # Simulator tick rate (ticks/s) +host_mem_usage 230968 # Number of bytes of host memory used +host_seconds 155.03 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -78,7 +78,7 @@ system.cpu.committedOps 188185920 # Nu system.cpu.num_int_alu_accesses 150106218 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3545028 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 32493890 # number of instructions that are conditional controls +system.cpu.num_conditional_control_insts 32494341 # number of instructions that are conditional controls system.cpu.num_int_insts 150106218 # number of integer instructions system.cpu.num_fp_insts 1752310 # number of float instructions system.cpu.num_int_register_reads 898652246 # number of times the integer registers were read |