diff options
| author | Gabe Black <gabeblack@google.com> | 2015-01-07 00:31:09 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2015-01-07 00:31:09 -0800 |
| commit | d0284544ec339808c2273ced3ebc566cad285a4a (patch) | |
| tree | 9a422f15bc9d10b58c9bf4c3a461994690df3e9f /tests/long | |
| parent | cd6380605c55bb9127d7f33ab717892642884e85 (diff) | |
| download | gem5-d0284544ec339808c2273ced3ebc566cad285a4a.tar.xz | |
stats: x86: Update stats for the CPUID change.
Diffstat (limited to 'tests/long')
10 files changed, 2908 insertions, 2763 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index 354237141..b4e8db156 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -207,6 +207,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -257,6 +258,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -599,6 +601,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -665,6 +668,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -700,6 +704,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 @@ -1202,6 +1207,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index 0bfe3bfc6..7183ecafd 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 19 2014 14:40:22 -gem5 started Nov 19 2014 14:41:52 +gem5 compiled Jan 6 2015 22:19:56 +gem5 started Jan 6 2015 22:27:08 gem5 executing on gabeblackz620.mtv.corp.google.com command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5125902116500 because m5_exit instruction encountered +Exiting @ tick 5125946039500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index fdc0fba9d..993fcc90f 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,129 +1,129 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.129943 # Number of seconds simulated -sim_ticks 5129943020500 # Number of ticks simulated -final_tick 5129943020500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.125946 # Number of seconds simulated +sim_ticks 5125946039500 # Number of ticks simulated +final_tick 5125946039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121408 # Simulator instruction rate (inst/s) -host_op_rate 239988 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1526556123 # Simulator tick rate (ticks/s) -host_mem_usage 798272 # Number of bytes of host memory used -host_seconds 3360.47 # Real time elapsed on the host -sim_insts 407987808 # Number of instructions simulated -sim_ops 806471132 # Number of ops (including micro ops) simulated +host_inst_rate 214937 # Simulator instruction rate (inst/s) +host_op_rate 424847 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2699457200 # Simulator tick rate (ticks/s) +host_mem_usage 751580 # Number of bytes of host memory used +host_seconds 1898.88 # Real time elapsed on the host +sim_insts 408140259 # Number of instructions simulated +sim_ops 806733017 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 4352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1049088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10796544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1045568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10796928 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11878656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1049088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1049088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9594624 # Number of bytes written to this memory -system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory +system.physmem.bytes_read::total 11875520 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1045568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1045568 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9590656 # Number of bytes written to this memory +system.physmem.bytes_written::total 9590656 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 68 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16392 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168696 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16337 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168702 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185604 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149916 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 848 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 185555 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149854 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149854 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 849 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2104613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2315553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204503 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1870318 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1870318 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1870318 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 203976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2106329 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2316747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203976 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1871002 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1871002 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1871002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 849 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2104613 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5527 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4185871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185604 # Number of read requests accepted -system.physmem.writeReqs 196636 # Number of write requests accepted -system.physmem.readBursts 185604 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196636 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11865664 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12992 # Total number of bytes read from write queue -system.physmem.bytesWritten 12442240 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11878656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12584704 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 203 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2199 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1712 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11483 # Per bank write bursts -system.physmem.perBankRdBursts::1 10958 # Per bank write bursts -system.physmem.perBankRdBursts::2 11903 # Per bank write bursts -system.physmem.perBankRdBursts::3 11497 # Per bank write bursts -system.physmem.perBankRdBursts::4 11986 # Per bank write bursts -system.physmem.perBankRdBursts::5 11369 # Per bank write bursts -system.physmem.perBankRdBursts::6 11563 # Per bank write bursts -system.physmem.perBankRdBursts::7 11462 # Per bank write bursts -system.physmem.perBankRdBursts::8 11178 # Per bank write bursts -system.physmem.perBankRdBursts::9 11812 # Per bank write bursts -system.physmem.perBankRdBursts::10 11732 # Per bank write bursts -system.physmem.perBankRdBursts::11 11823 # Per bank write bursts -system.physmem.perBankRdBursts::12 11783 # Per bank write bursts -system.physmem.perBankRdBursts::13 12309 # Per bank write bursts -system.physmem.perBankRdBursts::14 11732 # Per bank write bursts -system.physmem.perBankRdBursts::15 10811 # Per bank write bursts -system.physmem.perBankWrBursts::0 14023 # Per bank write bursts -system.physmem.perBankWrBursts::1 13077 # Per bank write bursts -system.physmem.perBankWrBursts::2 12485 # Per bank write bursts -system.physmem.perBankWrBursts::3 11134 # Per bank write bursts -system.physmem.perBankWrBursts::4 11942 # Per bank write bursts -system.physmem.perBankWrBursts::5 11710 # Per bank write bursts -system.physmem.perBankWrBursts::6 11692 # Per bank write bursts -system.physmem.perBankWrBursts::7 11673 # Per bank write bursts -system.physmem.perBankWrBursts::8 11519 # Per bank write bursts -system.physmem.perBankWrBursts::9 11764 # Per bank write bursts -system.physmem.perBankWrBursts::10 12914 # Per bank write bursts -system.physmem.perBankWrBursts::11 11938 # Per bank write bursts -system.physmem.perBankWrBursts::12 12257 # Per bank write bursts -system.physmem.perBankWrBursts::13 11913 # Per bank write bursts -system.physmem.perBankWrBursts::14 12398 # Per bank write bursts -system.physmem.perBankWrBursts::15 11971 # Per bank write bursts +system.physmem.bw_total::cpu.inst 203976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2106329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4187749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185555 # Number of read requests accepted +system.physmem.writeReqs 196574 # Number of write requests accepted +system.physmem.readBursts 185555 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 196574 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11866560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue +system.physmem.bytesWritten 12447744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11875520 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12580736 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 2049 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1754 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11700 # Per bank write bursts +system.physmem.perBankRdBursts::1 10942 # Per bank write bursts +system.physmem.perBankRdBursts::2 11772 # Per bank write bursts +system.physmem.perBankRdBursts::3 11534 # Per bank write bursts +system.physmem.perBankRdBursts::4 11556 # Per bank write bursts +system.physmem.perBankRdBursts::5 11202 # Per bank write bursts +system.physmem.perBankRdBursts::6 11589 # Per bank write bursts +system.physmem.perBankRdBursts::7 11470 # Per bank write bursts +system.physmem.perBankRdBursts::8 10957 # Per bank write bursts +system.physmem.perBankRdBursts::9 11574 # Per bank write bursts +system.physmem.perBankRdBursts::10 11037 # Per bank write bursts +system.physmem.perBankRdBursts::11 11773 # Per bank write bursts +system.physmem.perBankRdBursts::12 12032 # Per bank write bursts +system.physmem.perBankRdBursts::13 13037 # Per bank write bursts +system.physmem.perBankRdBursts::14 11759 # Per bank write bursts +system.physmem.perBankRdBursts::15 11481 # Per bank write bursts +system.physmem.perBankWrBursts::0 13445 # Per bank write bursts +system.physmem.perBankWrBursts::1 12349 # Per bank write bursts +system.physmem.perBankWrBursts::2 11384 # Per bank write bursts +system.physmem.perBankWrBursts::3 11463 # Per bank write bursts +system.physmem.perBankWrBursts::4 12267 # Per bank write bursts +system.physmem.perBankWrBursts::5 12371 # Per bank write bursts +system.physmem.perBankWrBursts::6 11486 # Per bank write bursts +system.physmem.perBankWrBursts::7 11359 # Per bank write bursts +system.physmem.perBankWrBursts::8 11596 # Per bank write bursts +system.physmem.perBankWrBursts::9 12338 # Per bank write bursts +system.physmem.perBankWrBursts::10 11770 # Per bank write bursts +system.physmem.perBankWrBursts::11 12080 # Per bank write bursts +system.physmem.perBankWrBursts::12 12282 # Per bank write bursts +system.physmem.perBankWrBursts::13 12669 # Per bank write bursts +system.physmem.perBankWrBursts::14 12453 # Per bank write bursts +system.physmem.perBankWrBursts::15 13184 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5129942968500 # Total gap between requests +system.physmem.totGap 5125945988000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185604 # Read request sizes (log2) +system.physmem.readPktSize::6 185555 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196636 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2018 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.writePktSize::6 196574 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170769 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2025 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see @@ -156,140 +156,138 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12555 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 322 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 75289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 322.860444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.432072 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.383638 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27971 37.15% 37.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17364 23.06% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7569 10.05% 70.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4193 5.57% 75.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3123 4.15% 79.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1949 2.59% 82.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1359 1.81% 84.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1178 1.56% 85.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10583 14.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 75289 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7789 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.801643 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 545.365861 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7788 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 10935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 11433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 12449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 12895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 13963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 13629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 13176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 12672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 11348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8475 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 592 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 75192 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.362060 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 187.476414 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 341.898646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27996 37.23% 37.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17297 23.00% 60.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7451 9.91% 70.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4205 5.59% 75.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3004 4.00% 79.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2064 2.74% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1408 1.87% 84.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1199 1.59% 85.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10568 14.05% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 75192 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7811 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.734349 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 544.550807 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7810 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7789 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7789 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.959558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.372117 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.594707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6350 81.53% 81.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 59 0.76% 82.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 17 0.22% 82.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 286 3.67% 86.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 164 2.11% 88.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 59 0.76% 89.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.53% 89.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 34 0.44% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 175 2.25% 92.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.21% 92.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 16 0.21% 92.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.17% 92.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 28 0.36% 93.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.21% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.13% 93.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 42 0.54% 94.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 108 1.39% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.12% 95.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 9 0.12% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 24 0.31% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 141 1.81% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 97.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 13 0.17% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.05% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 34 0.44% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 98.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 10 0.13% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 98.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.18% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.06% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 5 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.17% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 10 0.13% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 6 0.08% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 11 0.14% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.04% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.06% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 2 0.03% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 6 0.08% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 3 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7789 # Writes before turning the bus around for reads -system.physmem.totQLat 1998636250 # Total ticks spent queuing -system.physmem.totMemAccLat 5474905000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 927005000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10780.07 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7811 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7811 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.900269 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.294695 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 24.961495 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6395 81.87% 81.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 66 0.84% 82.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 12 0.15% 82.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 258 3.30% 86.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 186 2.38% 88.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 50 0.64% 89.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 38 0.49% 89.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 45 0.58% 90.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 169 2.16% 92.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.14% 92.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 12 0.15% 92.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 16 0.20% 92.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 26 0.33% 93.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 16 0.20% 93.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 15 0.19% 93.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 41 0.52% 94.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 93 1.19% 95.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 13 0.17% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 9 0.12% 95.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 19 0.24% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 147 1.88% 97.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.04% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 13 0.17% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 4 0.05% 98.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 20 0.26% 98.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 9 0.12% 98.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 5 0.06% 98.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.04% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 27 0.35% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 13 0.17% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.05% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.14% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 10 0.13% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 4 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 2 0.03% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 5 0.06% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 3 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 7 0.09% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 1 0.01% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::220-223 7 0.09% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::248-251 4 0.05% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::252-255 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7811 # Writes before turning the bus around for reads +system.physmem.totQLat 1990259250 # Total ticks spent queuing +system.physmem.totMemAccLat 5466790500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 927075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10734.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29530.07 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29484.08 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s @@ -299,180 +297,180 @@ system.physmem.busUtil 0.04 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.71 # Average write queue length when enqueuing -system.physmem.readRowHits 152292 # Number of row buffer hits during reads -system.physmem.writeRowHits 152229 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.29 # Row buffer hit rate for writes -system.physmem.avgGap 13420738.20 # Average gap between requests -system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 279697320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 152612625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 719316000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 633329280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129572750835 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2964303640500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3430724068320 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.764961 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4931314948000 # Time in different power states -system.physmem_0.memoryStateTime::REF 171299960000 # Time in different power states +system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing +system.physmem.readRowHits 152358 # Number of row buffer hits during reads +system.physmem.writeRowHits 152360 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.32 # Row buffer hit rate for writes +system.physmem.avgGap 13414176.86 # Average gap between requests +system.physmem.pageHitRate 80.20 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 277686360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 151515375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 715759200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 622883520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 129454885665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2962010423250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3428034983850 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.761488 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4927497903250 # Time in different power states +system.physmem_0.memoryStateTime::REF 171166580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27328009000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27281453250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 289487520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 157954500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 726804000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 626447520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 335062721760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129789266760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2964113714250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3430766396310 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.773213 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4930997374750 # Time in different power states -system.physmem_1.memoryStateTime::REF 171299960000 # Time in different power states +system.physmem_1.actEnergy 290765160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 158651625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 730470000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 637450560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 334801830480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 129625961760 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2961860356500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3428105486085 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.775242 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4927247811250 # Time in different power states +system.physmem_1.memoryStateTime::REF 171166580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27642592750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27531190000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86966196 # Number of BP lookups -system.cpu.branchPred.condPredicted 86966196 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 908530 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80060297 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78222813 # Number of BTB hits +system.cpu.branchPred.lookups 87010872 # Number of BP lookups +system.cpu.branchPred.condPredicted 87010872 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 908907 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80241948 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78260393 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.704875 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1554803 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 179885 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.530525 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1567280 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 181222 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449725865 # number of cpu cycles simulated +system.cpu.numCycles 449757362 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27729826 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429316628 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86966196 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79777616 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 417943861 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1905694 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 153883 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 50061 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 216755 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 126625 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 694 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9209956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 450181 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5437 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 447174552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894587 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.051890 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27680627 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429642410 # Number of instructions fetch has processed +system.cpu.fetch.Branches 87010872 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79827673 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 418150440 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1906654 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 150208 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 58666 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 213443 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 140 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 436 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9233721 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 451702 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5158 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 447207287 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.895606 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.052695 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281545500 62.96% 62.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2299594 0.51% 63.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72183543 16.14% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1609599 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2153830 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2329535 0.52% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1534724 0.34% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1901427 0.43% 81.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81616800 18.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281559277 62.96% 62.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2214583 0.50% 63.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72218429 16.15% 79.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1625336 0.36% 79.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2151026 0.48% 80.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2311115 0.52% 80.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1533968 0.34% 81.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1910699 0.43% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81682854 18.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 447174552 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193376 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954618 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23090202 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264882686 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150813511 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7435306 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 952847 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838903899 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 952847 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25942831 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223326641 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13232428 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154708804 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29011001 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 835406292 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 477425 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12418228 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 176585 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13740194 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997876395 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1814508658 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1115444420 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 102 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964480017 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33396376 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 469202 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 473127 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39031385 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17359783 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10198929 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1317086 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1098616 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829832373 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1210818 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824505871 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 240863 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23642425 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36460999 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 154878 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 447174552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.843812 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418056 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 447207287 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193462 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.955276 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23009193 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264931793 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150859313 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7453661 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 953327 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 839350026 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 953327 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25875798 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 223334745 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13198087 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154759437 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29085893 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 835811014 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 482001 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12419616 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 206377 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 13783403 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 998347758 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1815644422 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1116079946 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 122 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964783456 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33564300 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 467714 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 471747 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 39093495 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17396694 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10208602 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1304613 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1095322 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 830247357 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1203823 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824890478 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 241321 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23772173 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36627244 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 152885 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 447207287 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.844537 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418419 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262851560 58.78% 58.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13883927 3.10% 61.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10098896 2.26% 64.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6926055 1.55% 65.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74362880 16.63% 82.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4459374 1.00% 83.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72818710 16.28% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1199863 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 573287 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262823455 58.77% 58.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13859186 3.10% 61.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10127573 2.26% 64.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6921797 1.55% 65.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74369123 16.63% 82.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4467728 1.00% 83.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72848553 16.29% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1214671 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 575201 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 447174552 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 447207287 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1983031 71.93% 71.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 252 0.01% 71.94% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1287 0.05% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.99% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 612199 22.21% 94.19% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160068 5.81% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2002012 72.04% 72.04% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 252 0.01% 72.05% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1516 0.05% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 615311 22.14% 94.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160020 5.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 294191 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796088573 96.55% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150664 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125614 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 292641 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 796440241 96.55% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150873 0.02% 96.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125700 0.02% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued @@ -499,98 +497,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18441786 2.24% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9405043 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18469737 2.24% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9411286 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824505871 # Type of FU issued -system.cpu.iq.rate 1.833352 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2756837 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003344 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2099183812 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854698119 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819923286 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 181 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 182 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 50 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826968435 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 82 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1878873 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824890478 # Type of FU issued +system.cpu.iq.rate 1.834079 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2779111 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003369 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2100008470 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 855235960 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 820301631 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 204 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 226 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 827376851 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 97 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1872015 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3357342 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 15595 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14483 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1769318 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3394675 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 15480 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14595 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1778587 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224742 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72242 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2224947 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 72059 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 952847 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205624678 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9408932 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831043191 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 186605 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17359783 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10198929 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 713805 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 415277 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8093737 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14483 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 519848 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 541033 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1060881 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822872781 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18039155 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1498773 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 953327 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205633916 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9395655 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 831451180 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 157138 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17396694 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10208602 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 706837 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 415978 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8079838 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14595 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 523025 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 540470 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1063495 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 823253062 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18064803 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1501922 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27216659 # number of memory reference insts executed -system.cpu.iew.exec_branches 83327917 # Number of branches executed -system.cpu.iew.exec_stores 9177504 # Number of stores executed -system.cpu.iew.exec_rate 1.829721 # Inst execution rate -system.cpu.iew.wb_sent 822362005 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819923336 # cumulative count of insts written-back -system.cpu.iew.wb_producers 641186937 # num instructions producing a value -system.cpu.iew.wb_consumers 1050770759 # num instructions consuming a value +system.cpu.iew.exec_refs 27249763 # number of memory reference insts executed +system.cpu.iew.exec_branches 83367725 # Number of branches executed +system.cpu.iew.exec_stores 9184960 # Number of stores executed +system.cpu.iew.exec_rate 1.830438 # Inst execution rate +system.cpu.iew.wb_sent 822742058 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 820301688 # cumulative count of insts written-back +system.cpu.iew.wb_producers 641478984 # num instructions producing a value +system.cpu.iew.wb_consumers 1051241156 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823163 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610206 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823876 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610211 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24478012 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1055940 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 920864 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443494014 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.818449 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675035 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24588739 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1050938 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 921334 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443513076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818961 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675251 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272650089 61.48% 61.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11209358 2.53% 64.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3583153 0.81% 64.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74560256 16.81% 81.63% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2436163 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1608243 0.36% 82.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 951229 0.21% 82.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71042725 16.02% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5452798 1.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272623912 61.47% 61.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11196719 2.52% 63.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3582296 0.81% 64.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74597527 16.82% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2432522 0.55% 82.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1609310 0.36% 82.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 947533 0.21% 82.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71068767 16.02% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5454490 1.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443494014 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407987808 # Number of instructions committed -system.cpu.commit.committedOps 806471132 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443513076 # Number of insts commited each cycle +system.cpu.commit.committedInsts 408140259 # Number of instructions committed +system.cpu.commit.committedOps 806733017 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22432051 # Number of memory references committed -system.cpu.commit.loads 14002440 # Number of loads committed -system.cpu.commit.membars 475347 # Number of memory barriers committed -system.cpu.commit.branches 82201961 # Number of branches committed +system.cpu.commit.refs 22432033 # Number of memory references committed +system.cpu.commit.loads 14002018 # Number of loads committed +system.cpu.commit.membars 475437 # Number of memory barriers committed +system.cpu.commit.branches 82233213 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735281139 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155976 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174273 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783598184 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 145019 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121605 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735520454 # Number of committed integer instructions. +system.cpu.commit.function_calls 1156067 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171671 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783865362 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 145082 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121451 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -617,167 +615,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 14002440 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8429611 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13999436 1.74% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8430015 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806471132 # Class of committed instruction -system.cpu.commit.bw_lim_events 5452798 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806733017 # Class of committed instruction +system.cpu.commit.bw_lim_events 5454490 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1268912158 # The number of ROB reads -system.cpu.rob.rob_writes 1665595320 # The number of ROB writes -system.cpu.timesIdled 297665 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2551313 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9810160420 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407987808 # Number of Instructions Simulated -system.cpu.committedOps 806471132 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.102302 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.102302 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907192 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907192 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092777925 # number of integer regfile reads -system.cpu.int_regfile_writes 656276714 # number of integer regfile writes -system.cpu.fp_regfile_reads 50 # number of floating regfile reads -system.cpu.cc_regfile_reads 416321461 # number of cc regfile reads -system.cpu.cc_regfile_writes 322134346 # number of cc regfile writes -system.cpu.misc_regfile_reads 265712042 # number of misc regfile reads -system.cpu.misc_regfile_writes 402822 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1660901 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996168 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19148306 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1661413 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.525314 # Average number of references to valid blocks. +system.cpu.rob.rob_reads 1269302111 # The number of ROB reads +system.cpu.rob.rob_writes 1666357608 # The number of ROB writes +system.cpu.timesIdled 293383 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2550075 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9802132382 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 408140259 # Number of Instructions Simulated +system.cpu.committedOps 806733017 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.101968 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.101968 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907468 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907468 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1093345902 # number of integer regfile reads +system.cpu.int_regfile_writes 656583711 # number of integer regfile writes +system.cpu.fp_regfile_reads 57 # number of floating regfile reads +system.cpu.cc_regfile_reads 416569502 # number of cc regfile reads +system.cpu.cc_regfile_writes 322266839 # number of cc regfile writes +system.cpu.misc_regfile_reads 265844677 # number of misc regfile reads +system.cpu.misc_regfile_writes 400270 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1661069 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.997995 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19180634 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1661581 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.543605 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996168 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.997995 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 221 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88407170 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88407170 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10993462 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10993462 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8086554 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8086554 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 65615 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 65615 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19080016 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19080016 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19145631 # number of overall hits -system.cpu.dcache.overall_hits::total 19145631 # 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average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18618.500128 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18618.500128 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17465.385131 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17465.385131 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -785,58 +783,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 74149 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.785870 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 117599 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 74165 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.585640 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 219591309000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.785870 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986617 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986617 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 76914 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.799700 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 113377 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 76929 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.473788 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 194539504500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.799700 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.987481 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.987481 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 460921 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 460921 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 117599 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 117599 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 117599 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 117599 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 117599 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 117599 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75241 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 75241 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75241 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 75241 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75241 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 75241 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935995702 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935995702 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935995702 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 935995702 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935995702 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 935995702 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192840 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 192840 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192840 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 192840 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192840 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 192840 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.390173 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.390173 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.390173 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.390173 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.390173 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.390173 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12439.968927 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12439.968927 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12439.968927 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12439.968927 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12439.968927 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 460761 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 460761 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 113400 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 113400 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 113400 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 113400 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 113400 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 113400 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77987 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 77987 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77987 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 77987 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77987 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 77987 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 949066206 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 949066206 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 949066206 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 949066206 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 949066206 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 949066206 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191387 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 191387 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191387 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 191387 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191387 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 191387 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.407483 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.407483 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.407483 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.407483 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.407483 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.407483 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12169.543719 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12169.543719 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12169.543719 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12169.543719 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12169.543719 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -845,180 +843,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 14429 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 14429 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75241 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75241 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75241 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 75241 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75241 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 75241 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 785378468 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 785378468 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 785378468 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 785378468 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 785378468 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 785378468 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.390173 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.390173 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.390173 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.390173 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10438.171582 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10438.171582 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10438.171582 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 21202 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21202 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77987 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77987 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77987 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 77987 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77987 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 77987 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 792970936 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 792970936 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 792970936 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 792970936 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 792970936 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 792970936 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.407483 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.407483 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.407483 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.407483 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10167.988716 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10167.988716 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10167.988716 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1000738 # number of replacements -system.cpu.icache.tags.tagsinuse 509.865289 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8144093 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1001250 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.133926 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147645528250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.865289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995831 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995831 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 998047 # number of replacements +system.cpu.icache.tags.tagsinuse 509.614894 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8172291 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 998559 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.184084 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147683889250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.614894 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995342 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995342 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 178 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10211253 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10211253 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8144093 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8144093 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8144093 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8144093 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8144093 # number of overall hits -system.cpu.icache.overall_hits::total 8144093 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1065861 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1065861 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1065861 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1065861 # 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number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9209954 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9209954 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9209954 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115729 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115729 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115729 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115729 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115729 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115729 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13867.840247 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13867.840247 # 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number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108149 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.108149 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108149 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.108149 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.508213 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.508213 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.508213 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.508213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.508213 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.508213 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 16111 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.022557 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 25852 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 16125 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.603225 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5103942671000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.022557 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.376410 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.376410 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.replacements 15839 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.015286 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 25359 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 15853 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.599634 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5101686667000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.015286 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375955 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.375955 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 102724 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 102724 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25863 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25863 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.tag_accesses 101130 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 101130 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25498 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25498 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25865 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25865 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25865 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25865 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16998 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 16998 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16998 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 16998 # 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number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25500 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25500 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25500 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25500 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 16710 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 16710 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 16710 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 16710 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 16710 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 16710 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 189443244 # 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miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.395897 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.395878 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.395878 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.395878 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.395878 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11337.118133 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11337.118133 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11337.118133 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11337.118133 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11337.118133 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11337.118133 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1027,177 +1025,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2256 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2256 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16998 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16998 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16998 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 16998 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16998 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 16998 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 168025032 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 168025032 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 168025032 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 168025032 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 168025032 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 168025032 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.396584 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.396584 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.396566 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.396566 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.396566 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9884.988352 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9884.988352 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9884.988352 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3245 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3245 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 16710 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 16710 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 16710 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 16710 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 16710 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 16710 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 156005776 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 156005776 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 156005776 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 156005776 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 156005776 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 156005776 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.395897 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.395897 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.395878 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.395878 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.395878 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.395878 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9336.072771 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9336.072771 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9336.072771 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9336.072771 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112974 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64818.744711 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3837920 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 177018 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.680959 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112952 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64819.666116 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3838789 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176912 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.698862 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50388.015751 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.441797 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.125760 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3267.225445 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11145.935958 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768860 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000266 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50506.549042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 19.197840 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3269.774951 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11024.008903 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.770669 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000293 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049854 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170073 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989056 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64044 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 598 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3343 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7275 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52773 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977234 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 35081259 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 35081259 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69593 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 14758 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 984803 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1337710 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2406864 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1577834 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1577834 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 300 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 300 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 153385 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 153385 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 69593 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 14758 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 984803 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1491095 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2560249 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 69593 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 14758 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 984803 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1491095 # number of overall hits -system.cpu.l2cache.overall_hits::total 2560249 # number of overall hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049893 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.168213 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989070 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63960 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 594 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3359 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5550 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54407 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975952 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 35127054 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 35127054 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69856 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13439 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 982174 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1337175 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2402644 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1586883 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1586883 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 154161 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154161 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 69856 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 13439 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 982174 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1491336 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2556805 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 69856 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 13439 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 982174 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1491336 # number of overall hits +system.cpu.l2cache.overall_hits::total 2556805 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 68 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16393 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35895 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52361 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133756 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133756 # number of ReadExReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16339 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 35825 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 52237 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1483 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1483 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133848 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133848 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 68 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16393 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169651 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 186117 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16339 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169673 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 186085 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 68 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16393 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169651 # number of overall misses -system.cpu.l2cache.overall_misses::total 186117 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6414250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 407500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1255247500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2834689998 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4096759248 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17266314 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17266314 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9330791213 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9330791213 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6414250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 407500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1255247500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12165481211 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13427550461 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6414250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 407500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1255247500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12165481211 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13427550461 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69661 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 14763 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1001196 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1373605 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2459225 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1577834 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1577834 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1744 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1744 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287141 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287141 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69661 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 14763 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1001196 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1660746 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2746366 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69661 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 14763 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1001196 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1660746 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2746366 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000976 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000339 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016373 # 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average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 82003.676471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68900 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64031.707540 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59182.976528 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.627750 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16337 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169670 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 186080 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5240250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 330750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1042946750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2388969999 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3437487749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15771463 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15771463 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7656264290 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7656264290 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5240250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 330750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1042946750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10045234289 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11093752039 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5240250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 330750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1042946750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10045234289 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11093752039 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89281194000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89281194000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401486500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401486500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91682680500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91682680500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026090 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021277 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.827567 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.827567 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464735 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464735 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102149 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067841 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000972 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000372 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016361 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102149 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067841 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66150 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63839.551325 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66690.022863 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65811.911261 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10634.836817 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10634.836817 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57201.185599 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57201.185599 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66150 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63839.551325 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59204.539925 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59618.185936 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77062.500000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66150 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63839.551325 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59204.539925 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59618.185936 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1306,63 +1304,63 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3078150 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3077612 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13891 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13891 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1577834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3077249 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3076704 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13905 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1586883 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2215 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2215 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002495 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6134281 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34017 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 159331 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8330124 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64076544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208017731 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1089216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5381760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278565251 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 57093 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4382652 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010869 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103688 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeReq 2235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2235 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 288016 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 288016 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 9 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1997133 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6136134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 33399 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 169113 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8335779 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63904832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208116125 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1068096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5832064 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278921117 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 60473 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4391663 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010846 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103577 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4335015 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47637 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4344032 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47631 1.08% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4382652 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4064000382 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4391663 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4077594873 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 577500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 562500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1506120456 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1502063776 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3144694054 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3145123125 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 25505983 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 25073734 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 112929117 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 117041135 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 225688 # Transaction distribution -system.iobus.trans_dist::ReadResp 225688 # Transaction distribution -system.iobus.trans_dist::WriteReq 57721 # Transaction distribution -system.iobus.trans_dist::WriteResp 11001 # Transaction distribution +system.iobus.trans_dist::ReadReq 225706 # Transaction distribution +system.iobus.trans_dist::ReadResp 225706 # Transaction distribution +system.iobus.trans_dist::WriteReq 57738 # Transaction distribution +system.iobus.trans_dist::WriteResp 11018 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1644 # Transaction distribution -system.iobus.trans_dist::MessageResp 1644 # Transaction distribution +system.iobus.trans_dist::MessageReq 1643 # Transaction distribution +system.iobus.trans_dist::MessageResp 1643 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) @@ -1372,21 +1370,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27824 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95274 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95274 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 570106 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471626 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95262 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 570174 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) @@ -1396,25 +1394,25 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276514 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3918684 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 242096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027832 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3915656 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1434,7 +1432,7 @@ system.iobus.reqLayer11.occupancy 170000 # La system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 20719000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 20815000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) @@ -1444,54 +1442,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448342458 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 448351206 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 460608000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52374503 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52362260 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47582 # number of replacements -system.iocache.tags.tagsinuse 0.103930 # Cycle average of tags in use +system.iocache.tags.replacements 47576 # number of replacements +system.iocache.tags.tagsinuse 0.091535 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47592 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992992710000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103930 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006496 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006496 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992994629000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091535 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005721 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005721 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428733 # Number of tag accesses -system.iocache.tags.data_accesses 428733 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 917 # number of ReadReq misses -system.iocache.ReadReq_misses::total 917 # number of ReadReq misses +system.iocache.tags.tag_accesses 428679 # Number of tag accesses +system.iocache.tags.data_accesses 428679 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses +system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 917 # number of demand (read+write) misses -system.iocache.demand_misses::total 917 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 917 # number of overall misses -system.iocache.overall_misses::total 917 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152376946 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152376946 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12347668009 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12347668009 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 152376946 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 152376946 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 152376946 # number of overall miss cycles -system.iocache.overall_miss_latency::total 152376946 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 917 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 917 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 911 # number of demand (read+write) misses +system.iocache.demand_misses::total 911 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 911 # number of overall misses +system.iocache.overall_misses::total 911 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 147981947 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 147981947 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12360245999 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 12360245999 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 147981947 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 147981947 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 147981947 # number of overall miss cycles +system.iocache.overall_miss_latency::total 147981947 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 911 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 911 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 917 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 917 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 917 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 917 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 911 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 911 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 911 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 911 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1500,40 +1498,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 166168.970556 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264290.839234 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264290.839234 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 166168.970556 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 166168.970556 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 166168.970556 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70541 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 162439.019759 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264560.059910 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264560.059910 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 162439.019759 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162439.019759 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 162439.019759 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 70832 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9150 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9173 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.709399 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.721792 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 917 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 917 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 911 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 911 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 917 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 917 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 917 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 917 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104665946 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9918222015 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9918222015 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 104665946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104665946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 104665946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 911 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 911 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 911 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 911 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 100584447 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9930786019 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9930786019 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 100584447 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100584447 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 100584447 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1542,75 +1540,75 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 114139.526718 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212290.710938 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212290.710938 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 114139.526718 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 114139.526718 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 110411.028540 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212559.632256 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212559.632256 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110411.028540 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 110411.028540 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 662691 # Transaction distribution -system.membus.trans_dist::ReadResp 662685 # Transaction distribution -system.membus.trans_dist::WriteReq 13891 # Transaction distribution -system.membus.trans_dist::WriteResp 13891 # Transaction distribution -system.membus.trans_dist::Writeback 149916 # Transaction distribution +system.membus.trans_dist::ReadReq 662583 # Transaction distribution +system.membus.trans_dist::ReadResp 662574 # Transaction distribution +system.membus.trans_dist::WriteReq 13905 # Transaction distribution +system.membus.trans_dist::WriteResp 13905 # Transaction distribution +system.membus.trans_dist::Writeback 149854 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2202 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1731 # Transaction distribution -system.membus.trans_dist::ReadExReq 133471 # Transaction distribution -system.membus.trans_dist::ReadExResp 133469 # Transaction distribution -system.membus.trans_dist::MessageReq 1644 # Transaction distribution -system.membus.trans_dist::MessageResp 1644 # Transaction distribution -system.membus.trans_dist::BadAddressError 6 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478147 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724773 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1869528 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18458240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20250435 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2216 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1773 # Transaction distribution +system.membus.trans_dist::ReadExReq 133558 # Transaction distribution +system.membus.trans_dist::ReadExResp 133558 # Transaction distribution +system.membus.trans_dist::MessageReq 1643 # Transaction distribution +system.membus.trans_dist::MessageResp 1643 # Transaction distribution +system.membus.trans_dist::BadAddressError 9 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471626 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775064 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 18 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724758 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141461 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141461 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1869505 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242096 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550125 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18451136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20243357 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26262131 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1626 # Total snoops (count) -system.membus.snoop_fanout::samples 385584 # Request fanout histogram +system.membus.pkt_size::total 26255049 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1599 # Total snoops (count) +system.membus.snoop_fanout::samples 385491 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 385584 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 385491 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 385584 # Request fanout histogram -system.membus.reqLayer0.occupancy 251730500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 385491 # Request fanout histogram +system.membus.reqLayer0.occupancy 251614500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583066500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583372000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1995956000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1995485500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 7000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3161502789 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3161579497 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54989497 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 54941740 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal index 95ff094ce..640ecede9 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal @@ -40,12 +40,13 @@ Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
+using mwait in idle threads.
CPU: Fake M5 x86_64 CPU stepping 01
ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812560
+result 7812558
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index b8b0e9f76..dab7e71e5 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -138,6 +138,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -188,6 +189,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 @@ -1223,6 +1225,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 @@ -1258,6 +1261,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json index 0df868e7b..a259a8af3 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.json @@ -34,6 +34,7 @@ "mshrs": 20, "forward_snoops": true, "hit_latency": 20, + "demand_mshr_reserve": 1, "tgts_per_mshr": 12, "addr_ranges": [ "0:18446744073709551615" @@ -657,6 +658,7 @@ "mshrs": 20, "forward_snoops": false, "hit_latency": 50, + "demand_mshr_reserve": 1, "tgts_per_mshr": 12, "addr_ranges": [ "0:134217727" @@ -1810,6 +1812,7 @@ "mshrs": 4, "forward_snoops": true, "hit_latency": 2, + "demand_mshr_reserve": 1, "tgts_per_mshr": 20, "addr_ranges": [ "0:18446744073709551615" @@ -1919,6 +1922,7 @@ "mshrs": 4, "forward_snoops": true, "hit_latency": 2, + "demand_mshr_reserve": 1, "tgts_per_mshr": 20, "addr_ranges": [ "0:18446744073709551615" diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 2cf33b630..c98b760d2 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -3,8 +3,83 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Reading current count from inactive timer. warn: Don't know what interrupt to clear for console. +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 +warn: x86 cpuid: unknown family 0x8086 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 10068, Bank: 3 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 11067, Bank: 2 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 6494, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 6532, Bank: 6 +WARNING: Bank is already active! +Command: 0, Timestamp: 6448, Bank: 5 +WARNING: Bank is already active! +Command: 0, Timestamp: 6448, Bank: 2 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 11102, Bank: 3 +WARNING: Bank is already active! +Command: 0, Timestamp: 7271, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 8628, Bank: 5 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: Tried to clear PCI interrupt 14 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: Unknown mouse command 0xe1. +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: instruction 'wbinvd' unimplemented +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index d4863e151..7bea79dd6 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,8 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 19 2014 14:40:22 -gem5 started Nov 19 2014 14:41:52 +gem5 compiled Jan 6 2015 22:19:56 +gem5 started Jan 6 2015 22:27:08 gem5 executing on gabeblackz620.mtv.corp.google.com command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re /usr/local/google/home/gabeblack/gem5/hg/gem5/tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 039ebcc95..767b8b8bc 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,152 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.136081 # Number of seconds simulated -sim_ticks 5136081138000 # Number of ticks simulated -final_tick 5136081138000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.142213 # Number of seconds simulated +sim_ticks 5142212861500 # Number of ticks simulated +final_tick 5142212861500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 275445 # Simulator instruction rate (inst/s) -host_op_rate 547622 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5813086840 # Simulator tick rate (ticks/s) -host_mem_usage 1006240 # Number of bytes of host memory used -host_seconds 883.54 # Real time elapsed on the host -sim_insts 243366027 # Number of instructions simulated -sim_ops 483844707 # Number of ops (including micro ops) simulated +host_inst_rate 316771 # Simulator instruction rate (inst/s) +host_op_rate 629731 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6695034949 # Simulator tick rate (ticks/s) +host_mem_usage 960996 # Number of bytes of host memory used +host_seconds 768.06 # Real time elapsed on the host +sim_insts 243300298 # Number of instructions simulated +sim_ops 483673350 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 488576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5525632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 145728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1937472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1792 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 336128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2922880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 424320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5246720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 163840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2163392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 379584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2979328 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11386880 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 488576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 145728 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 336128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 970432 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9156352 # Number of bytes written to this memory -system.physmem.bytes_written::total 9156352 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7634 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 86338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2277 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 30273 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 28 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5252 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 45670 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11387840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 424320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 163840 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 379584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 967744 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9172160 # Number of bytes written to this memory +system.physmem.bytes_written::total 9172160 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6630 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 81980 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2560 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33803 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5931 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 46552 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177920 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143068 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143068 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 95126 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1075846 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 28373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 377228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 65444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 569088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5520 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2217037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 95126 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 28373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 65444 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1782751 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1782751 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1782751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 95126 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1075846 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 28373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 377228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 65444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 569088 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5520 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3999787 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 83943 # Number of read requests accepted -system.physmem.writeReqs 110041 # Number of write requests accepted -system.physmem.readBursts 83943 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 110041 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5367872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4480 # Total number of bytes read from write queue -system.physmem.bytesWritten 6959552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5372352 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7042624 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 70 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1298 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 825 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5657 # Per bank write bursts -system.physmem.perBankRdBursts::1 4325 # Per bank write bursts -system.physmem.perBankRdBursts::2 4452 # Per bank write bursts -system.physmem.perBankRdBursts::3 6002 # Per bank write bursts -system.physmem.perBankRdBursts::4 5499 # Per bank write bursts -system.physmem.perBankRdBursts::5 4854 # Per bank write bursts -system.physmem.perBankRdBursts::6 4847 # Per bank write bursts -system.physmem.perBankRdBursts::7 4597 # Per bank write bursts -system.physmem.perBankRdBursts::8 5338 # Per bank write bursts -system.physmem.perBankRdBursts::9 5444 # Per bank write bursts -system.physmem.perBankRdBursts::10 5075 # Per bank write bursts -system.physmem.perBankRdBursts::11 5197 # Per bank write bursts -system.physmem.perBankRdBursts::12 5244 # Per bank write bursts -system.physmem.perBankRdBursts::13 6205 # Per bank write bursts -system.physmem.perBankRdBursts::14 5705 # Per bank write bursts -system.physmem.perBankRdBursts::15 5432 # Per bank write bursts -system.physmem.perBankWrBursts::0 8070 # Per bank write bursts -system.physmem.perBankWrBursts::1 6584 # Per bank write bursts -system.physmem.perBankWrBursts::2 6149 # Per bank write bursts -system.physmem.perBankWrBursts::3 7200 # Per bank write bursts -system.physmem.perBankWrBursts::4 7057 # Per bank write bursts -system.physmem.perBankWrBursts::5 6223 # Per bank write bursts -system.physmem.perBankWrBursts::6 6693 # Per bank write bursts -system.physmem.perBankWrBursts::7 6492 # Per bank write bursts -system.physmem.perBankWrBursts::8 6300 # Per bank write bursts -system.physmem.perBankWrBursts::9 6374 # Per bank write bursts -system.physmem.perBankWrBursts::10 7150 # Per bank write bursts -system.physmem.perBankWrBursts::11 7064 # Per bank write bursts -system.physmem.perBankWrBursts::12 7000 # Per bank write bursts -system.physmem.perBankWrBursts::13 7706 # Per bank write bursts -system.physmem.perBankWrBursts::14 6569 # Per bank write bursts -system.physmem.perBankWrBursts::15 6112 # Per bank write bursts +system.physmem.num_reads::total 177935 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143315 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143315 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82517 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1020323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 31862 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 420712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 579386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5514 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2214580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82517 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 31862 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73817 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188196 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1783699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1783699 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1783699 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82517 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1020323 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 31862 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 420712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 579386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3998279 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 88878 # Number of read requests accepted +system.physmem.writeReqs 113942 # Number of write requests accepted +system.physmem.readBursts 88878 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 113942 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5683264 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4928 # Total number of bytes read from write queue +system.physmem.bytesWritten 7207296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5688192 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7292288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 77 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 1310 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 940 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5243 # Per bank write bursts +system.physmem.perBankRdBursts::1 4719 # Per bank write bursts +system.physmem.perBankRdBursts::2 5104 # Per bank write bursts +system.physmem.perBankRdBursts::3 5729 # Per bank write bursts +system.physmem.perBankRdBursts::4 5898 # Per bank write bursts +system.physmem.perBankRdBursts::5 5027 # Per bank write bursts +system.physmem.perBankRdBursts::6 5470 # Per bank write bursts +system.physmem.perBankRdBursts::7 5567 # Per bank write bursts +system.physmem.perBankRdBursts::8 5651 # Per bank write bursts +system.physmem.perBankRdBursts::9 5723 # Per bank write bursts +system.physmem.perBankRdBursts::10 5167 # Per bank write bursts +system.physmem.perBankRdBursts::11 5483 # Per bank write bursts +system.physmem.perBankRdBursts::12 5886 # Per bank write bursts +system.physmem.perBankRdBursts::13 6693 # Per bank write bursts +system.physmem.perBankRdBursts::14 5960 # Per bank write bursts +system.physmem.perBankRdBursts::15 5481 # Per bank write bursts +system.physmem.perBankWrBursts::0 7238 # Per bank write bursts +system.physmem.perBankWrBursts::1 6716 # Per bank write bursts +system.physmem.perBankWrBursts::2 7069 # Per bank write bursts +system.physmem.perBankWrBursts::3 6723 # Per bank write bursts +system.physmem.perBankWrBursts::4 7013 # Per bank write bursts +system.physmem.perBankWrBursts::5 6703 # Per bank write bursts +system.physmem.perBankWrBursts::6 6619 # Per bank write bursts +system.physmem.perBankWrBursts::7 7556 # Per bank write bursts +system.physmem.perBankWrBursts::8 6486 # Per bank write bursts +system.physmem.perBankWrBursts::9 6985 # Per bank write bursts +system.physmem.perBankWrBursts::10 6508 # Per bank write bursts +system.physmem.perBankWrBursts::11 6763 # Per bank write bursts +system.physmem.perBankWrBursts::12 7496 # Per bank write bursts +system.physmem.perBankWrBursts::13 7338 # Per bank write bursts +system.physmem.perBankWrBursts::14 7696 # Per bank write bursts +system.physmem.perBankWrBursts::15 7705 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5132269646500 # Total gap between requests +system.physmem.totGap 5141212728000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 83943 # Read request sizes (log2) +system.physmem.readPktSize::6 88878 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 110041 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 78296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4371 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 113942 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 84289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 3858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 535 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 0 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39516 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.960320 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.025881 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 337.744102 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15369 38.89% 38.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9220 23.33% 62.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3764 9.53% 71.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2091 5.29% 77.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1514 3.83% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 970 2.45% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 639 1.62% 84.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 601 1.52% 86.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5348 13.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39516 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4123 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 20.342712 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 185.525630 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4120 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 41455 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 310.951538 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.940976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 336.089751 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16126 38.90% 38.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9571 23.09% 61.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4083 9.85% 71.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2278 5.50% 77.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1502 3.62% 80.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1068 2.58% 83.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 718 1.73% 85.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 598 1.44% 86.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5511 13.29% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41455 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4333 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.493423 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 181.058580 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 4330 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-6655 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4123 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4123 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.374727 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.353037 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.922743 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 71 1.72% 1.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 7 0.17% 1.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 3190 77.37% 79.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 194 4.71% 83.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 131 3.18% 87.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 35 0.85% 87.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 132 3.20% 91.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 15 0.36% 91.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 23 0.56% 92.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 42 1.02% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 60 1.46% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 20 0.49% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 93 2.26% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.19% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 26 0.63% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 5 0.12% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 22 0.53% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 8 0.19% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 11 0.27% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 2 0.05% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 5 0.12% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.07% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.07% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.07% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 2 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.12% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.10% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4123 # Writes before turning the bus around for reads -system.physmem.totQLat 931934250 # Total ticks spent queuing -system.physmem.totMemAccLat 2504553000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 419365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11111.25 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4333 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4333 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.989845 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.182522 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 26.410005 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 65 1.50% 1.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 6 0.14% 1.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 7 0.16% 1.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3364 77.64% 79.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 26 0.60% 80.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 23 0.53% 80.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 179 4.13% 84.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 85 1.96% 86.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 35 0.81% 87.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 25 0.58% 88.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 23 0.53% 88.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 117 2.70% 91.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 7 0.16% 91.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.09% 91.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 4 0.09% 91.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 14 0.32% 91.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.21% 92.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.23% 92.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 35 0.81% 93.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 78 1.80% 95.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.05% 95.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 4 0.09% 95.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 7 0.16% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 92 2.12% 97.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 97.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 7 0.16% 97.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 24 0.55% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.07% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 4 0.09% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.32% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 4 0.09% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.12% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.16% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 6 0.14% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.07% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 3 0.07% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 3 0.07% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.05% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.07% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 2 0.05% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.05% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.05% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 3 0.07% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::212-215 2 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 2 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::228-231 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4333 # Writes before turning the bus around for reads +system.physmem.totQLat 976769250 # Total ticks spent queuing +system.physmem.totMemAccLat 2641788000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 444005000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10999.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29861.25 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.36 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.37 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29749.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.40 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.42 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.18 # Average write queue length when enqueuing -system.physmem.readRowHits 66618 # Number of row buffer hits during reads -system.physmem.writeRowHits 86482 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.53 # Row buffer hit rate for writes -system.physmem.avgGap 26457180.21 # Average gap between requests -system.physmem.pageHitRate 79.48 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 145862640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 79389750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 313817400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 352952640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250172869440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 94379716215 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2235135422250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2580580030335 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.988936 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3685687946000 # Time in different power states -system.physmem_0.memoryStateTime::REF 127900240000 # Time in different power states +system.physmem.avgWrQLen 10.09 # Average write queue length when enqueuing +system.physmem.readRowHits 70835 # Number of row buffer hits during reads +system.physmem.writeRowHits 89124 # Number of row buffer hits during writes +system.physmem.readRowHitRate 79.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.13 # Row buffer hit rate for writes +system.physmem.avgGap 25348647.71 # Average gap between requests +system.physmem.pageHitRate 79.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 153097560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 83370375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 333504600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 360527760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250475462640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 95043085920 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2239708824000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2586157872855 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.947189 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3689335375500 # Time in different power states +system.physmem_0.memoryStateTime::REF 128054940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17077044750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17909174750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 152878320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 83263125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 340392000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 351702000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250172869440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95036922225 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2235169487250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2581307514360 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.001289 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3684742447500 # Time in different power states -system.physmem_1.memoryStateTime::REF 127900240000 # Time in different power states +system.physmem_1.actEnergy 160302240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 87313875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 359135400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 369210960 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250475462640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95555045385 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2233887892500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2580894363000 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.132718 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3688582993750 # Time in different power states +system.physmem_1.memoryStateTime::REF 128054940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18039817250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18657353000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 818737889 # number of cpu cycles simulated +system.cpu0.numCycles 905515045 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71815441 # Number of instructions committed -system.cpu0.committedOps 146372002 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134241940 # Number of integer alu accesses +system.cpu0.committedInsts 71354866 # Number of instructions committed +system.cpu0.committedOps 145718889 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 133579753 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 946109 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14229680 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134241940 # number of integer instructions +system.cpu0.num_func_calls 936391 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14189595 # number of instructions that are conditional controls +system.cpu0.num_int_insts 133579753 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 246318200 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115340862 # number of times the integer registers were written +system.cpu0.num_int_register_reads 244625676 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114972528 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83590760 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55777582 # number of times the CC registers were written -system.cpu0.num_mem_refs 13734986 # number of memory refs -system.cpu0.num_load_insts 10122778 # Number of load instructions -system.cpu0.num_store_insts 3612208 # Number of store instructions -system.cpu0.num_idle_cycles 777021055.677311 # Number of idle cycles -system.cpu0.num_busy_cycles 41716833.322689 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050953 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949047 # Percentage of idle cycles -system.cpu0.Branches 15525387 # Number of branches fetched -system.cpu0.op_class::No_OpClass 95218 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 132436366 90.48% 90.54% # Class of executed instruction -system.cpu0.op_class::IntMult 58371 0.04% 90.58% # Class of executed instruction -system.cpu0.op_class::IntDiv 47638 0.03% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.62% # Class of executed instruction -system.cpu0.op_class::MemRead 10122778 6.92% 97.53% # Class of executed instruction -system.cpu0.op_class::MemWrite 3612208 2.47% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 83222516 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55621681 # number of times the CC registers were written +system.cpu0.num_mem_refs 13385296 # number of memory refs +system.cpu0.num_load_insts 10015665 # Number of load instructions +system.cpu0.num_store_insts 3369631 # Number of store instructions +system.cpu0.num_idle_cycles 858514977.989050 # Number of idle cycles +system.cpu0.num_busy_cycles 47000067.010950 # Number of busy cycles +system.cpu0.not_idle_fraction 0.051904 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.948096 # Percentage of idle cycles +system.cpu0.Branches 15470512 # Number of branches fetched +system.cpu0.op_class::No_OpClass 89016 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 132139784 90.68% 90.74% # Class of executed instruction +system.cpu0.op_class::IntMult 57056 0.04% 90.78% # Class of executed instruction +system.cpu0.op_class::IntDiv 49774 0.03% 90.82% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.82% # Class of executed instruction +system.cpu0.op_class::MemRead 10013957 6.87% 97.69% # Class of executed instruction +system.cpu0.op_class::MemWrite 3369631 2.31% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146372579 # Class of executed instruction +system.cpu0.op_class::total 145719218 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1637223 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999462 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19645241 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1637735 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 11.995372 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1638885 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999440 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19690308 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1639397 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.010701 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 126.457209 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 281.700690 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 103.841562 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.246987 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.550197 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.202816 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 129.361524 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 276.707159 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 105.930757 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.252659 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.540444 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.206896 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88377043 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88377043 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4914910 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2565511 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4026210 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11506631 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3467385 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1750714 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2858968 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8077067 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 20221 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10190 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29345 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59756 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8382295 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4316225 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6885178 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19583698 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8402516 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4326415 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6914523 # number of overall hits -system.cpu0.dcache.overall_hits::total 19643454 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 362607 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 162199 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 784843 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1309649 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 140483 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 61206 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 123727 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325416 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 152674 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 62891 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 190739 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406304 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 503090 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 223405 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 908570 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1635065 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 655764 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 286296 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1099309 # number of overall misses -system.cpu0.dcache.overall_misses::total 2041369 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2292566250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12877344029 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15169910279 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2335955064 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3849112259 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6185067323 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4628521314 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 16726456288 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 21354977602 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4628521314 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 16726456288 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 21354977602 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5277517 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2727710 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4811053 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12816280 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3607868 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1811920 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2982695 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8402483 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 172895 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 73081 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 220084 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466060 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8885385 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4539630 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7793748 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21218763 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9058280 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4612711 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 8013832 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21684823 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.068708 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059463 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.163133 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.102186 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.038938 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.033780 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041482 # miss rate for WriteReq accesses +system.cpu0.dcache.tags.tag_accesses 88564731 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88564731 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4814748 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2752692 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 3969504 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11536944 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3244156 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1918293 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2929310 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8091759 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19629 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10883 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29286 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 59798 # number of SoftPFReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8058904 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4670985 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6898814 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19628703 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8078533 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4681868 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6928100 # number of overall hits +system.cpu0.dcache.overall_hits::total 19688501 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 357538 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 167572 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 785074 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1310184 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 120756 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 69485 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 135769 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 326010 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 148495 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 65341 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 192799 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 406635 # number of SoftPFReq misses +system.cpu0.dcache.demand_misses::cpu0.data 478294 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 237057 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 920843 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1636194 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 626789 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 302398 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1113642 # number of overall misses +system.cpu0.dcache.overall_misses::total 2042829 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2347978500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 12373504263 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 14721482763 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2672090343 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4159812296 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9092.366980 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5386 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 268 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 277 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.731343 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.444043 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22336 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 22336 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 22336 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 22336 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 22336 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 22336 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 159327 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 372409 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 531736 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 159327 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 372409 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 531736 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 159327 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 372409 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 531736 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1905663500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4555263703 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6460927203 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1905663500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4555263703 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6460927203 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1905663500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4555263703 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6460927203 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004073 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004073 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004040 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.107652 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004073 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12150.629641 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12150.629641 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11960.706597 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12231.884039 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12150.629641 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 22841 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 22841 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 22841 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 22841 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 22841 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 22841 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 175554 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 376344 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 551898 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 175554 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 376344 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 551898 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 175554 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 376344 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 551898 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2103717250 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4645372892 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 6749090142 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2103717250 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4645372892 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 6749090142 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2103717250 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4645372892 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6749090142 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004220 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004220 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004349 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110562 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004220 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12228.872259 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12228.872259 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11983.305707 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12343.422220 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12228.872259 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2604019962 # number of cpu cycles simulated +system.cpu1.numCycles 2608019043 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35730684 # Number of instructions committed -system.cpu1.committedOps 69408718 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64481893 # Number of integer alu accesses +system.cpu1.committedInsts 36458068 # Number of instructions committed +system.cpu1.committedOps 70720299 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 65779411 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 491880 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6558534 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64481893 # number of integer instructions +system.cpu1.num_func_calls 521390 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6639276 # number of instructions that are conditional controls +system.cpu1.num_int_insts 65779411 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 119402180 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55560948 # number of times the integer registers were written +system.cpu1.num_int_register_reads 122190876 # number of times the integer registers were read +system.cpu1.num_int_register_writes 56554100 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36459460 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27231683 # number of times the CC registers were written -system.cpu1.num_mem_refs 4801643 # number of memory refs -system.cpu1.num_load_insts 2988079 # Number of load instructions -system.cpu1.num_store_insts 1813564 # Number of store instructions -system.cpu1.num_idle_cycles 2476018804.880995 # Number of idle cycles -system.cpu1.num_busy_cycles 128001157.119005 # Number of busy cycles -system.cpu1.not_idle_fraction 0.049155 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.950845 # Percentage of idle cycles -system.cpu1.Branches 7226738 # Number of branches fetched -system.cpu1.op_class::No_OpClass 34859 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64514544 92.95% 93.00% # Class of executed instruction -system.cpu1.op_class::IntMult 31705 0.05% 93.04% # Class of executed instruction -system.cpu1.op_class::IntDiv 26275 0.04% 93.08% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.08% # Class of executed instruction -system.cpu1.op_class::MemRead 2988079 4.31% 97.39% # Class of executed instruction -system.cpu1.op_class::MemWrite 1813564 2.61% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 37054979 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27544073 # number of times the CC registers were written +system.cpu1.num_mem_refs 5171486 # number of memory refs +system.cpu1.num_load_insts 3182631 # Number of load instructions +system.cpu1.num_store_insts 1988855 # Number of store instructions +system.cpu1.num_idle_cycles 2476913850.669656 # Number of idle cycles +system.cpu1.num_busy_cycles 131105192.330343 # Number of busy cycles +system.cpu1.not_idle_fraction 0.050270 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.949730 # Percentage of idle cycles +system.cpu1.Branches 7356329 # Number of branches fetched +system.cpu1.op_class::No_OpClass 36814 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 65455015 92.55% 92.61% # Class of executed instruction +system.cpu1.op_class::IntMult 34008 0.05% 92.65% # Class of executed instruction +system.cpu1.op_class::IntDiv 24962 0.04% 92.69% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.69% # Class of executed instruction +system.cpu1.op_class::MemRead 3181010 4.50% 97.19% # Class of executed instruction +system.cpu1.op_class::MemWrite 1988855 2.81% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69409026 # Class of executed instruction +system.cpu1.op_class::total 70720664 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29092929 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29092929 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 315476 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26409431 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25746575 # Number of BTB hits +system.cpu2.branchPred.lookups 28980045 # Number of BP lookups +system.cpu2.branchPred.condPredicted 28980045 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 316258 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26301179 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25662962 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.490078 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 584007 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63229 # Number of incorrect RAS predictions. -system.cpu2.numCycles 153281353 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.573428 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 575120 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 62760 # Number of incorrect RAS predictions. +system.cpu2.numCycles 153675594 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10494646 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 143459530 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29092929 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26330582 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 141345595 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 659748 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 97189 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 4757 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7888 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 55541 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 2125 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 437 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3459376 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 164097 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3515 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 152337401 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.854593 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.033085 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10522056 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 142983634 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 28980045 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26238082 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 141648223 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 664532 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 102750 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 5712 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8254 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 65359 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 18 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 587 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3403920 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 164909 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3818 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 152684574 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.843447 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.027165 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 97296263 63.87% 63.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 832536 0.55% 64.42% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23575408 15.48% 79.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 586344 0.38% 80.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 814239 0.53% 80.81% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 832677 0.55% 81.36% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 567105 0.37% 81.73% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 704147 0.46% 82.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27128682 17.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 97834881 64.08% 64.08% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 827461 0.54% 64.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23508780 15.40% 80.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 590429 0.39% 80.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 809590 0.53% 80.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 824910 0.54% 81.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 565945 0.37% 81.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 689592 0.45% 82.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27032986 17.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 152337401 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189801 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.935923 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9688238 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93124886 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 23395204 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5013369 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 330525 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 279674043 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 330525 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11836052 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76001562 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4488572 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 26027497 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12868079 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278471354 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 223428 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5927671 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 64367 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4764004 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 332707542 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 607302278 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 372965322 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 116 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320669422 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12038120 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 154906 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 156494 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 24500450 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6532282 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3632430 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 395237 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 325236 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276569941 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 416887 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274532538 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 100855 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8584816 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13350787 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 62925 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 152337401 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.802135 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.398465 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 152684574 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.188579 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.930425 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9666714 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 93465476 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 23018277 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4894255 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 332917 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 278595760 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 332917 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 11754676 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 75764311 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4472306 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 25597731 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 13455764 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 277400530 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 224282 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5843297 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 52985 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 5514893 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 331330378 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 605053013 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 371514373 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 36 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 319639627 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11690749 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 161038 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 162632 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 24003573 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6435164 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3706636 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 363903 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 318629 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 275503234 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 421288 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 273595538 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 103309 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8356083 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12887842 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 64640 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 152684574 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.791900 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.394187 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 89943207 59.04% 59.04% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5345468 3.51% 62.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3937636 2.58% 65.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3657575 2.40% 67.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22350485 14.67% 82.21% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2587133 1.70% 83.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23826816 15.64% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 472076 0.31% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 217005 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 90392452 59.20% 59.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5451363 3.57% 62.77% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3935423 2.58% 65.35% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3565723 2.34% 67.69% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22424664 14.69% 82.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2492768 1.63% 84.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23751475 15.56% 99.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 460834 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 209872 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 152337401 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 152684574 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1755222 86.36% 86.36% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 86.36% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 168 0.01% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 86.37% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 216539 10.65% 97.02% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 60595 2.98% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1676714 85.59% 85.59% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 85.59% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 168 0.01% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 221197 11.29% 96.89% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 60976 3.11% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 75570 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264135020 96.21% 96.24% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 55664 0.02% 96.26% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 49906 0.02% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6866354 2.50% 98.78% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3350024 1.22% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 82248 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 263185371 96.20% 96.23% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 54901 0.02% 96.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 48803 0.02% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6793041 2.48% 98.75% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3431174 1.25% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274532538 # Type of FU issued -system.cpu2.iq.rate 1.791037 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2032524 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007404 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 703535734 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 285575754 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 272952384 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 122 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 212 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 276489433 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 59 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 719306 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 273595538 # Type of FU issued +system.cpu2.iq.rate 1.780345 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1959055 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007160 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 701937961 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 284284863 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 272009603 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 52 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 275472321 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 24 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 698574 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1204229 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6084 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4820 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 645551 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1169867 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6207 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 4815 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 637978 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 756143 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 21686 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 755628 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 24889 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 330525 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70849508 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1741832 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 276986828 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 38338 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6532282 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3632430 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 240586 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 193301 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1249611 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4820 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 179927 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 186201 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 366128 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 273965652 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6730604 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 516589 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 332917 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 70606528 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1760004 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 275924522 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 40123 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6435186 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3706636 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 246888 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 186471 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1275738 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 4815 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 176824 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 191426 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 368250 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 273027006 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6657386 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 516016 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9996676 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27816636 # Number of branches executed -system.cpu2.iew.exec_stores 3266072 # Number of stores executed -system.cpu2.iew.exec_rate 1.787338 # Inst execution rate -system.cpu2.iew.wb_sent 273775485 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 272952416 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 212880444 # num instructions producing a value -system.cpu2.iew.wb_consumers 349125324 # num instructions consuming a value +system.cpu2.iew.exec_refs 10001726 # number of memory reference insts executed +system.cpu2.iew.exec_branches 27723980 # Number of branches executed +system.cpu2.iew.exec_stores 3344340 # Number of stores executed +system.cpu2.iew.exec_rate 1.776645 # Inst execution rate +system.cpu2.iew.wb_sent 272834661 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 272009615 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 211997747 # num instructions producing a value +system.cpu2.iew.wb_consumers 347754146 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.780728 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609754 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.770025 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609620 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8921992 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 353962 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 318190 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 151004847 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.775201 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.653055 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8688913 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356648 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 319605 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 151378980 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.765332 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.647504 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 93801921 62.12% 62.12% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4186228 2.77% 64.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1259762 0.83% 65.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24518557 16.24% 81.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1012800 0.67% 82.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 677237 0.45% 83.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 473264 0.31% 83.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23075029 15.28% 98.68% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 2000049 1.32% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 94244642 62.26% 62.26% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4276340 2.82% 65.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1271564 0.84% 65.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24442364 16.15% 82.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1016704 0.67% 82.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 679552 0.45% 83.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 473445 0.31% 83.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23012596 15.20% 98.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1961773 1.30% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 151004847 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135819902 # Number of instructions committed -system.cpu2.commit.committedOps 268063987 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 151378980 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 135487364 # Number of instructions committed +system.cpu2.commit.committedOps 267234162 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8314932 # Number of memory references committed -system.cpu2.commit.loads 5328053 # Number of loads committed -system.cpu2.commit.membars 161474 # Number of memory barriers committed -system.cpu2.commit.branches 27411077 # Number of branches committed +system.cpu2.commit.refs 8333976 # Number of memory references committed +system.cpu2.commit.loads 5265318 # Number of loads committed +system.cpu2.commit.membars 160044 # Number of memory barriers committed +system.cpu2.commit.branches 27319158 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244897516 # Number of committed integer instructions. -system.cpu2.commit.function_calls 434912 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 44620 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 259602696 96.84% 96.86% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 53542 0.02% 96.88% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 48197 0.02% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5328053 1.99% 98.89% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2986879 1.11% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 244126615 # Number of committed integer instructions. +system.cpu2.commit.function_calls 428007 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 46777 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 258753265 96.83% 96.84% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 52699 0.02% 96.86% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 47480 0.02% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5265283 1.97% 98.85% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3068658 1.15% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 268063987 # Class of committed instruction -system.cpu2.commit.bw_lim_events 2000049 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 267234162 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1961773 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 425964171 # The number of ROB reads -system.cpu2.rob.rob_writes 555310468 # The number of ROB writes -system.cpu2.timesIdled 112460 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 943952 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4909839532 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135819902 # Number of Instructions Simulated -system.cpu2.committedOps 268063987 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.128563 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.128563 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.886082 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.886082 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364708409 # number of integer regfile reads -system.cpu2.int_regfile_writes 218787106 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72944 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139159619 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107004309 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89032423 # number of misc regfile reads -system.cpu2.misc_regfile_writes 133306 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3554527 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554527 # Transaction distribution -system.iobus.trans_dist::WriteReq 57693 # Transaction distribution -system.iobus.trans_dist::WriteResp 10973 # Transaction distribution +system.cpu2.rob.rob_reads 425310506 # The number of ROB reads +system.cpu2.rob.rob_writes 553158006 # The number of ROB writes +system.cpu2.timesIdled 113704 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 991020 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4914719574 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 135487364 # Number of Instructions Simulated +system.cpu2.committedOps 267234162 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.134243 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.134243 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.881645 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.881645 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 363574277 # number of integer regfile reads +system.cpu2.int_regfile_writes 217910153 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72980 # number of floating regfile reads +system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes +system.cpu2.cc_regfile_reads 138812774 # number of cc regfile reads +system.cpu2.cc_regfile_writes 106705933 # number of cc regfile writes +system.cpu2.misc_regfile_reads 88766274 # number of misc regfile reads +system.cpu2.misc_regfile_writes 139734 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3554581 # Transaction distribution +system.iobus.trans_dist::ReadResp 3554581 # Transaction distribution +system.iobus.trans_dist::WriteReq 57732 # Transaction distribution +system.iobus.trans_dist::WriteResp 11012 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1666 # Transaction distribution -system.iobus.trans_dist::MessageResp 1666 # Transaction distribution +system.iobus.trans_dist::MessageReq 1688 # Transaction distribution +system.iobus.trans_dist::MessageResp 1688 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1126 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27740 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27910 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7129192 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95248 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7227772 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7129380 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95246 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95246 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3376 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3376 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7228002 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2252 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13870 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13955 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3570795 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027776 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6664 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605235 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2673040 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3570850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027768 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6752 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6752 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6605370 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2500128 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4313000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 3583000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1199,70 +1224,70 @@ system.iobus.reqLayer5.occupancy 758000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 22000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 345000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 318000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10349000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10022000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 277910069 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 273258249 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 302790000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 301483000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 34215251 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 28884002 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1117000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1044000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47569 # number of replacements -system.iocache.tags.tagsinuse 0.087266 # Cycle average of tags in use +system.iocache.tags.replacements 47568 # number of replacements +system.iocache.tags.tagsinuse 0.106184 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47585 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47584 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571413009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.087266 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005454 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005454 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000571396009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.106184 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006636 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006636 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428616 # Number of tag accesses -system.iocache.tags.data_accesses 428616 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses -system.iocache.ReadReq_misses::total 904 # number of ReadReq misses +system.iocache.tags.tag_accesses 428607 # Number of tag accesses +system.iocache.tags.data_accesses 428607 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses +system.iocache.ReadReq_misses::total 903 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 904 # number of demand (read+write) misses -system.iocache.demand_misses::total 904 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 904 # number of overall misses -system.iocache.overall_misses::total 904 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 131125053 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 131125053 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 7701347765 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 7701347765 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 131125053 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 131125053 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 131125053 # number of overall miss cycles -system.iocache.overall_miss_latency::total 131125053 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 903 # number of demand (read+write) misses +system.iocache.demand_misses::total 903 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 903 # number of overall misses +system.iocache.overall_misses::total 903 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 21110907 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21110907 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 7547175340 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 7547175340 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 21110907 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21110907 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 21110907 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21110907 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 904 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 904 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 904 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 904 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 903 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 903 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 903 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 903 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1271,311 +1296,325 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145049.837389 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 164840.491545 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 164840.491545 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145049.837389 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145049.837389 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145049.837389 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 44239 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 23378.634551 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 161540.568065 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 161540.568065 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 23378.634551 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 23378.634551 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 23378.634551 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 42516 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5740 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 5560 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.707143 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.646763 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 737 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 737 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28920 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 28920 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 737 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 737 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 737 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 737 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 92773553 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6197505767 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6197505767 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 92773553 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 92773553 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 92773553 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.815265 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.619007 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.619007 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.815265 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.815265 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.815265 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 125879.990502 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 214298.263036 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 214298.263036 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 125879.990502 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 125879.990502 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 125879.990502 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 186 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 186 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28512 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 28512 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 186 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 186 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 186 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 186 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 11438907 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6064547344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6064547344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 11438907 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 11438907 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 11438907 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.205980 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.610274 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.610274 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.205980 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.205980 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.205980 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 61499.500000 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212701.576319 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212701.576319 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 61499.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 61499.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 61499.500000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104557 # number of replacements -system.l2c.tags.tagsinuse 64826.146133 # Cycle average of tags in use -system.l2c.tags.total_refs 3692284 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168716 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.884611 # Average number of references to valid blocks. +system.l2c.tags.replacements 104912 # number of replacements +system.l2c.tags.tagsinuse 64826.396555 # Cycle average of tags in use +system.l2c.tags.total_refs 3699624 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169121 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.875604 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51357.956330 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134652 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1732.560753 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4954.090850 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 380.669805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1966.640889 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.273350 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 862.228039 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3565.591465 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.783660 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51247.277585 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1719.764589 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5034.334216 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003270 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 365.232722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1988.868841 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.547985 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 847.123033 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3617.112946 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.781971 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.026437 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075593 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005809 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030009 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000096 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.013157 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.054407 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989168 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64159 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2872 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7102 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53894 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.978989 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33845084 # Number of tag accesses -system.l2c.tags.data_accesses 33845084 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 19958 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10605 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 325698 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 500488 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 12200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6454 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 157050 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 219829 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 57606 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 367139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 593198 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2283839 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.026242 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076818 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.005573 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.030348 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000100 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.012926 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.055193 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989172 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64209 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 571 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3164 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7713 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52703 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.979752 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33891817 # Number of tag accesses +system.l2c.tags.data_accesses 33891817 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 20180 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10473 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 308266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 489820 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12327 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 6781 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 172994 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 227559 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 57791 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 13812 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 370398 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 597307 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2287708 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1546924 # number of Writeback hits -system.l2c.Writeback_hits::total 1546924 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 142 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 42 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 83 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 267 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 67626 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 34040 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 59382 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 161048 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 19958 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10607 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 325698 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 568114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12200 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6454 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 157050 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 253869 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 57606 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13614 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 367139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 652580 # number of demand (read+write) hits -system.l2c.demand_hits::total 2444889 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 19958 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10607 # number of overall hits -system.l2c.overall_hits::cpu0.inst 325698 # number of overall hits -system.l2c.overall_hits::cpu0.data 568114 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12200 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6454 # number of overall hits -system.l2c.overall_hits::cpu1.inst 157050 # number of overall hits -system.l2c.overall_hits::cpu1.data 253869 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 57606 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13614 # number of overall hits -system.l2c.overall_hits::cpu2.inst 367139 # number of overall hits -system.l2c.overall_hits::cpu2.data 652580 # number of overall hits -system.l2c.overall_hits::total 2444889 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7634 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 14793 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2277 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5204 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 28 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5252 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 12827 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48020 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 716 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 252 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 429 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.022773 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000536 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.015760 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018567 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.010757 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.774194 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.837879 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.523291 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.426445 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.339423 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.219808 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.015760 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.065502 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033982 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 272000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61470.214844 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63276.683010 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77991.935484 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65403.852639 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67165.685841 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 65370.224071 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12085.894231 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10298.459313 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10943.175723 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55894.129171 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59151.183269 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57690.879481 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 272000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61470.214844 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57043.190925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77991.935484 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65403.852639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61090.618747 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 59851.829331 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 272000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61470.214844 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57043.190925 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77991.935484 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65403.852639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61090.618747 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 59851.829331 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1707,62 +1758,66 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5119668 # Transaction distribution -system.membus.trans_dist::ReadResp 5119668 # Transaction distribution -system.membus.trans_dist::WriteReq 13886 # Transaction distribution -system.membus.trans_dist::WriteResp 13886 # Transaction distribution -system.membus.trans_dist::Writeback 143068 # Transaction distribution +system.membus.trans_dist::ReadReq 5122016 # Transaction distribution +system.membus.trans_dist::ReadResp 5122015 # Transaction distribution +system.membus.trans_dist::WriteReq 13950 # Transaction distribution +system.membus.trans_dist::WriteResp 13950 # Transaction distribution +system.membus.trans_dist::Writeback 143315 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1653 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1653 # Transaction distribution -system.membus.trans_dist::ReadExReq 130108 # Transaction distribution -system.membus.trans_dist::ReadExResp 130108 # Transaction distribution -system.membus.trans_dist::MessageReq 1666 # Transaction distribution -system.membus.trans_dist::MessageResp 1666 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3332 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3332 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3040070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455653 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10624915 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141621 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141621 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10769868 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570795 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6080137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17551104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27202036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6015808 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33224508 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 602 # Total snoops (count) -system.membus.snoop_fanout::samples 370472 # Request fanout histogram +system.membus.trans_dist::UpgradeReq 1630 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1630 # Transaction distribution +system.membus.trans_dist::ReadExReq 130173 # Transaction distribution +system.membus.trans_dist::ReadExResp 130173 # Transaction distribution +system.membus.trans_dist::MessageReq 1688 # Transaction distribution +system.membus.trans_dist::MessageResp 1688 # Transaction distribution +system.membus.trans_dist::BadAddressError 1 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3376 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129380 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044798 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455864 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 2 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10630044 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141727 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141727 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10775147 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6752 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6089593 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17566400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27226843 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6022656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6022656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33256251 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 522 # Total snoops (count) +system.membus.snoop_fanout::samples 370715 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 370472 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 370715 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 370472 # Request fanout histogram -system.membus.reqLayer0.occupancy 162446500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 370715 # Request fanout histogram +system.membus.reqLayer0.occupancy 161293000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314906500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 314500500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2234000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2088000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1120775500 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1165884999 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1117000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1044000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1662967675 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1714039312 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 35567749 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 30187998 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1776,51 +1831,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7434879 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7434349 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13888 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13888 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1546924 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 28920 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1664 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1664 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291412 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291412 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1730144 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14995223 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73480 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 207718 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17006565 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55364032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213483380 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 273608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 760144 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 269881164 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 70776 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4251023 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011203 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105249 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 7445356 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7445355 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13952 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13952 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1548383 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 28512 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1653 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1653 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 291909 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 291909 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 1 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1733601 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15004877 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73054 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 211316 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17022848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55474752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213691163 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 265608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 747576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270179099 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 79089 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4261601 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011175 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105119 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4203399 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47624 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4213978 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47623 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4251023 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5194614325 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4261601 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5362619847 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 931500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 837000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2395792281 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2486663092 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4837647628 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4974743955 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 25185912 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 27294890 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 87831597 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 94899067 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal index 2c13ee133..5e6b18ba5 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal @@ -40,12 +40,13 @@ Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset Mount-cache hash table entries: 256
CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)
CPU: L2 Cache: 1024K (64 bytes/line)
+using mwait in idle threads.
CPU: Fake M5 x86_64 CPU stepping 01
ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts.
-result 7812527
+result 7812526
Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16
PCI: Using configuration type 1
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