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authorGabe Black <gabeblack@google.com>2017-03-29 16:14:05 -0700
committerGabe Black <gabeblack@google.com>2017-04-05 18:40:59 +0000
commitf7ddc4672a17ee4fab3011bb1b570cc7c17dff28 (patch)
tree1b09ee7160f513160fdbd766af3afed63f053e1d /tests/long
parent8ebc3834651857ae5e2ea755844f263d9a8c34ae (diff)
downloadgem5-f7ddc4672a17ee4fab3011bb1b570cc7c17dff28.tar.xz
stats: Update some stats after simulated program exit behavior was changed.
The following CL delayed program exit and changed the stats for many if not most of the SE mode regressions. commit 2c1286865fc2542a0586ca4ff40b00765d17b348 Author: Brandon Potter <Brandon.Potter@amd.com> Date: Wed Mar 1 14:52:23 2017 -0600 syscall-emul: Rewrite system call exit code Change-Id: Id241f2b7d5374947597c715ee44febe1acc5ea16 Reviewed-on: https://gem5-review.googlesource.com/2656 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'tests/long')
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini82
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/arm/linux/o3-timing/simout11
-rw-r--r--tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt2516
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini49
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout11
-rw-r--r--tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt1074
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini97
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr3
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/o3-timing/simout13
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt2102
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini50
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr1
-rwxr-xr-xtests/long/se/10.mcf/ref/x86/linux/simple-timing/simout11
-rw-r--r--tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt1074
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini82
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/o3-timing/simerr3
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/o3-timing/simout13
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt2544
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini29
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr3
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/simple-atomic/simout13
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt516
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini53
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/simple-timing/simerr3
-rwxr-xr-xtests/long/se/20.parser/ref/arm/linux/simple-timing/simout13
-rw-r--r--tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt1362
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini97
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/o3-timing/simerr15
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/o3-timing/simout14
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt2176
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini26
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr4
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/simple-atomic/simout16
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt282
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini50
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/simple-timing/simerr4
-rwxr-xr-xtests/long/se/20.parser/ref/x86/linux/simple-timing/simout16
-rw-r--r--tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt1084
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini80
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/o3-timing/simerr5
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/o3-timing/simout15
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt2474
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini27
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr5
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/simple-atomic/simout15
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt516
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini51
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/simple-timing/simerr5
-rwxr-xr-xtests/long/se/30.eon/ref/arm/linux/simple-timing/simout15
-rw-r--r--tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt1342
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini2
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout8
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt18
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini27
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr3
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout13
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt516
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini51
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr3
-rwxr-xr-xtests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout13
-rw-r--r--tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt1364
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini80
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr2
-rwxr-xr-xtests/long/se/50.vortex/ref/arm/linux/o3-timing/simout12
-rw-r--r--tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt2524
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini80
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr4
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout14
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt2556
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini27
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr4
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout14
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt516
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini51
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr4
-rwxr-xr-xtests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout14
-rw-r--r--tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt1356
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini24
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr4
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout14
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt282
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini48
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr4
-rwxr-xr-xtests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout14
-rw-r--r--tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt1074
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini80
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr2
-rwxr-xr-xtests/long/se/70.twolf/ref/arm/linux/o3-timing/simout12
-rw-r--r--tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt2458
-rwxr-xr-xtests/long/se/70.twolf/ref/x86/linux/o3-timing/simout8
-rw-r--r--tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt26
93 files changed, 16935 insertions, 16455 deletions
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index afbdccd37..e061f70cd 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
index 4184e8f67..5b248e07d 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
@@ -1,4 +1,5 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 07887a4ce..b22552f23 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:52:57
-gem5 executing on e108600-lin, pid 17480
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 18:10:17
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 56685
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 58675371500 because target called exit()
+Exiting @ tick 58521086000 because exiting with last active thread context
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
index 57821b2e6..7a51f9c37 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
@@ -1,1262 +1,1262 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.058521 # Number of seconds simulated
-sim_ticks 58521086000 # Number of ticks simulated
-final_tick 58521086000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 243648 # Simulator instruction rate (inst/s)
-host_op_rate 244862 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 157397000 # Simulator tick rate (ticks/s)
-host_mem_usage 492140 # Number of bytes of host memory used
-host_seconds 371.81 # Real time elapsed on the host
-sim_insts 90589799 # Number of instructions simulated
-sim_ops 91041030 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 44736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 220224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 921920 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1186880 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 44736 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 44736 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4736 # Number of bytes written to this memory
-system.physmem.bytes_written::total 4736 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 699 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3441 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 14405 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 18545 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 74 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 74 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 764442 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3763156 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 15753638 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 20281237 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 764442 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 764442 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 80928 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 80928 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 80928 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 764442 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3763156 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 15753638 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 20362165 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 18546 # Number of read requests accepted
-system.physmem.writeReqs 74 # Number of write requests accepted
-system.physmem.readBursts 18546 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 74 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 1183360 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 3584 # Total number of bytes read from write queue
-system.physmem.bytesWritten 3328 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 1186944 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 4736 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 56 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 3297 # Per bank write bursts
-system.physmem.perBankRdBursts::1 920 # Per bank write bursts
-system.physmem.perBankRdBursts::2 949 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1031 # Per bank write bursts
-system.physmem.perBankRdBursts::4 1067 # Per bank write bursts
-system.physmem.perBankRdBursts::5 1119 # Per bank write bursts
-system.physmem.perBankRdBursts::6 1093 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1097 # Per bank write bursts
-system.physmem.perBankRdBursts::8 1024 # Per bank write bursts
-system.physmem.perBankRdBursts::9 961 # Per bank write bursts
-system.physmem.perBankRdBursts::10 934 # Per bank write bursts
-system.physmem.perBankRdBursts::11 899 # Per bank write bursts
-system.physmem.perBankRdBursts::12 902 # Per bank write bursts
-system.physmem.perBankRdBursts::13 895 # Per bank write bursts
-system.physmem.perBankRdBursts::14 1399 # Per bank write bursts
-system.physmem.perBankRdBursts::15 903 # Per bank write bursts
-system.physmem.perBankWrBursts::0 1 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 2 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 1 # Per bank write bursts
-system.physmem.perBankWrBursts::5 14 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9 # Per bank write bursts
-system.physmem.perBankWrBursts::7 3 # Per bank write bursts
-system.physmem.perBankWrBursts::8 1 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 2 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 1 # Per bank write bursts
-system.physmem.perBankWrBursts::13 12 # Per bank write bursts
-system.physmem.perBankWrBursts::14 5 # Per bank write bursts
-system.physmem.perBankWrBursts::15 1 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 58521077500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 18546 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 74 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 12593 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 3390 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 500 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 409 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 319 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 301 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 297 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 299 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 279 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 103 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 3004 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 394.652463 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 214.589229 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 405.543781 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 893 29.73% 29.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 965 32.12% 61.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 89 2.96% 64.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 63 2.10% 66.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 67 2.23% 69.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 66 2.20% 71.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 53 1.76% 73.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 47 1.56% 74.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 761 25.33% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 3004 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 6161.333333 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 2123.401593 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 8586.829993 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511 1 33.33% 33.33% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2559 1 33.33% 66.67% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15872-16383 1 33.33% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.333333 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.306995 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.154701 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 1 33.33% 33.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 2 66.67% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3 # Writes before turning the bus around for reads
-system.physmem.totQLat 837911216 # Total ticks spent queuing
-system.physmem.totMemAccLat 1184598716 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 92450000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 45316.99 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 64066.99 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 20.22 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.06 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 20.28 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.08 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.16 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.16 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 13.38 # Average write queue length when enqueuing
-system.physmem.readRowHits 15512 # Number of row buffer hits during reads
-system.physmem.writeRowHits 18 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.89 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 25.71 # Row buffer hit rate for writes
-system.physmem.avgGap 3142915.01 # Average gap between requests
-system.physmem.pageHitRate 83.67 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 16243500 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 8614650 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 75484080 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 156600 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 1895549760.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 464945010 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 99199680 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 4173482430 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 3272736480 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 9883191315 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 19894073865 # Total energy per rank (pJ)
-system.physmem_0.averagePower 339.947098 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 57233116090 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 194944250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 806364000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 39558059500 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 8522710566 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 286661660 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 9152346024 # Time in different power states
-system.physmem_1.actEnergy 5255040 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2785530 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 56527380 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 114840 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 247699920.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 125328180 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 13397280 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 772336890 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 242624160 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 13451278005 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 14917407225 # Total energy per rank (pJ)
-system.physmem_1.averagePower 254.906533 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 58211272096 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 21634250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 105218000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 55885668250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 631842954 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 182961654 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 1693760892 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 28121660 # Number of BP lookups
-system.cpu.branchPred.condPredicted 23134709 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 844714 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 11731332 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 11630363 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 99.139322 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 80725 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 95 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 28301 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 25845 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 2456 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 243 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 442 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 117042173 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 755365 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 134380549 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 28121660 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 11736933 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 115370240 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1692793 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles 1033 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 32086744 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 572 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 116973882 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.154260 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.318237 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 59688776 51.03% 51.03% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 13868271 11.86% 62.88% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 9100495 7.78% 70.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 34316340 29.34% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 116973882 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.240269 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.148138 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8865418 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 65026599 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 32710680 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9589004 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 782181 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 9831266 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 64876 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 113761457 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2108425 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 782181 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 15316274 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 50229704 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 114341 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 35119945 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 15411437 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 110456918 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 1289549 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 11149602 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1576334 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 2138216 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 510190 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 129202611 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 481340709 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 118978784 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 633 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 21889692 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 4408 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 4400 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 21529051 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26813393 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 5308956 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 540635 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 272789 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 109383305 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 8282 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 101253910 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 993650 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 18350557 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 40868291 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 64 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 116973882 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.865611 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 0.989909 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 55502940 47.45% 47.45% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 31207963 26.68% 74.13% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 21948493 18.76% 92.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7109305 6.08% 98.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1204859 1.03% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 322 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 116973882 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 9836731 48.84% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 51 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 19 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.84% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 9605308 47.69% 96.54% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 697155 3.46% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 3 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 24 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 71822499 70.93% 70.93% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 10678 0.01% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 184 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.94% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 24343876 24.04% 94.99% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 5076562 5.01% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 8 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 22 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 101253910 # Type of FU issued
-system.cpu.iq.rate 0.865106 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 20139291 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.198899 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 340613998 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 127742533 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 99568159 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 645 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 896 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 147 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 121392865 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 336 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 289487 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4337482 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 2085 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 1323 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 564112 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 7586 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 131115 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 782181 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 8303656 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 706645 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 109404410 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26813393 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 5308956 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 4394 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 183005 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 362995 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 1323 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 354101 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 451870 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 805971 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 100068536 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 23799476 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1185374 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 12823 # number of nop insts executed
-system.cpu.iew.exec_refs 28747002 # number of memory reference insts executed
-system.cpu.iew.exec_branches 20644390 # Number of branches executed
-system.cpu.iew.exec_stores 4947526 # Number of stores executed
-system.cpu.iew.exec_rate 0.854978 # Inst execution rate
-system.cpu.iew.wb_sent 99653444 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 99568306 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 59603520 # num instructions producing a value
-system.cpu.iew.wb_consumers 95472454 # num instructions consuming a value
-system.cpu.iew.wb_rate 0.850705 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.624301 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 17204380 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 780499 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 114317449 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.796498 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.736161 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 77973404 68.21% 68.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 18552037 16.23% 84.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 7135846 6.24% 90.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 3439776 3.01% 93.69% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1654311 1.45% 95.13% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 545783 0.48% 95.61% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 692568 0.61% 96.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 180777 0.16% 96.38% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 4142947 3.62% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 114317449 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 90602408 # Number of instructions committed
-system.cpu.commit.committedOps 91053639 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27220755 # Number of memory references committed
-system.cpu.commit.loads 22475911 # Number of loads committed
-system.cpu.commit.membars 3888 # Number of memory barriers committed
-system.cpu.commit.branches 18732305 # Number of branches committed
-system.cpu.commit.fp_insts 48 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 72326352 # Number of committed integer instructions.
-system.cpu.commit.function_calls 56148 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 63822387 70.09% 70.09% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 10474 0.01% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 6 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 15 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 2 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.10% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 22475905 24.68% 94.79% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 4744822 5.21% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 6 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 22 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 91053639 # Class of committed instruction
-system.cpu.commit.bw_lim_events 4142947 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 218426787 # The number of ROB reads
-system.cpu.rob.rob_writes 219173124 # The number of ROB writes
-system.cpu.timesIdled 593 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 68291 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 90589799 # Number of Instructions Simulated
-system.cpu.committedOps 91041030 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.292002 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.292002 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.773993 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.773993 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 108095256 # number of integer regfile reads
-system.cpu.int_regfile_writes 58597145 # number of integer regfile writes
-system.cpu.fp_regfile_reads 58 # number of floating regfile reads
-system.cpu.fp_regfile_writes 127 # number of floating regfile writes
-system.cpu.cc_regfile_reads 368871207 # number of cc regfile reads
-system.cpu.cc_regfile_writes 58517884 # number of cc regfile writes
-system.cpu.misc_regfile_reads 28439348 # number of misc regfile reads
-system.cpu.misc_regfile_writes 7784 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 5470632 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.768178 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 18243100 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 5471144 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 3.334421 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 38187500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.768178 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999547 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999547 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 327 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 61896540 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 61896540 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 13880582 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 13880582 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 4354214 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 4354214 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 3873 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 3873 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 18234796 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 18234796 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 18235318 # number of overall hits
-system.cpu.dcache.overall_hits::total 18235318 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 9588832 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 9588832 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 380767 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 380767 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 14 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 14 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 9969599 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9969599 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9969606 # number of overall misses
-system.cpu.dcache.overall_misses::total 9969606 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 89393317500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 89393317500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 4103772083 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 4103772083 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 302000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 302000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 93497089583 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 93497089583 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 93497089583 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 93497089583 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23469414 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23469414 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 28204395 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 28204395 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 28204924 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 28204924 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408567 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.408567 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080416 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.080416 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003602 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003602 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.353477 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.353477 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.353470 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.353470 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9322.649255 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 9322.649255 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10777.646390 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10777.646390 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21571.428571 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21571.428571 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 9378.219684 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 9378.219684 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 9378.213099 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 9378.213099 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 331670 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 131340 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 121646 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 12838 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.726518 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 10.230566 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 5470632 # number of writebacks
-system.cpu.dcache.writebacks::total 5470632 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4340269 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 4340269 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158185 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 158185 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 14 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 4498454 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 4498454 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 4498454 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 4498454 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5248563 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 5248563 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222582 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 222582 # number of WriteReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 5471149 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 43818706500 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 46120804483 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223634 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.demand_mshr_miss_rate::total 0.193982 # mshr miss rate for demand accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8348.705446 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10341.638061 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10341.638061 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 58875 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 58875 # average SoftPFReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 8429.783708 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8429.820589 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 8429.820589 # average overall mshr miss latency
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-system.cpu.icache.tags.replacements 449 # number of replacements
-system.cpu.icache.tags.tagsinuse 426.857560 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 32085580 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 907 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 35375.501654 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 426.857560 # Average occupied blocks per requestor
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-system.cpu.icache.tags.occ_task_id_blocks::1024 458 # Occupied blocks per task id
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-system.cpu.icache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 22 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 333 # Occupied blocks per task id
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-system.cpu.icache.demand_avg_miss_latency::total 70731.785095 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 70731.785095 # average overall miss latency
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-system.cpu.icache.avg_blocked_cycles::no_targets 264.714286 # average number of cycles each access was blocked
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67852.405286 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67852.405286 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 67852.405286 # average overall mshr miss latency
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-system.cpu.l2cache.prefetcher.num_hwpf_issued 4987667 # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified 5295978 # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit 268023 # number of redundant prefetches already in prefetch queue
-system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
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-system.cpu.l2cache.prefetcher.pfSpanPage 14076270 # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 99 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 11218.637670 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 5292117 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 14656 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 361.088769 # Average number of references to valid blocks.
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-system.cpu.l2cache.tags.occ_blocks::writebacks 11151.920658 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 66.717012 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024 14490 # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1022::4 56 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 454 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3440 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9642 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 120 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 834 # Occupied blocks per task id
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-system.cpu.l2cache.tags.tag_accesses 180525307 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 180525307 # Number of data accesses
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-system.cpu.l2cache.ReadCleanReq_hits::total 207 # number of ReadCleanReq hits
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-system.cpu.l2cache.ReadSharedReq_hits::total 5241769 # number of ReadSharedReq hits
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84604.136947 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84604.136947 # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 197662.504003 # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 197662.504003 # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::total 171825.931066 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84604.136947 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 188706.791828 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 171825.931066 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.unused_prefetches 1 # number of HardPF blocks evicted w/o reference
-system.cpu.l2cache.writebacks::writebacks 74 # number of writebacks
-system.cpu.l2cache.writebacks::total 74 # number of writebacks
-system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 158 # number of ReadExReq MSHR hits
-system.cpu.l2cache.ReadExReq_mshr_hits::total 158 # number of ReadExReq MSHR hits
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-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 22 # number of ReadSharedReq MSHR hits
-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 22 # number of ReadSharedReq MSHR hits
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-system.cpu.l2cache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 181 # number of demand (read+write) MSHR hits
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-system.cpu.l2cache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 181 # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 316332 # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total 316332 # number of HardPFReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::total 5 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 700 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 700 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 3101 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 3101 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 700 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 3442 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 4142 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 700 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 3442 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 316332 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 320474 # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1095451507 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 75500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 75500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 46761500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 46761500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 55046500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 55046500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 590692000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 590692000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55046500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 637453500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 692500000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55046500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 637453500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1095451507 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 1787951507 # number of overall MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001507 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001507 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.770925 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000591 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000591 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.000757 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.770925 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000629 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.058566 # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3462.980372 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15100 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15100 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 137130.498534 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 137130.498534 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78637.857143 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78637.857143 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 190484.359884 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 190484.359884 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 167189.763399 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78637.857143 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 185198.576409 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3462.980372 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 5579.084441 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 10943138 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 5471099 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 2928 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 301927 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 301926 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 5245799 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 5460271 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 10884 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 25 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq 318221 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 226252 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadCleanReq 908 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 5244892 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2264 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16412936 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 16415200 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 86784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700274048 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 700360832 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 318326 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 5120 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 5790377 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.052651 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.223337 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 5485509 94.73% 94.73% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 304867 5.27% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::total 5790377 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 10942650026 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 9032 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1362995 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 8206721993 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 14.0 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 18651 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 3037 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 58521086000 # Cumulative time (in ticks) in various power states
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-system.membus.trans_dist::ReadExResp 340 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 18206 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 37196 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 37196 # Packet count per connected master and slave (bytes)
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-system.membus.pkt_size::total 1191616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 18552 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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-system.membus.snoop_fanout::total 18552 # Request fanout histogram
-system.membus.reqLayer0.occupancy 29380556 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 97369032 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+sim_seconds 0.058521
+sim_ticks 58521086000
+final_tick 58521086000
+sim_freq 1000000000000
+host_inst_rate 103970
+host_op_rate 104488
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+system.physmem.writeBursts 74
+system.physmem.bytesReadDRAM 1183360
+system.physmem.bytesReadWrQ 3584
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+system.physmem.bytesReadSys 1186944
+system.physmem.bytesWrittenSys 4736
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+system.physmem.perBankRdBursts::8 1024
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+system.membus.snoop_fanout::samples 18552
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 18552 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 18552
+system.membus.reqLayer0.occupancy 29380556
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 97369032
+system.membus.respLayer1.utilization 0.2
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index c6db85421..d6f970870 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -85,6 +85,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -94,14 +95,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -115,6 +116,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -127,15 +129,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dtb]
type=SparcTLB
@@ -145,14 +148,14 @@ size=64
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -166,6 +169,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -178,15 +182,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=SparcInterrupts
@@ -204,14 +209,14 @@ size=64
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -225,6 +230,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -237,15 +243,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -281,7 +288,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
drivers=
@@ -290,14 +297,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/sparc/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
@@ -321,6 +329,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -332,7 +341,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -340,6 +349,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -348,6 +364,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -355,7 +372,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
index aadc3d011..c0b55d123 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index 8bd59a796..1f1ba7a8d 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-ti
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:30:06
-gem5 started Jul 21 2016 14:30:36
-gem5 executing on e108600-lin, pid 38669
-command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing
+gem5 compiled Apr 3 2017 18:41:19
+gem5 started Apr 3 2017 18:43:33
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 66471
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 361597758500 because target called exit()
+Exiting @ tick 361613361500 because exiting with last active thread context
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
index 33d560709..7f71ad751 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
@@ -1,541 +1,541 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.361613 # Number of seconds simulated
-sim_ticks 361613361500 # Number of ticks simulated
-final_tick 361613361500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1844871 # Simulator instruction rate (inst/s)
-host_op_rate 1844948 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2736100211 # Simulator tick rate (ticks/s)
-host_mem_usage 385448 # Number of bytes of host memory used
-host_seconds 132.16 # Real time elapsed on the host
-sim_insts 243825150 # Number of instructions simulated
-sim_ops 243835265 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory
-system.physmem.bytes_read::total 998592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 56256 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 56256 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 879 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 14724 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15603 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 155569 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2605921 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2761491 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 155569 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 155569 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 155569 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2605921 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2761491 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.workload.numSyscalls 443 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 723226723 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 243825150 # Number of instructions committed
-system.cpu.committedOps 243835265 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 194726494 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
-system.cpu.num_func_calls 4252956 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18619959 # number of instructions that are conditional controls
-system.cpu.num_int_insts 194726494 # number of integer instructions
-system.cpu.num_fp_insts 11630 # number of float instructions
-system.cpu.num_int_register_reads 456818988 # number of times the integer registers were read
-system.cpu.num_int_register_writes 215451553 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 23256 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 90 # number of times the floating registers were written
-system.cpu.num_mem_refs 105711441 # number of memory refs
-system.cpu.num_load_insts 82803521 # Number of load instructions
-system.cpu.num_store_insts 22907920 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 723226722.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 29302884 # Number of branches fetched
-system.cpu.op_class::No_OpClass 28877736 11.81% 11.81% # Class of executed instruction
-system.cpu.op_class::IntAlu 109842388 44.94% 56.75% # Class of executed instruction
-system.cpu.op_class::IntMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatAdd 42 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.75% # Class of executed instruction
-system.cpu.op_class::MemRead 82803516 33.88% 90.63% # Class of executed instruction
-system.cpu.op_class::MemWrite 22896343 9.37% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 11 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 11577 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 244431613 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 935475 # number of replacements
-system.cpu.dcache.tags.tagsinuse 3562.404243 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 134415942500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 3562.404243 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.869728 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.869728 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1416 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2526 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 361613361500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
-system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
-system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits
-system.cpu.dcache.overall_hits::total 104182817 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses
-system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses
-system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses
-system.cpu.dcache.overall_misses::total 939567 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 11614992000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 11614992000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 1335530000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 1335530000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::cpu.data 102000 # number of SwapReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency::total 102000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 12950522000 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 12950522000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 12950522000 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 12950522000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses
-system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses
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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50503.981797 # average ReadCleanReq mshr miss latency
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+system.membus.reqLayer0.occupancy 15606500
+system.membus.reqLayer0.utilization 0.0
+system.membus.respLayer1.occupancy 78015000
+system.membus.respLayer1.utilization 0.0
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index e54b7db9f..ebb274721 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -65,7 +66,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -139,6 +140,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -183,10 +185,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -200,6 +202,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -212,15 +215,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -313,10 +317,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
+children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@@ -328,11 +332,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
-[system.cpu.fuPool.FUList3.opList2]
+[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@@ -341,18 +359,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList
+children=opList0 opList1
count=0
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
+[system.cpu.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -502,24 +527,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
-children=opList
+children=opList0 opList1
count=0
eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0 opList1
+children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@@ -535,6 +567,20 @@ opClass=MemWrite
opLat=1
pipelined=true
+[system.cpu.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@@ -556,10 +602,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -573,6 +619,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -585,15 +632,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -643,10 +691,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -660,6 +708,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -672,15 +721,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -716,7 +766,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
drivers=
@@ -725,14 +775,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
index 36f24465c..5d01a7eba 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
@@ -1,3 +1,6 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index 9e929c5a5..fa6158a9b 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 21:08:11
-gem5 executing on e108600-lin, pid 17630
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:06:21
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87177
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -19,13 +18,11 @@ All Rights Reserved.
nodes : 500
active arcs : 1905
simplex iterations : 1502
-info: Increasing stack size by one page.
flow value : 4990014995
-info: Increasing stack size by one page.
new implicit arcs : 23867
active arcs : 25772
simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 66079350000 because target called exit()
+Exiting @ tick 65721494500 because exiting with last active thread context
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
index 492625dc5..b9b8eb4c6 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
@@ -1,1055 +1,1055 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.065721 # Number of seconds simulated
-sim_ticks 65721494500 # Number of ticks simulated
-final_tick 65721494500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 191999 # Simulator instruction rate (inst/s)
-host_op_rate 338080 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 79869594 # Simulator tick rate (ticks/s)
-host_mem_usage 415448 # Number of bytes of host memory used
-host_seconds 822.86 # Real time elapsed on the host
-sim_insts 157988547 # Number of instructions simulated
-sim_ops 278192464 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 68800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1892544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1961344 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 68800 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 68800 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 19136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 19136 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1075 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29571 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30646 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 299 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 299 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 1046842 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 28796424 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 29843265 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 1046842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 1046842 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 291168 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 291168 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 291168 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 1046842 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 28796424 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 30134433 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 30646 # Number of read requests accepted
-system.physmem.writeReqs 299 # Number of write requests accepted
-system.physmem.readBursts 30646 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 299 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 1952832 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue
-system.physmem.bytesWritten 17216 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 1961344 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 19136 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 1937 # Per bank write bursts
-system.physmem.perBankRdBursts::1 2081 # Per bank write bursts
-system.physmem.perBankRdBursts::2 2039 # Per bank write bursts
-system.physmem.perBankRdBursts::3 1941 # Per bank write bursts
-system.physmem.perBankRdBursts::4 2068 # Per bank write bursts
-system.physmem.perBankRdBursts::5 1911 # Per bank write bursts
-system.physmem.perBankRdBursts::6 1977 # Per bank write bursts
-system.physmem.perBankRdBursts::7 1878 # Per bank write bursts
-system.physmem.perBankRdBursts::8 1945 # Per bank write bursts
-system.physmem.perBankRdBursts::9 1939 # Per bank write bursts
-system.physmem.perBankRdBursts::10 1805 # Per bank write bursts
-system.physmem.perBankRdBursts::11 1794 # Per bank write bursts
-system.physmem.perBankRdBursts::12 1792 # Per bank write bursts
-system.physmem.perBankRdBursts::13 1800 # Per bank write bursts
-system.physmem.perBankRdBursts::14 1827 # Per bank write bursts
-system.physmem.perBankRdBursts::15 1779 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8 # Per bank write bursts
-system.physmem.perBankWrBursts::1 125 # Per bank write bursts
-system.physmem.perBankWrBursts::2 25 # Per bank write bursts
-system.physmem.perBankWrBursts::3 26 # Per bank write bursts
-system.physmem.perBankWrBursts::4 54 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8 # Per bank write bursts
-system.physmem.perBankWrBursts::6 14 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6 # Per bank write bursts
-system.physmem.perBankWrBursts::10 3 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 65721290500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 30646 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 299 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 29942 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 423 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 106 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 36 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 2852 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 690.064516 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 482.522488 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 397.377699 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 418 14.66% 14.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 289 10.13% 24.79% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 128 4.49% 29.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 119 4.17% 33.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 133 4.66% 38.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 123 4.31% 42.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 83 2.91% 45.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 2852 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 15 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 2030.466667 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 23.801531 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 7801.447410 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 15 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 15 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.933333 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.931540 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.258199 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1 6.67% 6.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 14 93.33% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 15 # Writes before turning the bus around for reads
-system.physmem.totQLat 402617750 # Total ticks spent queuing
-system.physmem.totMemAccLat 974736500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 152565000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 13194.96 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31944.96 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 29.71 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.26 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 29.84 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.29 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.23 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.23 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 12.51 # Average write queue length when enqueuing
-system.physmem.readRowHits 27734 # Number of row buffer hits during reads
-system.physmem.writeRowHits 187 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 90.89 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.54 # Row buffer hit rate for writes
-system.physmem.avgGap 2123809.68 # Average gap between requests
-system.physmem.pageHitRate 90.62 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 11052720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 5855685 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 113040480 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 1357200 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 309163920.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 263324610 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 16569120 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 979073610 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 268447200 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 14975920920 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 16943805465 # Total energy per rank (pJ)
-system.physmem_0.averagePower 257.812234 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 65100637750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 22061500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 131194000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 62254705500 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 699065250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 467433500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 2147034750 # Time in different power states
-system.physmem_1.actEnergy 9374820 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 4967655 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 104822340 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 46980 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 372471840.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 249536310 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 19488480 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 1119740490 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 403290240 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 14835337125 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 17119488570 # Total energy per rank (pJ)
-system.physmem_1.averagePower 260.485370 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 65120969250 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 28589000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 158136000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 61616793750 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 1050209250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 412212500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 2455554000 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 40406290 # Number of BP lookups
-system.cpu.branchPred.condPredicted 40406290 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1431845 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 26031629 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 0 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 6025963 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 91921 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 26031629 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 20992529 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 5039100 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 530263 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 444 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 131442990 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30464048 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 219898668 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 40406290 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 27018492 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 99269738 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2979935 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 465 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 7592 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 128961 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 50 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 29660171 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 359072 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 17 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 131360995 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.946103 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.409063 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 65827184 50.11% 50.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 4032527 3.07% 53.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 3600376 2.74% 55.92% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 6081929 4.63% 60.55% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 7728911 5.88% 66.44% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 5535416 4.21% 70.65% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 3331669 2.54% 73.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 2842658 2.16% 75.35% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 32380325 24.65% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 131360995 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.307405 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.672959 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 15255907 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 64520496 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 40208811 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 9885814 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 1489967 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 362265652 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 1489967 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 20796133 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 11129664 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 23832 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 44255424 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 53665975 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 352608748 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 23342 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 777450 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 46732943 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 5205031 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 354925639 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 934456502 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 575559102 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 21159 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 75712892 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 482 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 483 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 64647332 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 112313472 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 38475522 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 51426374 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 8868395 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 343765046 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 3883 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 317634440 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 163759 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 65576465 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 101836454 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 3438 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 131360995 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.418027 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.167913 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 35651981 27.14% 27.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 20061286 15.27% 42.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 17078933 13.00% 55.41% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 17586289 13.39% 68.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 15273572 11.63% 80.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 12870930 9.80% 90.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 6718617 5.11% 95.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 4059315 3.09% 98.43% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 2060072 1.57% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 131360995 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 367555 8.92% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.92% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 3559749 86.40% 95.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 191317 4.64% 99.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 13 0.00% 99.97% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 1395 0.03% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 33339 0.01% 0.01% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 181647745 57.19% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 11501 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 497 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 296 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 101245285 31.87% 89.08% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 34690277 10.92% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 508 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 4992 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 317634440 # Type of FU issued
-system.cpu.iq.rate 2.416519 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 4120029 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012971 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 770896978 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 409373525 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 313389776 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 16685 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 31480 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 3775 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 321713926 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 7204 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 57497351 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 21534087 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 66072 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 62227 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 7035770 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4204 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 141777 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 1489967 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 8057522 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2987683 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 343768929 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 139556 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 112313472 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 38475522 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1604 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 2862 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 2991864 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 62227 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 520614 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 1090823 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1611437 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 315197484 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 100490397 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2436956 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 134782236 # number of memory reference insts executed
-system.cpu.iew.exec_branches 32089039 # Number of branches executed
-system.cpu.iew.exec_stores 34291839 # Number of stores executed
-system.cpu.iew.exec_rate 2.397979 # Inst execution rate
-system.cpu.iew.wb_sent 314036708 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 313393551 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 237399400 # num instructions producing a value
-system.cpu.iew.wb_consumers 342887037 # num instructions consuming a value
-system.cpu.iew.wb_rate 2.384255 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.692355 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 65692241 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1439325 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 121896437 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.282203 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 3.051706 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 56939574 46.71% 46.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 16454719 13.50% 60.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 11025665 9.05% 69.26% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 8756483 7.18% 76.44% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2109912 1.73% 78.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1768746 1.45% 79.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 935268 0.77% 80.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 726580 0.60% 80.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 23179490 19.02% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 121896437 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 157988547 # Number of instructions committed
-system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 122219137 # Number of memory references committed
-system.cpu.commit.loads 90779385 # Number of loads committed
-system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 29309705 # Number of branches committed
-system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 278169481 # Number of committed integer instructions.
-system.cpu.commit.function_calls 4237596 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 16695 0.01% 0.01% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 155945353 56.06% 56.06% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 10938 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 329 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 12 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.07% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 90779371 32.63% 88.70% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 31439738 11.30% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 14 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 14 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction
-system.cpu.commit.bw_lim_events 23179490 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 442601652 # The number of ROB reads
-system.cpu.rob.rob_writes 697313320 # The number of ROB writes
-system.cpu.timesIdled 909 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 81995 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 157988547 # Number of Instructions Simulated
-system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.831978 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.831978 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.201955 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.201955 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 502529726 # number of integer regfile reads
-system.cpu.int_regfile_writes 247564665 # number of integer regfile writes
-system.cpu.fp_regfile_reads 3566 # number of floating regfile reads
-system.cpu.fp_regfile_writes 731 # number of floating regfile writes
-system.cpu.cc_regfile_reads 108994485 # number of cc regfile reads
-system.cpu.cc_regfile_writes 65428204 # number of cc regfile writes
-system.cpu.misc_regfile_reads 201784346 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 2073509 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4067.268199 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 71482624 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2077605 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 34.406263 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 21075173500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4067.268199 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.992985 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.992985 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 504 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 3445 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 150633517 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 150633517 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 40136683 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 40136683 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 31345941 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 31345941 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 71482624 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 71482624 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 71482624 # number of overall hits
-system.cpu.dcache.overall_hits::total 71482624 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2701521 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2701521 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 93811 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 93811 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 2795332 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 2795332 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 2795332 # number of overall misses
-system.cpu.dcache.overall_misses::total 2795332 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 32454671000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 32454671000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 3177582491 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 3177582491 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 35632253491 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 35632253491 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 35632253491 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 35632253491 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 42838204 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 42838204 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 74277956 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 74277956 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 74277956 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 74277956 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.063063 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.063063 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002984 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.002984 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12013.480924 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 12013.480924 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33872.173743 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33872.173743 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 12747.055982 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 12747.055982 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 12747.055982 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 219709 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 682 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 43158 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 6 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 5.090806 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 113.666667 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 2066902 # number of writebacks
-system.cpu.dcache.writebacks::total 2066902 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 705827 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 705827 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11900 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 11900 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 717727 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 717727 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 717727 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 717727 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1995694 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1995694 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81911 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 81911 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2077605 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2077605 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2077605 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2077605 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24272933500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 24272933500 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 100550000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2133852000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 2234402000 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353860 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353860 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.976385 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000288 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000288 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.014743 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.976385 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014233 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.014743 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70740.360739 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70740.360739 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 93534.883721 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 93534.883721 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 143764.347826 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 143764.347826 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 93534.883721 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72160.292178 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72910.069830 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 4152301 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2073596 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 23 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 330 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 330 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 1996764 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 2067201 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 86 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 6988 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 81942 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 81942 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 1101 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1995663 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2288 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 6231007 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 265324416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 680 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 19136 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 2079386 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.000170 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.013047 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2079386 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4143138500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 6.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1652498 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3116407500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 4.7 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 30996 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 350 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 1650 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 299 # Transaction distribution
-system.membus.trans_dist::CleanEvict 51 # Transaction distribution
-system.membus.trans_dist::ReadExReq 28996 # Transaction distribution
-system.membus.trans_dist::ReadExResp 28996 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 1650 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 61642 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1980480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 30646 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 30646 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 30646 # Request fanout histogram
-system.membus.reqLayer0.occupancy 43591500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer1.occupancy 161486250 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
+sim_seconds 0.065721
+sim_ticks 65721494500
+final_tick 65721494500
+sim_freq 1000000000000
+host_inst_rate 83517
+host_op_rate 147060
+host_tick_rate 34742064
+host_mem_usage 427260
+host_seconds 1891.70
+sim_insts 157988547
+sim_ops 278192464
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.physmem.bytes_read::cpu.inst 68800
+system.physmem.bytes_read::cpu.data 1892544
+system.physmem.bytes_read::total 1961344
+system.physmem.bytes_inst_read::cpu.inst 68800
+system.physmem.bytes_inst_read::total 68800
+system.physmem.bytes_written::writebacks 19136
+system.physmem.bytes_written::total 19136
+system.physmem.num_reads::cpu.inst 1075
+system.physmem.num_reads::cpu.data 29571
+system.physmem.num_reads::total 30646
+system.physmem.num_writes::writebacks 299
+system.physmem.num_writes::total 299
+system.physmem.bw_read::cpu.inst 1046842
+system.physmem.bw_read::cpu.data 28796424
+system.physmem.bw_read::total 29843265
+system.physmem.bw_inst_read::cpu.inst 1046842
+system.physmem.bw_inst_read::total 1046842
+system.physmem.bw_write::writebacks 291168
+system.physmem.bw_write::total 291168
+system.physmem.bw_total::writebacks 291168
+system.physmem.bw_total::cpu.inst 1046842
+system.physmem.bw_total::cpu.data 28796424
+system.physmem.bw_total::total 30134433
+system.physmem.readReqs 30646
+system.physmem.writeReqs 299
+system.physmem.readBursts 30646
+system.physmem.writeBursts 299
+system.physmem.bytesReadDRAM 1952832
+system.physmem.bytesReadWrQ 8512
+system.physmem.bytesWritten 17216
+system.physmem.bytesReadSys 1961344
+system.physmem.bytesWrittenSys 19136
+system.physmem.servicedByWrQ 133
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 1937
+system.physmem.perBankRdBursts::1 2081
+system.physmem.perBankRdBursts::2 2039
+system.physmem.perBankRdBursts::3 1941
+system.physmem.perBankRdBursts::4 2068
+system.physmem.perBankRdBursts::5 1911
+system.physmem.perBankRdBursts::6 1977
+system.physmem.perBankRdBursts::7 1878
+system.physmem.perBankRdBursts::8 1945
+system.physmem.perBankRdBursts::9 1939
+system.physmem.perBankRdBursts::10 1805
+system.physmem.perBankRdBursts::11 1794
+system.physmem.perBankRdBursts::12 1792
+system.physmem.perBankRdBursts::13 1800
+system.physmem.perBankRdBursts::14 1827
+system.physmem.perBankRdBursts::15 1779
+system.physmem.perBankWrBursts::0 8
+system.physmem.perBankWrBursts::1 125
+system.physmem.perBankWrBursts::2 25
+system.physmem.perBankWrBursts::3 26
+system.physmem.perBankWrBursts::4 54
+system.physmem.perBankWrBursts::5 8
+system.physmem.perBankWrBursts::6 14
+system.physmem.perBankWrBursts::7 0
+system.physmem.perBankWrBursts::8 0
+system.physmem.perBankWrBursts::9 6
+system.physmem.perBankWrBursts::10 3
+system.physmem.perBankWrBursts::11 0
+system.physmem.perBankWrBursts::12 0
+system.physmem.perBankWrBursts::13 0
+system.physmem.perBankWrBursts::14 0
+system.physmem.perBankWrBursts::15 0
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 65721290500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
+system.physmem.readPktSize::5 0
+system.physmem.readPktSize::6 30646
+system.physmem.writePktSize::0 0
+system.physmem.writePktSize::1 0
+system.physmem.writePktSize::2 0
+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
+system.physmem.writePktSize::5 0
+system.physmem.writePktSize::6 299
+system.physmem.rdQLenPdf::0 29942
+system.physmem.rdQLenPdf::1 423
+system.physmem.rdQLenPdf::2 106
+system.physmem.rdQLenPdf::3 36
+system.physmem.rdQLenPdf::4 5
+system.physmem.rdQLenPdf::5 1
+system.physmem.rdQLenPdf::6 0
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+system.physmem.rdQLenPdf::8 0
+system.physmem.rdQLenPdf::9 0
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+system.physmem.rdQLenPdf::15 0
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+system.physmem.rdQLenPdf::17 0
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+system.physmem.rdQLenPdf::24 0
+system.physmem.rdQLenPdf::25 0
+system.physmem.rdQLenPdf::26 0
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+system.physmem.rdQLenPdf::28 0
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+system.physmem.rdQLenPdf::30 0
+system.physmem.rdQLenPdf::31 0
+system.physmem.wrQLenPdf::0 1
+system.physmem.wrQLenPdf::1 1
+system.physmem.wrQLenPdf::2 1
+system.physmem.wrQLenPdf::3 1
+system.physmem.wrQLenPdf::4 1
+system.physmem.wrQLenPdf::5 1
+system.physmem.wrQLenPdf::6 1
+system.physmem.wrQLenPdf::7 1
+system.physmem.wrQLenPdf::8 1
+system.physmem.wrQLenPdf::9 1
+system.physmem.wrQLenPdf::10 1
+system.physmem.wrQLenPdf::11 1
+system.physmem.wrQLenPdf::12 1
+system.physmem.wrQLenPdf::13 1
+system.physmem.wrQLenPdf::14 1
+system.physmem.wrQLenPdf::15 15
+system.physmem.wrQLenPdf::16 16
+system.physmem.wrQLenPdf::17 16
+system.physmem.wrQLenPdf::18 16
+system.physmem.wrQLenPdf::19 16
+system.physmem.wrQLenPdf::20 16
+system.physmem.wrQLenPdf::21 16
+system.physmem.wrQLenPdf::22 16
+system.physmem.wrQLenPdf::23 16
+system.physmem.wrQLenPdf::24 16
+system.physmem.wrQLenPdf::25 16
+system.physmem.wrQLenPdf::26 16
+system.physmem.wrQLenPdf::27 16
+system.physmem.wrQLenPdf::28 16
+system.physmem.wrQLenPdf::29 16
+system.physmem.wrQLenPdf::30 15
+system.physmem.wrQLenPdf::31 15
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+system.physmem.wrQLenPdf::40 0
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+system.physmem.wrQLenPdf::47 0
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+system.physmem.wrQLenPdf::57 0
+system.physmem.wrQLenPdf::58 0
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+system.physmem.wrQLenPdf::60 0
+system.physmem.wrQLenPdf::61 0
+system.physmem.wrQLenPdf::62 0
+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 2852
+system.physmem.bytesPerActivate::mean 690.064516
+system.physmem.bytesPerActivate::gmean 482.522488
+system.physmem.bytesPerActivate::stdev 397.377699
+system.physmem.bytesPerActivate::0-127 418 14.66% 14.66%
+system.physmem.bytesPerActivate::128-255 289 10.13% 24.79%
+system.physmem.bytesPerActivate::256-383 128 4.49% 29.28%
+system.physmem.bytesPerActivate::384-511 119 4.17% 33.45%
+system.physmem.bytesPerActivate::512-639 133 4.66% 38.11%
+system.physmem.bytesPerActivate::640-767 123 4.31% 42.43%
+system.physmem.bytesPerActivate::768-895 83 2.91% 45.34%
+system.physmem.bytesPerActivate::896-1023 90 3.16% 48.49%
+system.physmem.bytesPerActivate::1024-1151 1469 51.51% 100.00%
+system.physmem.bytesPerActivate::total 2852
+system.physmem.rdPerTurnAround::samples 15
+system.physmem.rdPerTurnAround::mean 2030.466667
+system.physmem.rdPerTurnAround::gmean 23.801531
+system.physmem.rdPerTurnAround::stdev 7801.447410
+system.physmem.rdPerTurnAround::0-1023 14 93.33% 93.33%
+system.physmem.rdPerTurnAround::29696-30719 1 6.67% 100.00%
+system.physmem.rdPerTurnAround::total 15
+system.physmem.wrPerTurnAround::samples 15
+system.physmem.wrPerTurnAround::mean 17.933333
+system.physmem.wrPerTurnAround::gmean 17.931540
+system.physmem.wrPerTurnAround::stdev 0.258199
+system.physmem.wrPerTurnAround::17 1 6.67% 6.67%
+system.physmem.wrPerTurnAround::18 14 93.33% 100.00%
+system.physmem.wrPerTurnAround::total 15
+system.physmem.totQLat 402617750
+system.physmem.totMemAccLat 974736500
+system.physmem.totBusLat 152565000
+system.physmem.avgQLat 13194.96
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 31944.96
+system.physmem.avgRdBW 29.71
+system.physmem.avgWrBW 0.26
+system.physmem.avgRdBWSys 29.84
+system.physmem.avgWrBWSys 0.29
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.23
+system.physmem.busUtilRead 0.23
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.00
+system.physmem.avgWrQLen 12.51
+system.physmem.readRowHits 27734
+system.physmem.writeRowHits 187
+system.physmem.readRowHitRate 90.89
+system.physmem.writeRowHitRate 62.54
+system.physmem.avgGap 2123809.68
+system.physmem.pageHitRate 90.62
+system.physmem_0.actEnergy 11052720
+system.physmem_0.preEnergy 5855685
+system.physmem_0.readEnergy 113040480
+system.physmem_0.writeEnergy 1357200
+system.physmem_0.refreshEnergy 309163920.000000
+system.physmem_0.actBackEnergy 263324610
+system.physmem_0.preBackEnergy 16569120
+system.physmem_0.actPowerDownEnergy 979073610
+system.physmem_0.prePowerDownEnergy 268447200
+system.physmem_0.selfRefreshEnergy 14975920920
+system.physmem_0.totalEnergy 16943805465
+system.physmem_0.averagePower 257.812234
+system.physmem_0.totalIdleTime 65100637750
+system.physmem_0.memoryStateTime::IDLE 22061500
+system.physmem_0.memoryStateTime::REF 131194000
+system.physmem_0.memoryStateTime::SREF 62254705500
+system.physmem_0.memoryStateTime::PRE_PDN 699065250
+system.physmem_0.memoryStateTime::ACT 467433500
+system.physmem_0.memoryStateTime::ACT_PDN 2147034750
+system.physmem_1.actEnergy 9374820
+system.physmem_1.preEnergy 4967655
+system.physmem_1.readEnergy 104822340
+system.physmem_1.writeEnergy 46980
+system.physmem_1.refreshEnergy 372471840.000000
+system.physmem_1.actBackEnergy 249536310
+system.physmem_1.preBackEnergy 19488480
+system.physmem_1.actPowerDownEnergy 1119740490
+system.physmem_1.prePowerDownEnergy 403290240
+system.physmem_1.selfRefreshEnergy 14835337125
+system.physmem_1.totalEnergy 17119488570
+system.physmem_1.averagePower 260.485370
+system.physmem_1.totalIdleTime 65120969250
+system.physmem_1.memoryStateTime::IDLE 28589000
+system.physmem_1.memoryStateTime::REF 158136000
+system.physmem_1.memoryStateTime::SREF 61616793750
+system.physmem_1.memoryStateTime::PRE_PDN 1050209250
+system.physmem_1.memoryStateTime::ACT 412212500
+system.physmem_1.memoryStateTime::ACT_PDN 2455554000
+system.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.cpu.branchPred.lookups 40406290
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+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6228719
+system.cpu.toL2Bus.pkt_count::total 6231007
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 75968
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265248448
+system.cpu.toL2Bus.pkt_size::total 265324416
+system.cpu.toL2Bus.snoops 680
+system.cpu.toL2Bus.snoopTraffic 19136
+system.cpu.toL2Bus.snoop_fanout::samples 2079386
+system.cpu.toL2Bus.snoop_fanout::mean 0.000170
+system.cpu.toL2Bus.snoop_fanout::stdev 0.013047
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 2079032 99.98% 99.98%
+system.cpu.toL2Bus.snoop_fanout::1 354 0.02% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 2079386
+system.cpu.toL2Bus.reqLayer0.occupancy 4143138500
+system.cpu.toL2Bus.reqLayer0.utilization 6.3
+system.cpu.toL2Bus.respLayer0.occupancy 1652498
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 3116407500
+system.cpu.toL2Bus.respLayer1.utilization 4.7
+system.membus.snoop_filter.tot_requests 30996
+system.membus.snoop_filter.hit_single_requests 350
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 65721494500
+system.membus.trans_dist::ReadResp 1650
+system.membus.trans_dist::WritebackDirty 299
+system.membus.trans_dist::CleanEvict 51
+system.membus.trans_dist::ReadExReq 28996
+system.membus.trans_dist::ReadExResp 28996
+system.membus.trans_dist::ReadSharedReq 1650
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61642
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61642
+system.membus.pkt_count::total 61642
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1980480
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1980480
+system.membus.pkt_size::total 1980480
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 30646
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 30646 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 30646
+system.membus.reqLayer0.occupancy 43591500
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 161486250
+system.membus.respLayer1.utilization 0.2
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 420cd8ed8..03e352749 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -85,6 +86,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -100,14 +102,14 @@ eventq_index=0
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -121,6 +123,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -133,15 +136,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -187,6 +191,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -199,15 +204,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -274,6 +280,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -286,15 +293,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -330,7 +338,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=mcf mcf.in
cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
drivers=
@@ -339,14 +347,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/mcf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/mcf/smred/input/mcf.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=55300000000
system=system
uid=100
@@ -370,6 +379,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -381,7 +391,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -389,6 +399,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -397,6 +414,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -404,7 +422,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:268435455
+range=0:268435455:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
index aadc3d011..c0b55d123 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
@@ -1,2 +1,3 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 657298ab6..712b4d61b 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:18
-gem5 executing on e108600-lin, pid 18549
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/10.mcf/x86/linux/simple-timing
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:08:56
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 90898
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
MCF SPEC version 1.6.I
by Andreas Loebel
@@ -26,4 +25,4 @@ simplex iterations : 2663
flow value : 3080014995
checksum : 68389
optimal
-Exiting @ tick 366199170500 because target called exit()
+Exiting @ tick 366229314500 because exiting with last active thread context
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
index 957a0aa1f..275d179a2 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
@@ -1,541 +1,541 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.366229 # Number of seconds simulated
-sim_ticks 366229314500 # Number of ticks simulated
-final_tick 366229314500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1002365 # Simulator instruction rate (inst/s)
-host_op_rate 1765004 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2323557450 # Simulator tick rate (ticks/s)
-host_mem_usage 412036 # Number of bytes of host memory used
-host_seconds 157.62 # Real time elapsed on the host
-sim_insts 157988548 # Number of instructions simulated
-sim_ops 278192465 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1871552 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1922944 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 51392 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 51392 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6656 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6656 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 803 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 29243 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 30046 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 104 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 104 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 140327 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 5110328 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 5250656 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 140327 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 140327 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 18174 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 18174 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 18174 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 140327 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 5110328 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 5268830 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 444 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 732458629 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 157988548 # Number of instructions committed
-system.cpu.committedOps 278192465 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 278169482 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
-system.cpu.num_func_calls 8475189 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18628007 # number of instructions that are conditional controls
-system.cpu.num_int_insts 278169482 # number of integer instructions
-system.cpu.num_fp_insts 40 # number of float instructions
-system.cpu.num_int_register_reads 635379407 # number of times the integer registers were read
-system.cpu.num_int_register_writes 217447860 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 40 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 26 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 104140596 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 61764861 # number of times the CC registers were written
-system.cpu.num_mem_refs 122219137 # number of memory refs
-system.cpu.num_load_insts 90779385 # Number of load instructions
-system.cpu.num_store_insts 31439752 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 732458628.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 29309705 # Number of branches fetched
-system.cpu.op_class::No_OpClass 16695 0.01% 0.01% # Class of executed instruction
-system.cpu.op_class::IntAlu 155945354 56.06% 56.06% # Class of executed instruction
-system.cpu.op_class::IntMult 10938 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::IntDiv 329 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatAdd 12 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 56.07% # Class of executed instruction
-system.cpu.op_class::MemRead 90779371 32.63% 88.70% # Class of executed instruction
-system.cpu.op_class::MemWrite 31439738 11.30% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 14 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 14 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 278192465 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 366229314500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 2062733 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4076.272883 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 126128435500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4076.272883 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.995184 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.995184 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1776 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2198 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id
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+system.cpu.toL2Bus.snoop_fanout::samples 2067952
+system.cpu.toL2Bus.snoop_fanout::mean 0.000095
+system.cpu.toL2Bus.snoop_fanout::stdev 0.009760
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 2067755 99.99% 99.99%
+system.cpu.toL2Bus.snoop_fanout::1 197 0.01% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 2067952
+system.cpu.toL2Bus.reqLayer0.occupancy 4127703000
+system.cpu.toL2Bus.reqLayer0.utilization 1.1
+system.cpu.toL2Bus.respLayer0.occupancy 1212000
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 3100243500
+system.cpu.toL2Bus.respLayer1.utilization 0.8
+system.membus.snoop_filter.tot_requests 30164
+system.membus.snoop_filter.hit_single_requests 118
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 366229314500
+system.membus.trans_dist::ReadResp 1022
+system.membus.trans_dist::WritebackDirty 104
+system.membus.trans_dist::CleanEvict 14
+system.membus.trans_dist::ReadExReq 29024
+system.membus.trans_dist::ReadExResp 29024
+system.membus.trans_dist::ReadSharedReq 1022
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60210
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60210
+system.membus.pkt_count::total 60210
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929600
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929600
+system.membus.pkt_size::total 1929600
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 30046
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 30046 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 30046
+system.membus.reqLayer0.occupancy 30614500
+system.membus.reqLayer0.utilization 0.0
+system.membus.respLayer1.occupancy 150230000
+system.membus.respLayer1.utilization 0.0
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 4329f3215..e92ae69a2 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=114600000000
system=system
uid=100
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
index caeab8324..edc1e135d 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
@@ -1,4 +1,7 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index 87601728e..9e9d8d4ce 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:43:00
-gem5 executing on e108600-lin, pid 17328
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 18:14:44
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57363
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1
Processing sentences in batch mode
-info: Increasing stack size by one page.
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -70,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 236034256000 because target called exit()
+Exiting @ tick 235850129000 because exiting with last active thread context
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
index 774d0b356..90cdb7653 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
@@ -1,1276 +1,1276 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.235850 # Number of seconds simulated
-sim_ticks 235850129000 # Number of ticks simulated
-final_tick 235850129000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 254127 # Simulator instruction rate (inst/s)
-host_op_rate 275309 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 118629630 # Simulator tick rate (ticks/s)
-host_mem_usage 302132 # Number of bytes of host memory used
-host_seconds 1988.12 # Real time elapsed on the host
-sim_insts 505234934 # Number of instructions simulated
-sim_ops 547348155 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 651264 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10497792 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048 # Number of bytes read from this memory
-system.physmem.bytes_read::total 27559104 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 651264 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 651264 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18653440 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18653440 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 10176 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 164028 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 256407 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 430611 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 291460 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 291460 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 2761347 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 44510436 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 69578287 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 116850070 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 2761347 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 2761347 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 79090226 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 79090226 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 79090226 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 2761347 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 44510436 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 69578287 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 195940296 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 430611 # Number of read requests accepted
-system.physmem.writeReqs 291460 # Number of write requests accepted
-system.physmem.readBursts 430611 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 291460 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 27396288 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 162816 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18651392 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 27559104 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18653440 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 2544 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 9 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 27102 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26174 # Per bank write bursts
-system.physmem.perBankRdBursts::2 25664 # Per bank write bursts
-system.physmem.perBankRdBursts::3 33006 # Per bank write bursts
-system.physmem.perBankRdBursts::4 27996 # Per bank write bursts
-system.physmem.perBankRdBursts::5 29984 # Per bank write bursts
-system.physmem.perBankRdBursts::6 25487 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24586 # Per bank write bursts
-system.physmem.perBankRdBursts::8 25526 # Per bank write bursts
-system.physmem.perBankRdBursts::9 25681 # Per bank write bursts
-system.physmem.perBankRdBursts::10 25862 # Per bank write bursts
-system.physmem.perBankRdBursts::11 26092 # Per bank write bursts
-system.physmem.perBankRdBursts::12 27614 # Per bank write bursts
-system.physmem.perBankRdBursts::13 26106 # Per bank write bursts
-system.physmem.perBankRdBursts::14 25123 # Per bank write bursts
-system.physmem.perBankRdBursts::15 26064 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18530 # Per bank write bursts
-system.physmem.perBankWrBursts::1 18172 # Per bank write bursts
-system.physmem.perBankWrBursts::2 17960 # Per bank write bursts
-system.physmem.perBankWrBursts::3 17946 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18535 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18092 # Per bank write bursts
-system.physmem.perBankWrBursts::6 17937 # Per bank write bursts
-system.physmem.perBankWrBursts::7 17864 # Per bank write bursts
-system.physmem.perBankWrBursts::8 17881 # Per bank write bursts
-system.physmem.perBankWrBursts::9 17814 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18253 # Per bank write bursts
-system.physmem.perBankWrBursts::11 18685 # Per bank write bursts
-system.physmem.perBankWrBursts::12 18794 # Per bank write bursts
-system.physmem.perBankWrBursts::13 18180 # Per bank write bursts
-system.physmem.perBankWrBursts::14 18427 # Per bank write bursts
-system.physmem.perBankWrBursts::15 18358 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 235850076500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 430611 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 291460 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 318665 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 60579 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 13349 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7328 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 6151 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 5231 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4311 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3288 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 74 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 37 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 14 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6820 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 7302 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 12035 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 14838 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 16182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 16933 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17312 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17637 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17893 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 18126 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 18306 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 18426 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 18598 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 18683 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 18906 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 18563 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17444 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17201 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 121 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 24 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 18 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 329170 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 139.885214 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 98.537517 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 178.782393 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 329170 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17054 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 25.096224 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 145.074041 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17054 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17054 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.088542 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.022727 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.689258 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-33 2 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::34-35 1 0.01% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-37 1 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::42-43 3 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::46-47 1 0.01% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::62-63 1 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::74-75 2 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17054 # Writes before turning the bus around for reads
-system.physmem.totQLat 14249250266 # Total ticks spent queuing
-system.physmem.totMemAccLat 22275506516 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2140335000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 33287.43 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 52037.43 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 116.16 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 79.08 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 116.85 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 79.09 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.53 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.62 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.13 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing
-system.physmem.readRowHits 308139 # Number of row buffer hits during reads
-system.physmem.writeRowHits 82177 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 71.98 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 28.20 # Row buffer hit rate for writes
-system.physmem.avgGap 326630.04 # Average gap between requests
-system.physmem.pageHitRate 54.25 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1195207440 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 635245050 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1570792860 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 757087920 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 15735398640.000004 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 13510945980 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 615046560 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 46117601610 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 17430135360 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 15587831640 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 113161874670 # Total energy per rank (pJ)
-system.physmem_0.averagePower 479.804155 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 204603400415 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 912794276 # Time in different power states
-system.physmem_0.memoryStateTime::REF 6674692000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 58078463500 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 45390268663 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 23659127059 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 101134783502 # Time in different power states
-system.physmem_1.actEnergy 1155130620 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 613955100 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1485605520 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 764166240 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 15039011520.000004 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 13474802850 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 604322400 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 42537889890 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 17081497440 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 17718944700 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 110481339780 # Total energy per rank (pJ)
-system.physmem_1.averagePower 468.438739 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 204713337667 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 914400899 # Time in different power states
-system.physmem_1.memoryStateTime::REF 6380142000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 66945121250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 44482448304 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 23842248434 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 93285768113 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 174426540 # Number of BP lookups
-system.cpu.branchPred.condPredicted 130958868 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 7258964 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 89936054 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 78903188 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 87.732544 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 12071651 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 104612 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 4685817 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 4672093 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 13724 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 53795 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 548 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 471700259 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 7689412 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 726848478 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 174426540 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 95646932 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 455559849 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 14571167 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 7088 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 169 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 15067 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 235109896 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 36736 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 470557168 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.672087 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.189865 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 101222144 21.51% 21.51% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 131885544 28.03% 49.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 57421464 12.20% 61.74% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 180028016 38.26% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 470557168 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.369783 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.540912 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32637512 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 125886415 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 282414401 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 22855437 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 6763403 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 71909343 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 530427 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 710086582 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 29127059 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 6763403 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 63488458 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 61155779 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 40463668 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 273022741 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 25663119 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 681926435 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 12775010 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 10060236 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 2531231 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 1813266 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 2373970 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 826391408 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2997146717 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 717894841 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 654095674 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 172295734 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 1545774 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 1536126 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 43961162 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 142203026 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 67513624 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 12913434 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 11193544 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 664083030 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 2979301 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 608560988 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 5743597 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 119714176 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 304959820 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1669 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 470557168 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.293277 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.104886 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 154355830 32.80% 32.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 100909501 21.44% 54.25% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 145256303 30.87% 85.12% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 63003898 13.39% 98.51% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 7030993 1.49% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 643 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 470557168 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 71776446 52.99% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 30 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 44249945 32.67% 85.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 19436717 14.35% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 9 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 22 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 412327933 67.75% 67.75% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 351836 0.06% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.81% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 133457436 21.93% 89.74% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 62423748 10.26% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 16 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 16 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 608560988 # Type of FU issued
-system.cpu.iq.rate 1.290143 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 135463169 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.222596 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1828885813 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 786805257 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 593918713 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 97 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 744024094 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 63 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 7272380 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 26319743 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 24134 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 29234 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 10653404 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 224604 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 23301 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 6763403 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 23756716 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 981361 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 668554311 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 142203026 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 67513624 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1490759 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 256987 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 586437 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29234 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3560929 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3767464 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 7328393 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 598121332 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 128978812 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 10439656 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1491980 # number of nop insts executed
-system.cpu.iew.exec_refs 189925083 # number of memory reference insts executed
-system.cpu.iew.exec_branches 131214447 # Number of branches executed
-system.cpu.iew.exec_stores 60946271 # Number of stores executed
-system.cpu.iew.exec_rate 1.268011 # Inst execution rate
-system.cpu.iew.wb_sent 595160432 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 593918729 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 349300209 # num instructions producing a value
-system.cpu.iew.wb_consumers 571006140 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.259102 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611728 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 106531473 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 6736784 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 453954004 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.208695 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.885174 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 225266208 49.62% 49.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 116316093 25.62% 75.25% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 43463338 9.57% 84.82% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 23021553 5.07% 89.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 11663985 2.57% 92.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 7751412 1.71% 94.17% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 8276330 1.82% 95.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 4247049 0.94% 96.93% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 13948036 3.07% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 453954004 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 506578818 # Number of instructions committed
-system.cpu.commit.committedOps 548692039 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 172743503 # Number of memory references committed
-system.cpu.commit.loads 115883283 # Number of loads committed
-system.cpu.commit.membars 1488542 # Number of memory barriers committed
-system.cpu.commit.branches 121552863 # Number of branches committed
-system.cpu.commit.fp_insts 16 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 448447003 # Number of committed integer instructions.
-system.cpu.commit.function_calls 9757362 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 375609314 68.46% 68.46% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 339219 0.06% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.52% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 115883283 21.12% 89.64% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 56860204 10.36% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 16 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 548692039 # Class of committed instruction
-system.cpu.commit.bw_lim_events 13948036 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 1095222342 # The number of ROB reads
-system.cpu.rob.rob_writes 1327086117 # The number of ROB writes
-system.cpu.timesIdled 14782 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 1143091 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 505234934 # Number of Instructions Simulated
-system.cpu.committedOps 547348155 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.933626 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.933626 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.071093 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.071093 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 609897818 # number of integer regfile reads
-system.cpu.int_regfile_writes 327085541 # number of integer regfile writes
-system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.cc_regfile_reads 2165040622 # number of cc regfile reads
-system.cpu.cc_regfile_writes 376344417 # number of cc regfile writes
-system.cpu.misc_regfile_reads 217537377 # number of misc regfile reads
-system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 2817480 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.627959 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 168773991 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2817992 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 59.891579 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 504701000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.627959 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999273 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999273 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 355076080 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 355076080 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 114071383 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 114071383 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 51722665 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 51722665 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 2778 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 2778 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488556 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 1488556 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 165794048 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 165794048 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 165796826 # number of overall hits
-system.cpu.dcache.overall_hits::total 165796826 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 4838662 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 4838662 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 2516384 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 2516384 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 10 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 10 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 65 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 65 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 7355046 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 7355046 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 7355056 # number of overall misses
-system.cpu.dcache.overall_misses::total 7355056 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 63735397500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 63735397500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 19938555937 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 19938555937 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 846000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 846000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 83673953437 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 83673953437 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 83673953437 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 83673953437 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 118910045 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 118910045 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 54239049 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 54239049 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 2788 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 2788 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488621 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 1488621 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 173149094 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 173149094 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 173151882 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 173151882 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040692 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.040692 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046394 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.046394 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003587 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.003587 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.042478 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.042478 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.042477 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.042477 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13172.111939 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 13172.111939 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7923.494958 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 7923.494958 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13015.384615 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13015.384615 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 11376.401104 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 11376.401104 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 11376.385637 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 11376.385637 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 14 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1100252 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 221126 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.666667 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 4.975679 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 2817480 # number of writebacks
-system.cpu.dcache.writebacks::total 2817480 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2540507 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 2540507 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1996523 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1996523 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 65 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 65 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 4537030 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 4537030 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 4537030 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 4537030 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2298155 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 2298155 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519861 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 519861 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 9 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 9 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2818016 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2818016 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2818025 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2818025 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32727255000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 32727255000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4791332496 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 4791332496 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1174000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1174000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37518587496 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 37518587496 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37519761496 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 37519761496 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019327 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019327 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009585 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009585 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003228 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003228 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016275 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016275 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.016275 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14240.664794 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14240.664794 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9216.564612 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9216.564612 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 130444.444444 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 130444.444444 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13313.830545 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 13313.830545 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13314.204628 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 13314.204628 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 76537 # number of replacements
-system.cpu.icache.tags.tagsinuse 465.899675 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 235023805 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 77049 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 3050.316098 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 116553680500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 465.899675 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.909960 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.909960 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 263 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 121 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 14 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 470296624 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 470296624 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
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-system.cpu.icache.ReadReq_hits::total 235023805 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 235023805 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 235023805 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 235023805 # number of overall hits
-system.cpu.icache.overall_hits::total 235023805 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 85967 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 85967 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 85967 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 85967 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 85967 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 1954653197 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 1954653197 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 1954653197 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 1954653197 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 1954653197 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 1954653197 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 235109772 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 235109772 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 235109772 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 235109772 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 235109772 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 235109772 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000366 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000366 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.000366 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.000366 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000366 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000366 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22737.250305 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 22737.250305 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 22737.250305 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 22737.250305 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 22737.250305 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 201943 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 7203 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 28.035957 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 76537 # number of writebacks
-system.cpu.icache.writebacks::total 76537 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8885 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 8885 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 8885 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 8885 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 8885 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 8885 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 77082 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 77082 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 77082 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 77082 # number of demand (read+write) MSHR misses
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-system.cpu.icache.overall_mshr_misses::total 77082 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1551815800 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 1551815800 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1551815800 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 1551815800 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1551815800 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 1551815800 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000328 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.000328 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000328 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.000328 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20132.012662 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20132.012662 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20132.012662 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20132.012662 # average overall mshr miss latency
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-system.cpu.l2cache.prefetcher.pfIdentified 8515198 # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit 454 # number of redundant prefetches already in prefetch queue
-system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
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-system.cpu.l2cache.prefetcher.pfSpanPage 744250 # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 390446 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 15006.522104 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 2698185 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 406039 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 6.645138 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 14933.160754 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 73.361350 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.911448 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.004478 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.915925 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022 107 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 15486 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3 51 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4 51 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 675 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5453 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6496 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2623 # Occupied blocks per task id
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-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945190 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 95374967 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 95374967 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
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-system.cpu.l2cache.WritebackDirty_hits::total 2350430 # number of WritebackDirty hits
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-system.cpu.l2cache.WritebackClean_hits::total 520007 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 516734 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 516734 # number of ReadExReq hits
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-system.cpu.l2cache.ReadCleanReq_hits::total 66859 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2131098 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 2131098 # number of ReadSharedReq hits
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-system.cpu.l2cache.overall_hits::total 2714691 # number of overall hits
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-system.cpu.l2cache.ReadCleanReq_misses::total 10187 # number of ReadCleanReq misses
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-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 13944331500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 13944331500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 973097500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14407254000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 15380351500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 973097500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14407254000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 21400232213 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 36780583713 # number of overall MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007057 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007057 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.132077 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.069837 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.069837 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.060174 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.132077 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.058208 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.183186 # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 60091.743408 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15666.666667 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15666.666667 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 125657.573290 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 125657.573290 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 95626.719733 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 95626.719733 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 86964.554554 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 86964.554554 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88288.806291 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 95626.719733 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 87833.578209 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 60091.743408 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69354.014216 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 5789124 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 99823 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 99226 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 597 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 2373057 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 2641890 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 543587 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 98986 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq 403295 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 33 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 522015 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 522015 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 77082 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 2295977 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 230663 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8453531 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8684194 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9829184 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 370499456 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 793778 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 18655808 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 3688848 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.034290 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.182859 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3688848 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5788579005 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 2.5 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 1506 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 115655928 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 4227026456 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 821093 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 414041 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 426929 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 291460 # Transaction distribution
-system.membus.trans_dist::CleanEvict 98986 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 36 # Transaction distribution
-system.membus.trans_dist::ReadExReq 3681 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3681 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 426930 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1251703 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 46212480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 430647 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 430647 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 430647 # Request fanout histogram
-system.membus.reqLayer0.occupancy 2213026745 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2279181090 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 1.0 # Layer utilization (%)
+sim_seconds 0.235850
+sim_ticks 235850129000
+final_tick 235850129000
+sim_freq 1000000000000
+host_inst_rate 106785
+host_op_rate 115686
+host_tick_rate 49848699
+host_mem_usage 313808
+host_seconds 4731.32
+sim_insts 505234934
+sim_ops 547348155
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 235850129000
+system.physmem.bytes_read::cpu.inst 651264
+system.physmem.bytes_read::cpu.data 10497792
+system.physmem.bytes_read::cpu.l2cache.prefetcher 16410048
+system.physmem.bytes_read::total 27559104
+system.physmem.bytes_inst_read::cpu.inst 651264
+system.physmem.bytes_inst_read::total 651264
+system.physmem.bytes_written::writebacks 18653440
+system.physmem.bytes_written::total 18653440
+system.physmem.num_reads::cpu.inst 10176
+system.physmem.num_reads::cpu.data 164028
+system.physmem.num_reads::cpu.l2cache.prefetcher 256407
+system.physmem.num_reads::total 430611
+system.physmem.num_writes::writebacks 291460
+system.physmem.num_writes::total 291460
+system.physmem.bw_read::cpu.inst 2761347
+system.physmem.bw_read::cpu.data 44510436
+system.physmem.bw_read::cpu.l2cache.prefetcher 69578287
+system.physmem.bw_read::total 116850070
+system.physmem.bw_inst_read::cpu.inst 2761347
+system.physmem.bw_inst_read::total 2761347
+system.physmem.bw_write::writebacks 79090226
+system.physmem.bw_write::total 79090226
+system.physmem.bw_total::writebacks 79090226
+system.physmem.bw_total::cpu.inst 2761347
+system.physmem.bw_total::cpu.data 44510436
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+system.physmem.bw_total::total 195940296
+system.physmem.readReqs 430611
+system.physmem.writeReqs 291460
+system.physmem.readBursts 430611
+system.physmem.writeBursts 291460
+system.physmem.bytesReadDRAM 27396288
+system.physmem.bytesReadWrQ 162816
+system.physmem.bytesWritten 18651392
+system.physmem.bytesReadSys 27559104
+system.physmem.bytesWrittenSys 18653440
+system.physmem.servicedByWrQ 2544
+system.physmem.mergedWrBursts 9
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 27102
+system.physmem.perBankRdBursts::1 26174
+system.physmem.perBankRdBursts::2 25664
+system.physmem.perBankRdBursts::3 33006
+system.physmem.perBankRdBursts::4 27996
+system.physmem.perBankRdBursts::5 29984
+system.physmem.perBankRdBursts::6 25487
+system.physmem.perBankRdBursts::7 24586
+system.physmem.perBankRdBursts::8 25526
+system.physmem.perBankRdBursts::9 25681
+system.physmem.perBankRdBursts::10 25862
+system.physmem.perBankRdBursts::11 26092
+system.physmem.perBankRdBursts::12 27614
+system.physmem.perBankRdBursts::13 26106
+system.physmem.perBankRdBursts::14 25123
+system.physmem.perBankRdBursts::15 26064
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+system.physmem.perBankWrBursts::1 18172
+system.physmem.perBankWrBursts::2 17960
+system.physmem.perBankWrBursts::3 17946
+system.physmem.perBankWrBursts::4 18535
+system.physmem.perBankWrBursts::5 18092
+system.physmem.perBankWrBursts::6 17937
+system.physmem.perBankWrBursts::7 17864
+system.physmem.perBankWrBursts::8 17881
+system.physmem.perBankWrBursts::9 17814
+system.physmem.perBankWrBursts::10 18253
+system.physmem.perBankWrBursts::11 18685
+system.physmem.perBankWrBursts::12 18794
+system.physmem.perBankWrBursts::13 18180
+system.physmem.perBankWrBursts::14 18427
+system.physmem.perBankWrBursts::15 18358
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 235850076500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
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+system.physmem.writePktSize::4 0
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+system.physmem.writePktSize::6 291460
+system.physmem.rdQLenPdf::0 318665
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+system.physmem.rdQLenPdf::3 9026
+system.physmem.rdQLenPdf::4 7328
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+system.physmem.wrQLenPdf::20 16933
+system.physmem.wrQLenPdf::21 17312
+system.physmem.wrQLenPdf::22 17637
+system.physmem.wrQLenPdf::23 17893
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+system.physmem.wrQLenPdf::62 0
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+system.physmem.bytesPerActivate::samples 329170
+system.physmem.bytesPerActivate::mean 139.885214
+system.physmem.bytesPerActivate::gmean 98.537517
+system.physmem.bytesPerActivate::stdev 178.782393
+system.physmem.bytesPerActivate::0-127 210239 63.87% 63.87%
+system.physmem.bytesPerActivate::128-255 79533 24.16% 88.03%
+system.physmem.bytesPerActivate::256-383 14816 4.50% 92.53%
+system.physmem.bytesPerActivate::384-511 7238 2.20% 94.73%
+system.physmem.bytesPerActivate::512-639 4909 1.49% 96.22%
+system.physmem.bytesPerActivate::640-767 2469 0.75% 96.97%
+system.physmem.bytesPerActivate::768-895 1818 0.55% 97.52%
+system.physmem.bytesPerActivate::896-1023 1563 0.47% 98.00%
+system.physmem.bytesPerActivate::1024-1151 6585 2.00% 100.00%
+system.physmem.bytesPerActivate::total 329170
+system.physmem.rdPerTurnAround::samples 17054
+system.physmem.rdPerTurnAround::mean 25.096224
+system.physmem.rdPerTurnAround::stdev 145.074041
+system.physmem.rdPerTurnAround::0-1023 17052 99.99% 99.99%
+system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99%
+system.physmem.rdPerTurnAround::18432-19455 1 0.01% 100.00%
+system.physmem.rdPerTurnAround::total 17054
+system.physmem.wrPerTurnAround::samples 17054
+system.physmem.wrPerTurnAround::mean 17.088542
+system.physmem.wrPerTurnAround::gmean 17.022727
+system.physmem.wrPerTurnAround::stdev 1.689258
+system.physmem.wrPerTurnAround::16-17 9980 58.52% 58.52%
+system.physmem.wrPerTurnAround::18-19 6296 36.92% 95.44%
+system.physmem.wrPerTurnAround::20-21 558 3.27% 98.71%
+system.physmem.wrPerTurnAround::22-23 128 0.75% 99.46%
+system.physmem.wrPerTurnAround::24-25 50 0.29% 99.75%
+system.physmem.wrPerTurnAround::26-27 15 0.09% 99.84%
+system.physmem.wrPerTurnAround::28-29 10 0.06% 99.90%
+system.physmem.wrPerTurnAround::30-31 6 0.04% 99.94%
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+system.cpu.toL2Bus.snoop_filter.tot_requests 5789124
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2894045
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 26043
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+system.cpu.toL2Bus.pkt_count::total 8684194
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+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 360670272
+system.cpu.toL2Bus.pkt_size::total 370499456
+system.cpu.toL2Bus.snoops 793778
+system.cpu.toL2Bus.snoopTraffic 18655808
+system.cpu.toL2Bus.snoop_fanout::samples 3688848
+system.cpu.toL2Bus.snoop_fanout::mean 0.034290
+system.cpu.toL2Bus.snoop_fanout::stdev 0.182859
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 3562956 96.59% 96.59%
+system.cpu.toL2Bus.snoop_fanout::1 125295 3.40% 99.98%
+system.cpu.toL2Bus.snoop_fanout::2 597 0.02% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 3688848
+system.cpu.toL2Bus.reqLayer0.occupancy 5788579005
+system.cpu.toL2Bus.reqLayer0.utilization 2.5
+system.cpu.toL2Bus.snoopLayer0.occupancy 1506
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 115655928
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 4227026456
+system.cpu.toL2Bus.respLayer1.utilization 1.8
+system.membus.snoop_filter.tot_requests 821093
+system.membus.snoop_filter.hit_single_requests 414041
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 235850129000
+system.membus.trans_dist::ReadResp 426929
+system.membus.trans_dist::WritebackDirty 291460
+system.membus.trans_dist::CleanEvict 98986
+system.membus.trans_dist::UpgradeReq 36
+system.membus.trans_dist::ReadExReq 3681
+system.membus.trans_dist::ReadExResp 3681
+system.membus.trans_dist::ReadSharedReq 426930
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1251703
+system.membus.pkt_count::total 1251703
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46212480
+system.membus.pkt_size::total 46212480
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 430647
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 430647 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 430647
+system.membus.reqLayer0.occupancy 2213026745
+system.membus.reqLayer0.utilization 0.9
+system.membus.respLayer1.occupancy 2279181090
+system.membus.respLayer1.utilization 1.0
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index 719526a91..bd579b4cb 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -90,6 +90,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -165,8 +166,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -177,8 +176,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -239,7 +236,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
drivers=
@@ -248,14 +245,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=114600000000
system=system
uid=100
@@ -279,6 +277,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -290,7 +289,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -298,6 +297,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -306,6 +312,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -313,7 +320,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
index aadc3d011..094173d40 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
@@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
index 6f63d3022..a36e35467 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-ato
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:38:22
-gem5 executing on e108600-lin, pid 23082
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 17:56:13
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54223
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1
Processing sentences in batch mode
-info: Increasing stack size by one page.
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -70,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 279360903000 because target called exit()
+Exiting @ tick 279360903000 because exiting with last active thread context
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
index f22db7f03..30c0da648 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.279361 # Number of seconds simulated
-sim_ticks 279360903000 # Number of ticks simulated
-final_tick 279360903000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2213544 # Simulator instruction rate (inst/s)
-host_op_rate 2397561 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1220693561 # Simulator tick rate (ticks/s)
-host_mem_usage 263256 # Number of bytes of host memory used
-host_seconds 228.85 # Real time elapsed on the host
-sim_insts 506578818 # Number of instructions simulated
-sim_ops 548692039 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 2066434344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 422848347 # Number of bytes read from this memory
-system.physmem.bytes_read::total 2489282691 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 2066434344 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 2066434344 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 216066596 # Number of bytes written to this memory
-system.physmem.bytes_written::total 216066596 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 516608586 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 115590054 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 632198640 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 55727590 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 55727590 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7397006245 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1513627506 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 8910633751 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7397006245 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7397006245 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 773431764 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 773431764 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7397006245 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2287059270 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 9684065515 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 548 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 279360903000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 558721807 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 506578818 # Number of instructions committed
-system.cpu.committedOps 548692039 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_func_calls 19311615 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
-system.cpu.num_int_insts 448447005 # number of integer instructions
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_int_register_reads 749023721 # number of times the integer registers were read
-system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 1634221880 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
-system.cpu.num_mem_refs 172743505 # number of memory refs
-system.cpu.num_load_insts 115883283 # Number of load instructions
-system.cpu.num_store_insts 56860222 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 558721806.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 121552863 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
-system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
-system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 548692589 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 630707528 # Transaction distribution
-system.membus.trans_dist::ReadResp 632196069 # Transaction distribution
-system.membus.trans_dist::WriteReq 54239049 # Transaction distribution
-system.membus.trans_dist::WriteResp 54239049 # Transaction distribution
-system.membus.trans_dist::SoftPFReq 2571 # Transaction distribution
-system.membus.trans_dist::SoftPFResp 2571 # Transaction distribution
-system.membus.trans_dist::LoadLockedReq 1488541 # Transaction distribution
-system.membus.trans_dist::StoreCondReq 1488541 # Transaction distribution
-system.membus.trans_dist::StoreCondResp 1488541 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1375852460 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 2705349287 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 687926230 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 687926230 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 687926230 # Request fanout histogram
+sim_seconds 0.279361
+sim_ticks 279360903000
+final_tick 279360903000
+sim_freq 1000000000000
+host_inst_rate 937755
+host_op_rate 1015713
+host_tick_rate 517139598
+host_mem_usage 274756
+host_seconds 540.20
+sim_insts 506578818
+sim_ops 548692039
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 279360903000
+system.physmem.bytes_read::cpu.inst 2066434344
+system.physmem.bytes_read::cpu.data 422848347
+system.physmem.bytes_read::total 2489282691
+system.physmem.bytes_inst_read::cpu.inst 2066434344
+system.physmem.bytes_inst_read::total 2066434344
+system.physmem.bytes_written::cpu.data 216066596
+system.physmem.bytes_written::total 216066596
+system.physmem.num_reads::cpu.inst 516608586
+system.physmem.num_reads::cpu.data 115590054
+system.physmem.num_reads::total 632198640
+system.physmem.num_writes::cpu.data 55727590
+system.physmem.num_writes::total 55727590
+system.physmem.bw_read::cpu.inst 7397006245
+system.physmem.bw_read::cpu.data 1513627506
+system.physmem.bw_read::total 8910633751
+system.physmem.bw_inst_read::cpu.inst 7397006245
+system.physmem.bw_inst_read::total 7397006245
+system.physmem.bw_write::cpu.data 773431764
+system.physmem.bw_write::total 773431764
+system.physmem.bw_total::cpu.inst 7397006245
+system.physmem.bw_total::cpu.data 2287059270
+system.physmem.bw_total::total 9684065515
+system.pwrStateResidencyTicks::UNDEFINED 279360903000
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
+system.cpu.dtb.walker.walks 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dtb.walker.walkRequestOrigin::total 0
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.flush_tlb 0
+system.cpu.dtb.flush_tlb_mva 0
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 0
+system.cpu.dtb.align_faults 0
+system.cpu.dtb.prefetch_faults 0
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 279360903000
+system.cpu.itb.walker.walks 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.itb.walker.walkRequestOrigin::total 0
+system.cpu.itb.inst_hits 0
+system.cpu.itb.inst_misses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 0
+system.cpu.itb.flush_tlb_mva 0
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 0
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 548
+system.cpu.pwrStateResidencyTicks::ON 279360903000
+system.cpu.numCycles 558721807
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 506578818
+system.cpu.committedOps 548692039
+system.cpu.num_int_alu_accesses 448447005
+system.cpu.num_fp_alu_accesses 16
+system.cpu.num_func_calls 19311615
+system.cpu.num_conditional_control_insts 90670594
+system.cpu.num_int_insts 448447005
+system.cpu.num_fp_insts 16
+system.cpu.num_int_register_reads 749023721
+system.cpu.num_int_register_writes 289993515
+system.cpu.num_fp_register_reads 16
+system.cpu.num_fp_register_writes 0
+system.cpu.num_cc_register_reads 1634221880
+system.cpu.num_cc_register_writes 344062197
+system.cpu.num_mem_refs 172743505
+system.cpu.num_load_insts 115883283
+system.cpu.num_store_insts 56860222
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 558721807
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 121552863
+system.cpu.op_class::No_OpClass 0 0.00% 0.00%
+system.cpu.op_class::IntAlu 375609862 68.46% 68.46%
+system.cpu.op_class::IntMult 339219 0.06% 68.52%
+system.cpu.op_class::IntDiv 0 0.00% 68.52%
+system.cpu.op_class::FloatAdd 0 0.00% 68.52%
+system.cpu.op_class::FloatCmp 0 0.00% 68.52%
+system.cpu.op_class::FloatCvt 0 0.00% 68.52%
+system.cpu.op_class::FloatMult 0 0.00% 68.52%
+system.cpu.op_class::FloatMultAcc 0 0.00% 68.52%
+system.cpu.op_class::FloatDiv 0 0.00% 68.52%
+system.cpu.op_class::FloatMisc 0 0.00% 68.52%
+system.cpu.op_class::FloatSqrt 0 0.00% 68.52%
+system.cpu.op_class::SimdAdd 0 0.00% 68.52%
+system.cpu.op_class::SimdAddAcc 0 0.00% 68.52%
+system.cpu.op_class::SimdAlu 0 0.00% 68.52%
+system.cpu.op_class::SimdCmp 0 0.00% 68.52%
+system.cpu.op_class::SimdCvt 0 0.00% 68.52%
+system.cpu.op_class::SimdMisc 0 0.00% 68.52%
+system.cpu.op_class::SimdMult 0 0.00% 68.52%
+system.cpu.op_class::SimdMultAcc 0 0.00% 68.52%
+system.cpu.op_class::SimdShift 0 0.00% 68.52%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52%
+system.cpu.op_class::SimdSqrt 0 0.00% 68.52%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52%
+system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52%
+system.cpu.op_class::SimdFloatMult 0 0.00% 68.52%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52%
+system.cpu.op_class::MemRead 115883283 21.12% 89.64%
+system.cpu.op_class::MemWrite 56860206 10.36% 100.00%
+system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
+system.cpu.op_class::FloatMemWrite 16 0.00% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 548692589
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 279360903000
+system.membus.trans_dist::ReadReq 630707528
+system.membus.trans_dist::ReadResp 632196069
+system.membus.trans_dist::WriteReq 54239049
+system.membus.trans_dist::WriteResp 54239049
+system.membus.trans_dist::SoftPFReq 2571
+system.membus.trans_dist::SoftPFResp 2571
+system.membus.trans_dist::LoadLockedReq 1488541
+system.membus.trans_dist::StoreCondReq 1488541
+system.membus.trans_dist::StoreCondResp 1488541
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1033217172
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 342635288
+system.membus.pkt_count::total 1375852460
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2066434344
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638914943
+system.membus.pkt_size::total 2705349287
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 687926230
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 687926230 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 687926230
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index cc618b726..cd5fa2511 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -87,6 +87,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=parser 2.1.dict -batch
cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
drivers=
@@ -411,14 +414,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/parser
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=114600000000
system=system
uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -461,6 +466,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
index aadc3d011..094173d40 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
@@ -1,2 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
index 1889b3430..e4542abd6 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
@@ -3,13 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:38:21
-gem5 executing on e108600-lin, pid 23071
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 18:35:18
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 61430
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
Reading the dictionary files: *************************************************
@@ -20,12 +19,10 @@ Welcome to the Link Parser -- Version 2.1
Processing sentences in batch mode
-info: Increasing stack size by one page.
Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -70,4 +67,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 708539449500 because target called exit()
+Exiting @ tick 708700329500 because exiting with last active thread context
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
index 072f29102..78d65a20d 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
@@ -1,685 +1,685 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.708700 # Number of seconds simulated
-sim_ticks 708700329500 # Number of ticks simulated
-final_tick 708700329500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1580290 # Simulator instruction rate (inst/s)
-host_op_rate 1711383 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2217795996 # Simulator tick rate (ticks/s)
-host_mem_usage 275040 # Number of bytes of host memory used
-host_seconds 319.55 # Real time elapsed on the host
-sim_insts 504984064 # Number of instructions simulated
-sim_ops 546875315 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 147392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 8988096 # Number of bytes read from this memory
-system.physmem.bytes_read::total 9135488 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 147392 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 147392 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6185472 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6185472 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2303 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 140439 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 142742 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 96648 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 96648 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 207975 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 12682506 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12890481 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 207975 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 207975 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 8727909 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 8727909 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 8727909 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 207975 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 12682506 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 21618390 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 708700329500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 548 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 708700329500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1417400659 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 504984064 # Number of instructions committed
-system.cpu.committedOps 546875315 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 448447005 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
-system.cpu.num_func_calls 19311615 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 90670594 # number of instructions that are conditional controls
-system.cpu.num_int_insts 448447005 # number of integer instructions
-system.cpu.num_fp_insts 16 # number of float instructions
-system.cpu.num_int_register_reads 748339627 # number of times the integer registers were read
-system.cpu.num_int_register_writes 289993515 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 1984285070 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 344062197 # number of times the CC registers were written
-system.cpu.num_mem_refs 172743505 # number of memory refs
-system.cpu.num_load_insts 115883283 # Number of load instructions
-system.cpu.num_store_insts 56860222 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 1417400658.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 121552863 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 375609862 68.46% 68.46% # Class of executed instruction
-system.cpu.op_class::IntMult 339219 0.06% 68.52% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 3 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.52% # Class of executed instruction
-system.cpu.op_class::MemRead 115883283 21.12% 89.64% # Class of executed instruction
-system.cpu.op_class::MemWrite 56860206 10.36% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 16 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19166.085277 # average overall miss latency
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-system.cpu.dcache.overall_mshr_misses::total 1140372 # number of overall MSHR misses
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-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26153.212551 # average WriteReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18166.102084 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18166.140523 # average overall mshr miss latency
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-system.cpu.icache.tags.age_task_id_blocks_1024::3 256 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1402 # Occupied blocks per task id
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-system.cpu.icache.ReadReq_avg_miss_latency::total 23046.002951 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 23046.002951 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 23046.002951 # average overall miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22046.002951 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 22046.002951 # average overall mshr miss latency
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31936 # Occupied blocks per task id
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-system.cpu.l2cache.WritebackDirty_hits::total 1065429 # number of WritebackDirty hits
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-system.cpu.l2cache.WritebackClean_hits::total 9751 # number of WritebackClean hits
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-system.cpu.l2cache.ReadExReq_hits::total 255675 # number of ReadExReq hits
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-system.cpu.l2cache.ReadCleanReq_hits::total 9218 # number of ReadCleanReq hits
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+system.cpu.l2cache.demand_accesses::cpu.data 1140372
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+system.cpu.l2cache.overall_accesses::cpu.data 1140372
+system.cpu.l2cache.overall_accesses::total 1151893
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60587.928789
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+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.writebacks::writebacks 96648
+system.cpu.l2cache.writebacks::total 96648
+system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 2
+system.cpu.l2cache.CleanEvict_mshr_misses::total 2
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7098557500
+system.cpu.l2cache.demand_mshr_miss_latency::total 7215061500
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+system.cpu.l2cache.overall_mshr_miss_latency::total 7215061500
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.282835
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.282835
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199896
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+system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919
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+system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50540.170381
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50540.170381
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50587.928789
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50546.170714
+system.cpu.toL2Bus.snoop_filter.tot_requests 2297957
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 1146116
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3565
+system.cpu.toL2Bus.snoop_filter.tot_snoops 2153
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2152
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 708700329500
+system.cpu.toL2Bus.trans_dist::ReadResp 795385
+system.cpu.toL2Bus.trans_dist::WritebackDirty 1162077
+system.cpu.toL2Bus.trans_dist::WritebackClean 9788
+system.cpu.toL2Bus.trans_dist::CleanEvict 85012
+system.cpu.toL2Bus.trans_dist::ReadExReq 356508
+system.cpu.toL2Bus.trans_dist::ReadExResp 356508
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 11521
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 783864
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 32830
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3417020
+system.cpu.toL2Bus.pkt_count::total 3449850
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1363776
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141171264
+system.cpu.toL2Bus.pkt_size::total 142535040
+system.cpu.toL2Bus.snoops 110813
+system.cpu.toL2Bus.snoopTraffic 6185472
+system.cpu.toL2Bus.snoop_fanout::samples 1262706
+system.cpu.toL2Bus.snoop_fanout::mean 0.004570
+system.cpu.toL2Bus.snoop_fanout::stdev 0.067461
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1256936 99.54% 99.54%
+system.cpu.toL2Bus.snoop_fanout::1 5769 0.46% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 1262706
+system.cpu.toL2Bus.reqLayer0.occupancy 2224195500
+system.cpu.toL2Bus.reqLayer0.utilization 0.3
+system.cpu.toL2Bus.respLayer0.occupancy 17281500
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 1710558000
+system.cpu.toL2Bus.respLayer1.utilization 0.2
+system.membus.snoop_filter.tot_requests 251405
+system.membus.snoop_filter.hit_single_requests 108784
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 708700329500
+system.membus.trans_dist::ReadResp 41909
+system.membus.trans_dist::WritebackDirty 96648
+system.membus.trans_dist::CleanEvict 12014
+system.membus.trans_dist::ReadExReq 100833
+system.membus.trans_dist::ReadExResp 100833
+system.membus.trans_dist::ReadSharedReq 41909
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 394146
+system.membus.pkt_count::total 394146
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15320960
+system.membus.pkt_size::total 15320960
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 142743
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 142743 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 142743
+system.membus.reqLayer0.occupancy 644372828
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 713710000
+system.membus.respLayer1.utilization 0.1
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 246d6b579..a38a74511 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -65,7 +66,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -139,6 +140,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -183,10 +185,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -200,6 +202,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -212,15 +215,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -313,10 +317,10 @@ pipelined=true
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList0 opList1 opList2
+children=opList0 opList1 opList2 opList3 opList4
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4
[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
@@ -328,11 +332,25 @@ pipelined=true
[system.cpu.fuPool.FUList3.opList1]
type=OpDesc
eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
+[system.cpu.fuPool.FUList3.opList3]
+type=OpDesc
+eventq_index=0
opClass=FloatDiv
opLat=12
pipelined=false
-[system.cpu.fuPool.FUList3.opList2]
+[system.cpu.fuPool.FUList3.opList4]
type=OpDesc
eventq_index=0
opClass=FloatSqrt
@@ -341,18 +359,25 @@ pipelined=false
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList
+children=opList0 opList1
count=0
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList
+opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1
-[system.cpu.fuPool.FUList4.opList]
+[system.cpu.fuPool.FUList4.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=1
pipelined=true
+[system.cpu.fuPool.FUList4.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
[system.cpu.fuPool.FUList5]
type=FUDesc
children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
@@ -502,24 +527,31 @@ pipelined=true
[system.cpu.fuPool.FUList6]
type=FUDesc
-children=opList
+children=opList0 opList1
count=0
eventq_index=0
-opList=system.cpu.fuPool.FUList6.opList
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
-[system.cpu.fuPool.FUList6.opList]
+[system.cpu.fuPool.FUList6.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=1
pipelined=true
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
[system.cpu.fuPool.FUList7]
type=FUDesc
-children=opList0 opList1
+children=opList0 opList1 opList2 opList3
count=4
eventq_index=0
-opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
+opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3
[system.cpu.fuPool.FUList7.opList0]
type=OpDesc
@@ -535,6 +567,20 @@ opClass=MemWrite
opLat=1
pipelined=true
+[system.cpu.fuPool.FUList7.opList2]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=1
+pipelined=true
+
+[system.cpu.fuPool.FUList7.opList3]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=1
+pipelined=true
+
[system.cpu.fuPool.FUList8]
type=FUDesc
children=opList
@@ -556,10 +602,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -573,6 +619,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -585,15 +632,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -643,10 +691,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -660,6 +708,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -672,15 +721,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -716,7 +766,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=parser 2.1.dict -batch
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
drivers=
@@ -725,14 +775,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=114600000000
system=system
uid=100
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
index bbcd9d751..630e657e6 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
@@ -1,3 +1,18 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 94b6c45b2..e7ed8f409 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -3,17 +3,13 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 21:09:23
-gem5 executing on e108600-lin, pid 17649
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:06:22
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87198
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
Reading the dictionary files: *************************************************
58924 words stored in 3784810 bytes
@@ -72,4 +68,4 @@ Echoing of input sentence turned on.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 487015166000 because target called exit()
+Exiting @ tick 487050729500 because exiting with last active thread context
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
index 699c09a91..72edf9459 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
@@ -1,1092 +1,1092 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.487051 # Number of seconds simulated
-sim_ticks 487050729500 # Number of ticks simulated
-final_tick 487050729500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 151835 # Simulator instruction rate (inst/s)
-host_op_rate 280970 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 89437473 # Simulator tick rate (ticks/s)
-host_mem_usage 318556 # Number of bytes of host memory used
-host_seconds 5445.71 # Real time elapsed on the host
-sim_insts 826847303 # Number of instructions simulated
-sim_ops 1530082520 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 156352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24658560 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24814912 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 156352 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 156352 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18911424 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18911424 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 2443 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 385290 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 387733 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 295491 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 295491 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 321018 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 50628320 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 50949338 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 321018 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 321018 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 38828448 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 38828448 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 38828448 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 321018 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 50628320 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 89777786 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 387733 # Number of read requests accepted
-system.physmem.writeReqs 295491 # Number of write requests accepted
-system.physmem.readBursts 387733 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 295491 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24795072 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 19840 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18909504 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24814912 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18911424 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 310 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24612 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26389 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24828 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24571 # Per bank write bursts
-system.physmem.perBankRdBursts::4 23534 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23661 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24754 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24509 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23888 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23557 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24834 # Per bank write bursts
-system.physmem.perBankRdBursts::11 24002 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23243 # Per bank write bursts
-system.physmem.perBankRdBursts::13 22894 # Per bank write bursts
-system.physmem.perBankRdBursts::14 23905 # Per bank write bursts
-system.physmem.perBankRdBursts::15 24242 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18972 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19954 # Per bank write bursts
-system.physmem.perBankWrBursts::2 19038 # Per bank write bursts
-system.physmem.perBankWrBursts::3 19006 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18208 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18444 # Per bank write bursts
-system.physmem.perBankWrBursts::6 19174 # Per bank write bursts
-system.physmem.perBankWrBursts::7 19116 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18744 # Per bank write bursts
-system.physmem.perBankWrBursts::9 17955 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18923 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17774 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17399 # Per bank write bursts
-system.physmem.perBankWrBursts::13 16985 # Per bank write bursts
-system.physmem.perBankWrBursts::14 17804 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17965 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 487050613500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 387733 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 295491 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 381263 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 5754 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 361 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 34 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6088 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6353 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 17482 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17661 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17684 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17682 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17687 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17686 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17693 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17689 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17695 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17698 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17697 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17702 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 17729 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17821 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17712 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17704 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 146416 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 298.484100 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 176.719176 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 324.748192 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 52816 36.07% 36.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 41066 28.05% 64.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13865 9.47% 73.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7498 5.12% 78.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4985 3.40% 82.12% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3806 2.60% 84.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 2894 1.98% 86.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2818 1.92% 88.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16668 11.38% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 146416 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17678 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 21.914866 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::gmean 18.161180 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 216.039339 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17672 99.97% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17678 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17678 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.713486 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.686282 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 0.965426 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 11315 64.01% 64.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 269 1.52% 65.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 5957 33.70% 99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 123 0.70% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 10 0.06% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 3 0.02% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17678 # Writes before turning the bus around for reads
-system.physmem.totQLat 9794922250 # Total ticks spent queuing
-system.physmem.totMemAccLat 17059103500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1937115000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 25282.24 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 44032.24 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 50.91 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 38.82 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 50.95 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 38.83 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.70 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.40 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.30 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 20.96 # Average write queue length when enqueuing
-system.physmem.readRowHits 316322 # Number of row buffer hits during reads
-system.physmem.writeRowHits 220133 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 81.65 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 74.50 # Row buffer hit rate for writes
-system.physmem.avgGap 712871.05 # Average gap between requests
-system.physmem.pageHitRate 78.55 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 538191780 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 286032945 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1405566120 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 792980640 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 13571251200.000004 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 8851881120 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 742850400 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 36305173020 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 16998972000 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 84070895340 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 163568832135 # Total energy per rank (pJ)
-system.physmem_0.averagePower 335.835307 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 465691902250 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 1184996500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 5763492000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 341808238000 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 44268234250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 14409717250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 79616051500 # Time in different power states
-system.physmem_1.actEnergy 507311280 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 269615775 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1360634100 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 749325780 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 13094905200.000004 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 8819547870 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 717418080 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 34208424030 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 16648938720 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 85396744800 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 161777173725 # Total energy per rank (pJ)
-system.physmem_1.averagePower 332.156722 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 465831856000 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 1145526000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 5561926000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 347456670000 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 43356567250 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 14511269750 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 75018770500 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 299198029 # Number of BP lookups
-system.cpu.branchPred.condPredicted 299198029 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 24258277 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 226066805 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 0 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 40193400 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 4437789 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 226066805 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 118144411 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 107922394 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 11883156 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 551 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 974101460 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 230169557 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1594277830 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 299198029 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 158337811 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 718471067 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 49469999 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 2698 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 34945 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 480096 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 4714 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 69 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 216546560 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 6526632 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 8 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 973898145 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.063667 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.497102 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 481357803 49.43% 49.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 36544666 3.75% 53.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 36285723 3.73% 56.90% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 32866211 3.37% 60.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 28367371 2.91% 63.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 29577354 3.04% 66.23% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 39843150 4.09% 70.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 36876934 3.79% 74.11% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 252178933 25.89% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 973898145 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.307153 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.636665 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 166490369 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 388298779 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 313723542 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 80650456 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 24734999 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2751923456 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 24734999 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 202899221 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 199700520 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 14210 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 351959746 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 194589449 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2631585273 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 503822 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 119585114 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 21729790 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 44646970 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2710512651 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 6600728549 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 4213051781 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 1976674 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1616961572 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 1093551079 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 884 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 794 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 367177164 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 608809294 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 243550763 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 252688912 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 75518257 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2418516015 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 104540 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1999668107 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 3656750 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 888538035 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1505526254 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 103988 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 973898145 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.053262 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.107501 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 345655298 35.49% 35.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 135232191 13.89% 49.38% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 129689064 13.32% 62.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 119012847 12.22% 74.91% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 97852872 10.05% 84.96% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 66913699 6.87% 91.83% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 45825912 4.71% 96.54% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 22646304 2.33% 98.86% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 11069958 1.14% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 973898145 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11137608 43.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 43.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 11929198 46.06% 89.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 2740827 10.58% 99.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.64% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 92541 0.36% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2900375 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1333719780 66.70% 66.84% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 357536 0.02% 66.86% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 4798411 0.24% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 4 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 1 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.10% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 471767183 23.59% 90.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 185670018 9.29% 99.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 6 0.00% 99.98% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 454793 0.02% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1999668107 # Type of FU issued
-system.cpu.iq.rate 2.052833 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 25900174 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.012952 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5001578236 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 3304560217 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1922724831 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 1213047 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 3212370 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 280288 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2022120560 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 547346 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 180407023 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 224726218 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 356451 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 693943 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 94392568 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 33314 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 814 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 24734999 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 149663879 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 6607902 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2418620555 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 1417513 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 608809531 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 243550763 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 36150 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1478128 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 4302509 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 693943 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 8551096 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 21778410 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 30329506 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1944942401 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 457167604 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 54725706 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 635670117 # number of memory reference insts executed
-system.cpu.iew.exec_branches 185387955 # Number of branches executed
-system.cpu.iew.exec_stores 178502513 # Number of stores executed
-system.cpu.iew.exec_rate 1.996653 # Inst execution rate
-system.cpu.iew.wb_sent 1933639401 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1923005119 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1456045504 # num instructions producing a value
-system.cpu.iew.wb_consumers 2200626785 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.974132 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.661650 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 888612801 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 24293835 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 840170563 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.821157 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.461954 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 361187525 42.99% 42.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 184077910 21.91% 64.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 57677028 6.86% 71.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 87256558 10.39% 82.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 30345133 3.61% 85.76% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 26488854 3.15% 88.91% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 10500866 1.25% 90.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 9042630 1.08% 91.24% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 73594059 8.76% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 840170563 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 826847303 # Number of instructions committed
-system.cpu.commit.committedOps 1530082520 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 533241508 # Number of memory references committed
-system.cpu.commit.loads 384083313 # Number of loads committed
-system.cpu.commit.membars 0 # Number of memory barriers committed
-system.cpu.commit.branches 149981740 # Number of branches committed
-system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1527470225 # Number of committed integer instructions.
-system.cpu.commit.function_calls 17673145 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 2048202 0.13% 0.13% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 989691028 64.68% 64.82% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 306834 0.02% 64.84% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 4794948 0.31% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.15% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 384083313 25.10% 90.25% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 149158195 9.75% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 1530082520 # Class of committed instruction
-system.cpu.commit.bw_lim_events 73594059 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 3185271825 # The number of ROB reads
-system.cpu.rob.rob_writes 4972894886 # The number of ROB writes
-system.cpu.timesIdled 2025 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 203315 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 826847303 # Number of Instructions Simulated
-system.cpu.committedOps 1530082520 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.178091 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.178091 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.848831 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.848831 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2927263565 # number of integer regfile reads
-system.cpu.int_regfile_writes 1575987355 # number of integer regfile writes
-system.cpu.fp_regfile_reads 281295 # number of floating regfile reads
-system.cpu.fp_regfile_writes 5 # number of floating regfile writes
-system.cpu.cc_regfile_reads 617980900 # number of cc regfile reads
-system.cpu.cc_regfile_writes 419571241 # number of cc regfile writes
-system.cpu.misc_regfile_reads 1064489388 # number of misc regfile reads
-system.cpu.misc_regfile_writes 1 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 2545571 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4088.077195 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 420813077 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 2549667 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 165.046289 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 1863239500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4088.077195 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.998066 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.998066 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 606 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 3449 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 850870799 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 850870799 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 272443625 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 272443625 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 148366897 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 148366897 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 420810522 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 420810522 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 420810522 # number of overall hits
-system.cpu.dcache.overall_hits::total 420810522 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2558730 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2558730 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 791314 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 791314 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 3350044 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3350044 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3350044 # number of overall misses
-system.cpu.dcache.overall_misses::total 3350044 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 62817542000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 62817542000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 26367570500 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 26367570500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 89185112500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 89185112500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 89185112500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 89185112500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 275002355 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 275002355 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 149158211 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 424160566 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 424160566 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 424160566 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 424160566 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.009304 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.009304 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005305 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.005305 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.007898 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.007898 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.007898 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.007898 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24550.281585 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 24550.281585 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33321.248581 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33321.248581 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 26622.071979 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 26622.071979 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 26622.071979 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 9991 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 13057 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 901 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 13 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.088790 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 1004.384615 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 2337865 # number of writebacks
-system.cpu.dcache.writebacks::total 2337865 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 792851 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 792851 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 5950 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 5950 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 798801 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 798801 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 798801 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 798801 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765879 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1765879 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 785364 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 785364 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 2551243 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 2551243 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 2551243 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 2551243 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37626062000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 37626062000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25475564000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 25475564000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 63101626000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 63101626000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 63101626000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 63101626000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006421 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006421 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005265 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005265 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.006015 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006015 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.006015 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21307.270770 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21307.270770 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32437.906499 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32437.906499 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24733.679230 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24733.679230 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 3942 # number of replacements
-system.cpu.icache.tags.tagsinuse 1083.391017 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 216536709 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 5668 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 38203.371383 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 1083.391017 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.529000 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.529000 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 1726 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 80 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.842773 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 433100363 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 433100363 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 216536917 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 216536917 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 216536917 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 216536917 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 216536917 # number of overall hits
-system.cpu.icache.overall_hits::total 216536917 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 9643 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 9643 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 9643 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 9643 # number of demand (read+write) misses
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 134013.917315 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84674.098673 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84984.973023 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 5107999 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2549734 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 19983 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 3565 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3558 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 1772876 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 2633356 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 3942 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::CleanEvict 268356 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 1576 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 1576 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 784034 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 784034 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 7243 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765633 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16775 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7648057 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 7664832 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 610048 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312802048 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 313412096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 357794 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 19017216 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 2914627 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.008154 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.089959 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 2890867 99.18% 99.18% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 23753 0.81% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 2914627 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4895855901 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 10867494 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3825288599 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 740964 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 353722 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 180910 # Transaction distribution
-system.membus.trans_dist::WritebackDirty 295491 # Transaction distribution
-system.membus.trans_dist::CleanEvict 57731 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206823 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206823 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 180910 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128697 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128697 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1128697 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43726336 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43726336 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 43726336 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 387742 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 387742 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 387742 # Request fanout histogram
-system.membus.reqLayer0.occupancy 1998138500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.4 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2051606500 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
+sim_seconds 0.487051
+sim_ticks 487050729500
+final_tick 487050729500
+sim_freq 1000000000000
+host_inst_rate 109718
+host_op_rate 203033
+host_tick_rate 64628655
+host_mem_usage 330116
+host_seconds 7536.14
+sim_insts 826847303
+sim_ops 1530082520
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 487050729500
+system.physmem.bytes_read::cpu.inst 156352
+system.physmem.bytes_read::cpu.data 24658560
+system.physmem.bytes_read::total 24814912
+system.physmem.bytes_inst_read::cpu.inst 156352
+system.physmem.bytes_inst_read::total 156352
+system.physmem.bytes_written::writebacks 18911424
+system.physmem.bytes_written::total 18911424
+system.physmem.num_reads::cpu.inst 2443
+system.physmem.num_reads::cpu.data 385290
+system.physmem.num_reads::total 387733
+system.physmem.num_writes::writebacks 295491
+system.physmem.num_writes::total 295491
+system.physmem.bw_read::cpu.inst 321018
+system.physmem.bw_read::cpu.data 50628320
+system.physmem.bw_read::total 50949338
+system.physmem.bw_inst_read::cpu.inst 321018
+system.physmem.bw_inst_read::total 321018
+system.physmem.bw_write::writebacks 38828448
+system.physmem.bw_write::total 38828448
+system.physmem.bw_total::writebacks 38828448
+system.physmem.bw_total::cpu.inst 321018
+system.physmem.bw_total::cpu.data 50628320
+system.physmem.bw_total::total 89777786
+system.physmem.readReqs 387733
+system.physmem.writeReqs 295491
+system.physmem.readBursts 387733
+system.physmem.writeBursts 295491
+system.physmem.bytesReadDRAM 24795072
+system.physmem.bytesReadWrQ 19840
+system.physmem.bytesWritten 18909504
+system.physmem.bytesReadSys 24814912
+system.physmem.bytesWrittenSys 18911424
+system.physmem.servicedByWrQ 310
+system.physmem.mergedWrBursts 0
+system.physmem.neitherReadNorWriteReqs 0
+system.physmem.perBankRdBursts::0 24612
+system.physmem.perBankRdBursts::1 26389
+system.physmem.perBankRdBursts::2 24828
+system.physmem.perBankRdBursts::3 24571
+system.physmem.perBankRdBursts::4 23534
+system.physmem.perBankRdBursts::5 23661
+system.physmem.perBankRdBursts::6 24754
+system.physmem.perBankRdBursts::7 24509
+system.physmem.perBankRdBursts::8 23888
+system.physmem.perBankRdBursts::9 23557
+system.physmem.perBankRdBursts::10 24834
+system.physmem.perBankRdBursts::11 24002
+system.physmem.perBankRdBursts::12 23243
+system.physmem.perBankRdBursts::13 22894
+system.physmem.perBankRdBursts::14 23905
+system.physmem.perBankRdBursts::15 24242
+system.physmem.perBankWrBursts::0 18972
+system.physmem.perBankWrBursts::1 19954
+system.physmem.perBankWrBursts::2 19038
+system.physmem.perBankWrBursts::3 19006
+system.physmem.perBankWrBursts::4 18208
+system.physmem.perBankWrBursts::5 18444
+system.physmem.perBankWrBursts::6 19174
+system.physmem.perBankWrBursts::7 19116
+system.physmem.perBankWrBursts::8 18744
+system.physmem.perBankWrBursts::9 17955
+system.physmem.perBankWrBursts::10 18923
+system.physmem.perBankWrBursts::11 17774
+system.physmem.perBankWrBursts::12 17399
+system.physmem.perBankWrBursts::13 16985
+system.physmem.perBankWrBursts::14 17804
+system.physmem.perBankWrBursts::15 17965
+system.physmem.numRdRetry 0
+system.physmem.numWrRetry 0
+system.physmem.totGap 487050613500
+system.physmem.readPktSize::0 0
+system.physmem.readPktSize::1 0
+system.physmem.readPktSize::2 0
+system.physmem.readPktSize::3 0
+system.physmem.readPktSize::4 0
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+system.physmem.readPktSize::6 387733
+system.physmem.writePktSize::0 0
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+system.physmem.writePktSize::3 0
+system.physmem.writePktSize::4 0
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+system.physmem.writePktSize::6 295491
+system.physmem.rdQLenPdf::0 381263
+system.physmem.rdQLenPdf::1 5754
+system.physmem.rdQLenPdf::2 361
+system.physmem.rdQLenPdf::3 34
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+system.physmem.wrQLenPdf::15 6088
+system.physmem.wrQLenPdf::16 6353
+system.physmem.wrQLenPdf::17 17482
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+system.physmem.wrQLenPdf::19 17684
+system.physmem.wrQLenPdf::20 17682
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+system.physmem.wrQLenPdf::22 17686
+system.physmem.wrQLenPdf::23 17693
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+system.physmem.wrQLenPdf::29 17729
+system.physmem.wrQLenPdf::30 17821
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+system.physmem.wrQLenPdf::63 0
+system.physmem.bytesPerActivate::samples 146416
+system.physmem.bytesPerActivate::mean 298.484100
+system.physmem.bytesPerActivate::gmean 176.719176
+system.physmem.bytesPerActivate::stdev 324.748192
+system.physmem.bytesPerActivate::0-127 52816 36.07% 36.07%
+system.physmem.bytesPerActivate::128-255 41066 28.05% 64.12%
+system.physmem.bytesPerActivate::256-383 13865 9.47% 73.59%
+system.physmem.bytesPerActivate::384-511 7498 5.12% 78.71%
+system.physmem.bytesPerActivate::512-639 4985 3.40% 82.12%
+system.physmem.bytesPerActivate::640-767 3806 2.60% 84.71%
+system.physmem.bytesPerActivate::768-895 2894 1.98% 86.69%
+system.physmem.bytesPerActivate::896-1023 2818 1.92% 88.62%
+system.physmem.bytesPerActivate::1024-1151 16668 11.38% 100.00%
+system.physmem.bytesPerActivate::total 146416
+system.physmem.rdPerTurnAround::samples 17678
+system.physmem.rdPerTurnAround::mean 21.914866
+system.physmem.rdPerTurnAround::gmean 18.161180
+system.physmem.rdPerTurnAround::stdev 216.039339
+system.physmem.rdPerTurnAround::0-1023 17672 99.97% 99.97%
+system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.97%
+system.physmem.rdPerTurnAround::2048-3071 1 0.01% 99.98%
+system.physmem.rdPerTurnAround::3072-4095 2 0.01% 99.99%
+system.physmem.rdPerTurnAround::8192-9215 1 0.01% 99.99%
+system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00%
+system.physmem.rdPerTurnAround::total 17678
+system.physmem.wrPerTurnAround::samples 17678
+system.physmem.wrPerTurnAround::mean 16.713486
+system.physmem.wrPerTurnAround::gmean 16.686282
+system.physmem.wrPerTurnAround::stdev 0.965426
+system.physmem.wrPerTurnAround::16 11315 64.01% 64.01%
+system.physmem.wrPerTurnAround::17 269 1.52% 65.53%
+system.physmem.wrPerTurnAround::18 5957 33.70% 99.23%
+system.physmem.wrPerTurnAround::19 123 0.70% 99.92%
+system.physmem.wrPerTurnAround::20 10 0.06% 99.98%
+system.physmem.wrPerTurnAround::21 3 0.02% 99.99%
+system.physmem.wrPerTurnAround::22 1 0.01% 100.00%
+system.physmem.wrPerTurnAround::total 17678
+system.physmem.totQLat 9794922250
+system.physmem.totMemAccLat 17059103500
+system.physmem.totBusLat 1937115000
+system.physmem.avgQLat 25282.24
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 44032.24
+system.physmem.avgRdBW 50.91
+system.physmem.avgWrBW 38.82
+system.physmem.avgRdBWSys 50.95
+system.physmem.avgWrBWSys 38.83
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.70
+system.physmem.busUtilRead 0.40
+system.physmem.busUtilWrite 0.30
+system.physmem.avgRdQLen 1.04
+system.physmem.avgWrQLen 20.96
+system.physmem.readRowHits 316322
+system.physmem.writeRowHits 220133
+system.physmem.readRowHitRate 81.65
+system.physmem.writeRowHitRate 74.50
+system.physmem.avgGap 712871.05
+system.physmem.pageHitRate 78.55
+system.physmem_0.actEnergy 538191780
+system.physmem_0.preEnergy 286032945
+system.physmem_0.readEnergy 1405566120
+system.physmem_0.writeEnergy 792980640
+system.physmem_0.refreshEnergy 13571251200.000004
+system.physmem_0.actBackEnergy 8851881120
+system.physmem_0.preBackEnergy 742850400
+system.physmem_0.actPowerDownEnergy 36305173020
+system.physmem_0.prePowerDownEnergy 16998972000
+system.physmem_0.selfRefreshEnergy 84070895340
+system.physmem_0.totalEnergy 163568832135
+system.physmem_0.averagePower 335.835307
+system.physmem_0.totalIdleTime 465691902250
+system.physmem_0.memoryStateTime::IDLE 1184996500
+system.physmem_0.memoryStateTime::REF 5763492000
+system.physmem_0.memoryStateTime::SREF 341808238000
+system.physmem_0.memoryStateTime::PRE_PDN 44268234250
+system.physmem_0.memoryStateTime::ACT 14409717250
+system.physmem_0.memoryStateTime::ACT_PDN 79616051500
+system.physmem_1.actEnergy 507311280
+system.physmem_1.preEnergy 269615775
+system.physmem_1.readEnergy 1360634100
+system.physmem_1.writeEnergy 749325780
+system.physmem_1.refreshEnergy 13094905200.000004
+system.physmem_1.actBackEnergy 8819547870
+system.physmem_1.preBackEnergy 717418080
+system.physmem_1.actPowerDownEnergy 34208424030
+system.physmem_1.prePowerDownEnergy 16648938720
+system.physmem_1.selfRefreshEnergy 85396744800
+system.physmem_1.totalEnergy 161777173725
+system.physmem_1.averagePower 332.156722
+system.physmem_1.totalIdleTime 465831856000
+system.physmem_1.memoryStateTime::IDLE 1145526000
+system.physmem_1.memoryStateTime::REF 5561926000
+system.physmem_1.memoryStateTime::SREF 347456670000
+system.physmem_1.memoryStateTime::PRE_PDN 43356567250
+system.physmem_1.memoryStateTime::ACT 14511269750
+system.physmem_1.memoryStateTime::ACT_PDN 75018770500
+system.pwrStateResidencyTicks::UNDEFINED 487050729500
+system.cpu.branchPred.lookups 299198029
+system.cpu.branchPred.condPredicted 299198029
+system.cpu.branchPred.condIncorrect 24258277
+system.cpu.branchPred.BTBLookups 226066805
+system.cpu.branchPred.BTBHits 0
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 0.000000
+system.cpu.branchPred.usedRAS 40193400
+system.cpu.branchPred.RASInCorrect 4437789
+system.cpu.branchPred.indirectLookups 226066805
+system.cpu.branchPred.indirectHits 118144411
+system.cpu.branchPred.indirectMisses 107922394
+system.cpu.branchPredindirectMispredicted 11883156
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500
+system.cpu.apic_clk_domain.clock 8000
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 487050729500
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 487050729500
+system.cpu.workload.numSyscalls 551
+system.cpu.pwrStateResidencyTicks::ON 487050729500
+system.cpu.numCycles 974101460
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.fetch.icacheStallCycles 230169557
+system.cpu.fetch.Insts 1594277830
+system.cpu.fetch.Branches 299198029
+system.cpu.fetch.predictedBranches 158337811
+system.cpu.fetch.Cycles 718471067
+system.cpu.fetch.SquashCycles 49469998
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+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 487050729500
+system.cpu.toL2Bus.trans_dist::ReadResp 1772876
+system.cpu.toL2Bus.trans_dist::WritebackDirty 2633356
+system.cpu.toL2Bus.trans_dist::WritebackClean 3942
+system.cpu.toL2Bus.trans_dist::CleanEvict 268356
+system.cpu.toL2Bus.trans_dist::UpgradeReq 1576
+system.cpu.toL2Bus.trans_dist::UpgradeResp 1576
+system.cpu.toL2Bus.trans_dist::ReadExReq 784034
+system.cpu.toL2Bus.trans_dist::ReadExResp 784034
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 7243
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1765633
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16775
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7648057
+system.cpu.toL2Bus.pkt_count::total 7664832
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 610048
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312802048
+system.cpu.toL2Bus.pkt_size::total 313412096
+system.cpu.toL2Bus.snoops 357794
+system.cpu.toL2Bus.snoopTraffic 19017216
+system.cpu.toL2Bus.snoop_fanout::samples 2914627
+system.cpu.toL2Bus.snoop_fanout::mean 0.008154
+system.cpu.toL2Bus.snoop_fanout::stdev 0.089959
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 2890867 99.18% 99.18%
+system.cpu.toL2Bus.snoop_fanout::1 23753 0.81% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 2914627
+system.cpu.toL2Bus.reqLayer0.occupancy 4895855901
+system.cpu.toL2Bus.reqLayer0.utilization 1.0
+system.cpu.toL2Bus.respLayer0.occupancy 10867494
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 3825288599
+system.cpu.toL2Bus.respLayer1.utilization 0.8
+system.membus.snoop_filter.tot_requests 740964
+system.membus.snoop_filter.hit_single_requests 353722
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 487050729500
+system.membus.trans_dist::ReadResp 180910
+system.membus.trans_dist::WritebackDirty 295491
+system.membus.trans_dist::CleanEvict 57731
+system.membus.trans_dist::UpgradeReq 9
+system.membus.trans_dist::ReadExReq 206823
+system.membus.trans_dist::ReadExResp 206823
+system.membus.trans_dist::ReadSharedReq 180910
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1128697
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1128697
+system.membus.pkt_count::total 1128697
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43726336
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43726336
+system.membus.pkt_size::total 43726336
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 387742
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 387742 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 387742
+system.membus.reqLayer0.occupancy 1998138500
+system.membus.reqLayer0.utilization 0.4
+system.membus.respLayer1.occupancy 2051606500
+system.membus.respLayer1.utilization 0.4
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index 4c9b068a2..dd85c448b 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
@@ -88,6 +89,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -167,7 +169,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=parser 2.1.dict -batch
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
drivers=
@@ -176,14 +178,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=114600000000
system=system
uid=100
@@ -207,6 +210,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -218,7 +222,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -226,6 +230,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -234,6 +245,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -241,7 +253,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
index aadc3d011..43d70058a 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
index 3a0d1b2f1..227ee869b 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
@@ -3,16 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:19
-gem5 executing on e108600-lin, pid 18563
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:06:22
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87200
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
- Reading the dictionary files: *****************************info: Increasing stack size by one page.
-********************
+ Reading the dictionary files: *************************************************
58924 words stored in 3784810 bytes
@@ -26,8 +24,6 @@ Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -72,4 +68,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 885772926000 because target called exit()
+Exiting @ tick 885772926000 because exiting with last active thread context
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
index 0b4609b35..5fc9dc6b8 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
@@ -1,145 +1,145 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.885773 # Number of seconds simulated
-sim_ticks 885772926000 # Number of ticks simulated
-final_tick 885772926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1551014 # Simulator instruction rate (inst/s)
-host_op_rate 2870153 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1661547121 # Simulator tick rate (ticks/s)
-host_mem_usage 272636 # Number of bytes of host memory used
-host_seconds 533.10 # Real time elapsed on the host
-sim_insts 826847304 # Number of instructions simulated
-sim_ops 1530082521 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 8546485088 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 2285527276 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10832012364 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 8546485088 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 8546485088 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 991837474 # Number of bytes written to this memory
-system.physmem.bytes_written::total 991837474 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1068310636 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 384083342 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1452393978 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 149158211 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149158211 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 9648618554 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2580263190 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 12228881744 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 9648618554 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 9648618554 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1119742368 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1119742368 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 9648618554 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3700005559 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13348624112 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 551 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 885772926000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1771545853 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 826847304 # Number of instructions committed
-system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 35346287 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1527470226 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
-system.cpu.num_mem_refs 533241508 # number of memory refs
-system.cpu.num_load_insts 384083313 # Number of load instructions
-system.cpu.num_store_insts 149158195 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 1771545852.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 149981740 # Number of branches fetched
-system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
-system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
-system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
-system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
-system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1530082521 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 1452393978 # Transaction distribution
-system.membus.trans_dist::ReadResp 1452393978 # Transaction distribution
-system.membus.trans_dist::WriteReq 149158211 # Transaction distribution
-system.membus.trans_dist::WriteResp 149158211 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 2136621272 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 1066483106 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 3203104378 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 8546485088 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 3277364750 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 11823849838 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1601552189 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1601552189 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 1601552189 # Request fanout histogram
+sim_seconds 0.885773
+sim_ticks 885772926000
+final_tick 885772926000
+sim_freq 1000000000000
+host_inst_rate 728826
+host_op_rate 1348694
+host_tick_rate 780766307
+host_mem_usage 284536
+host_seconds 1134.49
+sim_insts 826847304
+sim_ops 1530082521
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 885772926000
+system.physmem.bytes_read::cpu.inst 8546485088
+system.physmem.bytes_read::cpu.data 2285527276
+system.physmem.bytes_read::total 10832012364
+system.physmem.bytes_inst_read::cpu.inst 8546485088
+system.physmem.bytes_inst_read::total 8546485088
+system.physmem.bytes_written::cpu.data 991837474
+system.physmem.bytes_written::total 991837474
+system.physmem.num_reads::cpu.inst 1068310636
+system.physmem.num_reads::cpu.data 384083342
+system.physmem.num_reads::total 1452393978
+system.physmem.num_writes::cpu.data 149158211
+system.physmem.num_writes::total 149158211
+system.physmem.bw_read::cpu.inst 9648618554
+system.physmem.bw_read::cpu.data 2580263190
+system.physmem.bw_read::total 12228881744
+system.physmem.bw_inst_read::cpu.inst 9648618554
+system.physmem.bw_inst_read::total 9648618554
+system.physmem.bw_write::cpu.data 1119742368
+system.physmem.bw_write::total 1119742368
+system.physmem.bw_total::cpu.inst 9648618554
+system.physmem.bw_total::cpu.data 3700005559
+system.physmem.bw_total::total 13348624112
+system.pwrStateResidencyTicks::UNDEFINED 885772926000
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000
+system.cpu.apic_clk_domain.clock 8000
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 885772926000
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 885772926000
+system.cpu.workload.numSyscalls 551
+system.cpu.pwrStateResidencyTicks::ON 885772926000
+system.cpu.numCycles 1771545853
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 826847304
+system.cpu.committedOps 1530082521
+system.cpu.num_int_alu_accesses 1527470226
+system.cpu.num_fp_alu_accesses 0
+system.cpu.num_func_calls 35346287
+system.cpu.num_conditional_control_insts 92881952
+system.cpu.num_int_insts 1527470226
+system.cpu.num_fp_insts 0
+system.cpu.num_int_register_reads 3298246119
+system.cpu.num_int_register_writes 1240060586
+system.cpu.num_fp_register_reads 0
+system.cpu.num_fp_register_writes 0
+system.cpu.num_cc_register_reads 562449682
+system.cpu.num_cc_register_writes 376900986
+system.cpu.num_mem_refs 533241508
+system.cpu.num_load_insts 384083313
+system.cpu.num_store_insts 149158195
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 1771545853
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 149981740
+system.cpu.op_class::No_OpClass 2048202 0.13% 0.13%
+system.cpu.op_class::IntAlu 989691029 64.68% 64.82%
+system.cpu.op_class::IntMult 306834 0.02% 64.84%
+system.cpu.op_class::IntDiv 4794948 0.31% 65.15%
+system.cpu.op_class::FloatAdd 0 0.00% 65.15%
+system.cpu.op_class::FloatCmp 0 0.00% 65.15%
+system.cpu.op_class::FloatCvt 0 0.00% 65.15%
+system.cpu.op_class::FloatMult 0 0.00% 65.15%
+system.cpu.op_class::FloatMultAcc 0 0.00% 65.15%
+system.cpu.op_class::FloatDiv 0 0.00% 65.15%
+system.cpu.op_class::FloatMisc 0 0.00% 65.15%
+system.cpu.op_class::FloatSqrt 0 0.00% 65.15%
+system.cpu.op_class::SimdAdd 0 0.00% 65.15%
+system.cpu.op_class::SimdAddAcc 0 0.00% 65.15%
+system.cpu.op_class::SimdAlu 0 0.00% 65.15%
+system.cpu.op_class::SimdCmp 0 0.00% 65.15%
+system.cpu.op_class::SimdCvt 0 0.00% 65.15%
+system.cpu.op_class::SimdMisc 0 0.00% 65.15%
+system.cpu.op_class::SimdMult 0 0.00% 65.15%
+system.cpu.op_class::SimdMultAcc 0 0.00% 65.15%
+system.cpu.op_class::SimdShift 0 0.00% 65.15%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15%
+system.cpu.op_class::SimdSqrt 0 0.00% 65.15%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 65.15%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15%
+system.cpu.op_class::SimdFloatMult 0 0.00% 65.15%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15%
+system.cpu.op_class::MemRead 384083313 25.10% 90.25%
+system.cpu.op_class::MemWrite 149158195 9.75% 100.00%
+system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
+system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 1530082521
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 885772926000
+system.membus.trans_dist::ReadReq 1452393978
+system.membus.trans_dist::ReadResp 1452393978
+system.membus.trans_dist::WriteReq 149158211
+system.membus.trans_dist::WriteResp 149158211
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136621272
+system.membus.pkt_count_system.cpu.icache_port::total 2136621272
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066483106
+system.membus.pkt_count_system.cpu.dcache_port::total 1066483106
+system.membus.pkt_count::total 3203104378
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546485088
+system.membus.pkt_size_system.cpu.icache_port::total 8546485088
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277364750
+system.membus.pkt_size_system.cpu.dcache_port::total 3277364750
+system.membus.pkt_size::total 11823849838
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1601552189
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1601552189 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1601552189
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index d62d690f2..6ea332421 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -85,6 +86,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -100,14 +102,14 @@ eventq_index=0
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -121,6 +123,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -133,15 +136,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -187,6 +191,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -199,15 +204,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -274,6 +280,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -286,15 +293,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -330,7 +338,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=parser 2.1.dict -batch
cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
drivers=
@@ -339,14 +347,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/parser
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/arm/projectscratch/randd/systems/dist/cpu2000/data/parser/mdred/input/parser.in
+input=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=114600000000
system=system
uid=100
@@ -370,6 +379,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -381,7 +391,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -389,6 +399,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -397,6 +414,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -404,7 +422,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
index aadc3d011..43d70058a 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index e0c4a0b01..5231f3e17 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -3,16 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:17
-gem5 executing on e108600-lin, pid 18541
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:06:22
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87196
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
- Reading the dictionary files: *****************************info: Increasing stack size by one page.
-********************
+ Reading the dictionary files: *************************************************
58924 words stored in 3784810 bytes
@@ -26,8 +24,6 @@ Echoing of input sentence turned on.
* as had expected the party to be a success , it was a success
* do you know where John 's
* he said that , finding that it was impossible to get work as a waiter , he would work as a janitor
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
* how fast the program is it
* I am wondering whether to invite to the party
* I gave him for his birthday it
@@ -72,4 +68,4 @@ info: Increasing stack size by one page.
about 2 million people attended
the five best costumes got prizes
No errors!
-Exiting @ tick 1650501252500 because target called exit()
+Exiting @ tick 1650923912500 because exiting with last active thread context
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
index bbca4e86c..48f9b108e 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
@@ -1,546 +1,546 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.650924 # Number of seconds simulated
-sim_ticks 1650923912500 # Number of ticks simulated
-final_tick 1650923912500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1073233 # Simulator instruction rate (inst/s)
-host_op_rate 1986019 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2142868820 # Simulator tick rate (ticks/s)
-host_mem_usage 285448 # Number of bytes of host memory used
-host_seconds 770.43 # Real time elapsed on the host
-sim_insts 826847304 # Number of instructions simulated
-sim_ops 1530082521 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 115968 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 24312256 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24428224 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 115968 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 115968 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18812864 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18812864 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1812 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 379879 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 381691 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 293951 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 293951 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 70244 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 14726455 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 14796699 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 70244 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 70244 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 11395355 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 11395355 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 11395355 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 70244 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 14726455 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 26192054 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 551 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 1650923912500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 3301847825 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 826847304 # Number of instructions committed
-system.cpu.committedOps 1530082521 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1527470226 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 35346287 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 92881952 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1527470226 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 3298246119 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1240060586 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 562449682 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 376900986 # number of times the CC registers were written
-system.cpu.num_mem_refs 533241508 # number of memory refs
-system.cpu.num_load_insts 384083313 # Number of load instructions
-system.cpu.num_store_insts 149158195 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 3301847824.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 149981740 # Number of branches fetched
-system.cpu.op_class::No_OpClass 2048202 0.13% 0.13% # Class of executed instruction
-system.cpu.op_class::IntAlu 989691029 64.68% 64.82% # Class of executed instruction
-system.cpu.op_class::IntMult 306834 0.02% 64.84% # Class of executed instruction
-system.cpu.op_class::IntDiv 4794948 0.31% 65.15% # Class of executed instruction
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-system.cpu.op_class::FloatCmp 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 65.15% # Class of executed instruction
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-system.cpu.op_class::SimdAddAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 65.15% # Class of executed instruction
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-system.cpu.op_class::SimdMultAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 65.15% # Class of executed instruction
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-system.cpu.op_class::SimdFloatMisc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.15% # Class of executed instruction
-system.cpu.op_class::MemRead 384083313 25.10% 90.25% # Class of executed instruction
-system.cpu.op_class::MemWrite 149158195 9.75% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1530082521 # Class of executed instruction
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-system.cpu.dcache.tags.tagsinuse 4086.382570 # Cycle average of tags in use
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-system.cpu.dcache.tags.sampled_refs 2521112 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 210.510458 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 8250925500 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id
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-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1069004218 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1069004218 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1650923912500 # Cumulative time (in ticks) in various power states
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-system.cpu.dcache.ReadReq_hits::total 382353600 # number of ReadReq hits
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-system.cpu.dcache.WriteReq_hits::total 148366841 # number of WriteReq hits
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-system.cpu.dcache.overall_hits::total 530720441 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 1729742 # number of ReadReq misses
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-system.cpu.dcache.WriteReq_misses::total 791370 # number of WriteReq misses
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-system.cpu.dcache.demand_misses::total 2521112 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 2521112 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 31154171500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 31154171500 # number of ReadReq miss cycles
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-system.cpu.dcache.ReadReq_accesses::total 384083342 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_accesses::total 149158211 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 18010.877634 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26048.831141 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 26048.831141 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 20533.968741 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 20533.968741 # average overall miss latency
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-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25048.831141 # average WriteReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 19533.968741 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19533.968741 # average overall mshr miss latency
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-system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id
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-system.cpu.icache.overall_misses::total 2814 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 127237000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 127237000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 127237000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 127237000 # number of overall miss cycles
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-system.cpu.icache.demand_avg_miss_latency::total 45215.707178 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 45215.707178 # average overall miss latency
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 44215.707178 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 44215.707178 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 44215.707178 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 44215.707178 # average overall mshr miss latency
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.475071 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 30276.892760 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 346 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 32344 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.l2cache.tags.data_accesses 40719748 # Number of data accesses
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-system.cpu.l2cache.WritebackDirty_hits::total 2324919 # number of WritebackDirty hits
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-system.cpu.l2cache.WritebackClean_hits::total 1253 # number of WritebackClean hits
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+system.cpu.l2cache.CleanEvict_mshr_misses::total 6
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206529
+system.cpu.l2cache.ReadExReq_mshr_misses::total 206529
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1812
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1812
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 173350
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 173350
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1812
+system.cpu.l2cache.demand_mshr_misses::cpu.data 379879
+system.cpu.l2cache.demand_mshr_misses::total 381691
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1812
+system.cpu.l2cache.overall_mshr_misses::cpu.data 379879
+system.cpu.l2cache.overall_mshr_misses::total 381691
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10429718000
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10429718000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 91549500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 91549500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8754197500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8754197500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 91549500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19183915500
+system.cpu.l2cache.demand_mshr_miss_latency::total 19275465000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 91549500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19183915500
+system.cpu.l2cache.overall_mshr_miss_latency::total 19275465000
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf
+system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.260977
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.260977
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.643923
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.643923
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.100217
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.100217
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.643923
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.150679
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.151229
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.643923
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150679
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.151229
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.016947
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.016947
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.006623
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.006623
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500.129795
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500.129795
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.006623
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500.068443
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.182084
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.006623
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500.068443
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.182084
+system.cpu.toL2Bus.snoop_filter.tot_requests 5042195
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2518269
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0
+system.cpu.toL2Bus.snoop_filter.tot_snoops 1866
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1866
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1650923912500
+system.cpu.toL2Bus.trans_dist::ReadResp 1732556
+system.cpu.toL2Bus.trans_dist::WritebackDirty 2618871
+system.cpu.toL2Bus.trans_dist::WritebackClean 1253
+system.cpu.toL2Bus.trans_dist::CleanEvict 247565
+system.cpu.toL2Bus.trans_dist::ReadExReq 791370
+system.cpu.toL2Bus.trans_dist::ReadExResp 791370
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 2814
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1729742
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6881
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7559240
+system.cpu.toL2Bus.pkt_count::total 7566121
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 260288
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 310145984
+system.cpu.toL2Bus.pkt_size::total 310406272
+system.cpu.toL2Bus.snoops 349420
+system.cpu.toL2Bus.snoopTraffic 18812928
+system.cpu.toL2Bus.snoop_fanout::samples 2873346
+system.cpu.toL2Bus.snoop_fanout::mean 0.000649
+system.cpu.toL2Bus.snoop_fanout::stdev 0.025475
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 2871480 99.94% 99.94%
+system.cpu.toL2Bus.snoop_fanout::1 1866 0.06% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 2873346
+system.cpu.toL2Bus.reqLayer0.occupancy 4847269500
+system.cpu.toL2Bus.reqLayer0.utilization 0.3
+system.cpu.toL2Bus.respLayer0.occupancy 4221000
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 3781668000
+system.cpu.toL2Bus.respLayer1.utilization 0.2
+system.membus.snoop_filter.tot_requests 729250
+system.membus.snoop_filter.hit_single_requests 347559
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 1650923912500
+system.membus.trans_dist::ReadResp 175162
+system.membus.trans_dist::WritebackDirty 293951
+system.membus.trans_dist::CleanEvict 53608
+system.membus.trans_dist::ReadExReq 206529
+system.membus.trans_dist::ReadExResp 206529
+system.membus.trans_dist::ReadSharedReq 175162
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1110941
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1110941
+system.membus.pkt_count::total 1110941
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43241088
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43241088
+system.membus.pkt_size::total 43241088
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 381691
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 381691 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 381691
+system.membus.reqLayer0.occupancy 1905079500
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 1908455000
+system.membus.respLayer1.utilization 0.1
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index 3870e90de..2c21341f7 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
index 3415c9346..2f8aeb16c 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
@@ -1,11 +1,14 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
+info: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
@@ -32,6 +35,8 @@ col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
0 8 14
1 8 14
2 8 14
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index 5ac8e5d82..2e95c35f3 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -3,17 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:51:10
-gem5 executing on e108600-lin, pid 17461
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 18:05:52
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 55337
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
Eon, Version 1.1
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
OO-style eon Time= 0.120000
-Exiting @ tick 122177531500 because target called exit()
+Exiting @ tick 124340889500 because exiting with last active thread context
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
index be47c4345..f1f3dd777 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
@@ -1,1241 +1,1241 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.124341 # Number of seconds simulated
-sim_ticks 124340889500 # Number of ticks simulated
-final_tick 124340889500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 229813 # Simulator instruction rate (inst/s)
-host_op_rate 275917 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 104656772 # Simulator tick rate (ticks/s)
-host_mem_usage 292960 # Number of bytes of host memory used
-host_seconds 1188.08 # Real time elapsed on the host
-sim_insts 273037218 # Number of instructions simulated
-sim_ops 327811600 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 1894400 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 14645312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 169216 # Number of bytes read from this memory
-system.physmem.bytes_read::total 16708928 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1894400 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 29600 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 228833 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 2644 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 261077 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 15235535 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 117783555 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 1360904 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 134379994 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 15235535 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 15235535 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 15235535 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 117783555 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 1360904 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 134379994 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 261078 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 261078 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 16708992 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 16708992 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 1259 # Per bank write bursts
-system.physmem.perBankRdBursts::1 69989 # Per bank write bursts
-system.physmem.perBankRdBursts::2 1294 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10805 # Per bank write bursts
-system.physmem.perBankRdBursts::4 42847 # Per bank write bursts
-system.physmem.perBankRdBursts::5 121814 # Per bank write bursts
-system.physmem.perBankRdBursts::6 160 # Per bank write bursts
-system.physmem.perBankRdBursts::7 259 # Per bank write bursts
-system.physmem.perBankRdBursts::8 225 # Per bank write bursts
-system.physmem.perBankRdBursts::9 562 # Per bank write bursts
-system.physmem.perBankRdBursts::10 7823 # Per bank write bursts
-system.physmem.perBankRdBursts::11 812 # Per bank write bursts
-system.physmem.perBankRdBursts::12 1216 # Per bank write bursts
-system.physmem.perBankRdBursts::13 747 # Per bank write bursts
-system.physmem.perBankRdBursts::14 656 # Per bank write bursts
-system.physmem.perBankRdBursts::15 610 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 124340880000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 261078 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 204158 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 43358 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 12121 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 308 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 247 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 209 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 181 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 231 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 123 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 61 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 20 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 17 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 17 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 67983 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 245.745201 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 180.705876 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 200.483366 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 18259 26.86% 26.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 22263 32.75% 59.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 11383 16.74% 76.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 6868 10.10% 86.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 4760 7.00% 93.45% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 2080 3.06% 96.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1310 1.93% 98.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 394 0.58% 99.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 666 0.98% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 67983 # Bytes accessed per row activation
-system.physmem.totQLat 4612072505 # Total ticks spent queuing
-system.physmem.totMemAccLat 9507285005 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1305390000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 17665.50 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 36415.50 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 134.38 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 134.38 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 1.05 # Data bus utilization in percentage
-system.physmem.busUtilRead 1.05 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.60 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 193085 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 73.96 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 476259.51 # Average gap between requests
-system.physmem.pageHitRate 73.96 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 450291240 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 239324085 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1773768780 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 9681809280.000002 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 4644193560 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 227236800 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 45907805700 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 3604922400 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 978458700 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 67507810545 # Total energy per rank (pJ)
-system.physmem_0.averagePower 542.925264 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 113563299646 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 155533000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 4097020000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 3501663750 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 9387944632 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 6524904104 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 100673824014 # Time in different power states
-system.physmem_1.actEnergy 35171640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 18667605 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 90321000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3119298000.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 731861760 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 127236960 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 10304428080 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 3803073120 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 21964091670 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 40194673995 # Total energy per rank (pJ)
-system.physmem_1.averagePower 323.261913 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 122403387505 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 207240000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1323736000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 89902145500 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 9903979079 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 406525995 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 22597262926 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 36038003 # Number of BP lookups
-system.cpu.branchPred.condPredicted 19334387 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 996297 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 17830996 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13933502 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 78.142029 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 6950609 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 4465 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 2515874 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 2470358 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 45516 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 129389 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 191 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 124340889500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 248681780 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 13212448 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 309769989 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 36038003 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 23354469 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 231113604 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 2018885 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 1934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 92 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 3406 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 82291256 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 35072 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 245340926 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.517468 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.300338 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 84879866 34.60% 34.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 40535888 16.52% 51.12% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 28014472 11.42% 62.54% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 91910700 37.46% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 245340926 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.144916 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.245648 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 27542743 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 94606230 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 97234991 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 25081957 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 875005 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 12946400 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 134756 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 348426325 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3406644 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 875005 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 44284460 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 38724844 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 289442 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 104535895 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 56631280 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 344535849 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 1483850 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 7863336 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 96546 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 8390481 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 28393613 # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents 3430855 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 394784790 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 2217316444 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 335868704 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 192847846 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 372230048 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 22554742 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 11609 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 11576 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 59430212 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 89918066 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 84391902 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2366315 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1969070 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 343213178 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 22626 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 339325700 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 951900 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 15424204 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 36793818 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 506 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 245340926 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.383078 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.139070 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 64299867 26.21% 26.21% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 77319752 31.52% 57.72% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 59651654 24.31% 82.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 34378652 14.01% 96.05% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 8900677 3.63% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 777968 0.32% 99.99% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 12356 0.01% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 245340926 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 8768859 6.80% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 7313 0.01% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 162373 0.13% 6.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.93% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 163818 0.13% 7.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 81957 0.06% 7.12% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 59658 0.05% 7.17% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 818593 0.63% 7.80% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 313085 0.24% 8.04% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 382100 0.30% 8.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 27482783 21.31% 29.65% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 41323323 32.04% 61.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 30643180 23.76% 85.44% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 18783688 14.56% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 108181018 31.88% 31.88% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 2148109 0.63% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 6799471 2.00% 34.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.52% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 8597209 2.53% 37.05% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 3207374 0.95% 38.00% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 1592649 0.47% 38.47% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 20858202 6.15% 44.61% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 7175067 2.11% 46.73% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 7140627 2.10% 48.83% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 175298 0.05% 48.88% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 46505269 13.71% 62.59% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 55942906 16.49% 79.08% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 43451689 12.81% 91.88% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 27550812 8.12% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 339325700 # Type of FU issued
-system.cpu.iq.rate 1.364498 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 128990730 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.380138 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 765966009 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 235211704 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 219112487 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 287968947 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 123463225 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 116939299 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 298793937 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 169522493 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 5585313 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4185791 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 7155 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 14925 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 2016285 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 158671 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 539433 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 875005 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 1351770 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1745589 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 343237205 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 89918066 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 84391902 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 11593 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 6365 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1739416 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 14925 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 447604 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 457294 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 904898 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 337307001 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 89393919 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2018699 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 1401 # number of nop insts executed
-system.cpu.iew.exec_refs 172494904 # number of memory reference insts executed
-system.cpu.iew.exec_branches 31547244 # Number of branches executed
-system.cpu.iew.exec_stores 83100985 # Number of stores executed
-system.cpu.iew.exec_rate 1.356380 # Inst execution rate
-system.cpu.iew.wb_sent 336195874 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 336051786 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 153071265 # num instructions producing a value
-system.cpu.iew.wb_consumers 267284033 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.351333 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.572691 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 14115058 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 861860 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 243135580 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.348269 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.043603 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 113362923 46.63% 46.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 66036162 27.16% 73.79% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 21343595 8.78% 82.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 13169605 5.42% 87.98% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 8174730 3.36% 91.34% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 4365960 1.80% 93.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 2981752 1.23% 94.36% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 2446011 1.01% 95.37% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 11254842 4.63% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 243135580 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 273037830 # Number of instructions committed
-system.cpu.commit.committedOps 327812212 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 168107892 # Number of memory references committed
-system.cpu.commit.loads 85732275 # Number of loads committed
-system.cpu.commit.membars 11033 # Number of memory barriers committed
-system.cpu.commit.branches 30563525 # Number of branches committed
-system.cpu.commit.fp_insts 114216705 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 258331703 # Number of committed integer instructions.
-system.cpu.commit.function_calls 6225114 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 104312485 31.82% 31.82% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 2145917 0.65% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 32.48% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 6594343 2.01% 34.49% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 34.49% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 7943502 2.42% 36.91% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 3118180 0.95% 37.86% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 1563217 0.48% 38.34% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 19652356 6.00% 44.33% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 7136937 2.18% 46.51% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 175285 0.05% 48.72% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 44185201 13.48% 62.20% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 55008399 16.78% 78.98% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 41547074 12.67% 91.65% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 27367218 8.35% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 327812212 # Class of committed instruction
-system.cpu.commit.bw_lim_events 11254842 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 573805485 # The number of ROB reads
-system.cpu.rob.rob_writes 686062388 # The number of ROB writes
-system.cpu.timesIdled 39277 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 3340854 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 273037218 # Number of Instructions Simulated
-system.cpu.committedOps 327811600 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.910798 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.910798 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.097938 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.097938 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 325088854 # number of integer regfile reads
-system.cpu.int_regfile_writes 134066659 # number of integer regfile writes
-system.cpu.fp_regfile_reads 186464530 # number of floating regfile reads
-system.cpu.fp_regfile_writes 131741747 # number of floating regfile writes
-system.cpu.cc_regfile_reads 1279144313 # number of cc regfile reads
-system.cpu.cc_regfile_writes 80001955 # number of cc regfile writes
-system.cpu.misc_regfile_reads 1055862294 # number of misc regfile reads
-system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 1544317 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.844251 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 161914838 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1544829 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 104.810848 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 91273000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.844251 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999696 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999696 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 333130269 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 333130269 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 80902071 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 80902071 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 80921196 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 80921196 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 69698 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 69698 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 10906 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 10906 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 161823267 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 161823267 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 161892965 # number of overall hits
-system.cpu.dcache.overall_hits::total 161892965 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 2746434 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 2746434 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1131503 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1131503 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 13 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 13 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 3877937 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 3877937 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 3877950 # number of overall misses
-system.cpu.dcache.overall_misses::total 3877950 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 47498967000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 47498967000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 9188860405 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 9188860405 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 56687827405 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 56687827405 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 56687827405 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 56687827405 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 83648505 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 83648505 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 69711 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 69711 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10910 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 10910 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 165701204 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 165701204 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 165770915 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 165770915 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032833 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.032833 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013790 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.013790 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000186 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.000186 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000367 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000367 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.023403 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.023403 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.023393 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.023393 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17294.778247 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 17294.778247 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8120.933312 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 8120.933312 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 14618.037221 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 14618.037221 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 14617.988217 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 14617.988217 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 1101938 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 136754 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 8.057812 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 1544317 # number of writebacks
-system.cpu.dcache.writebacks::total 1544317 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1422290 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 1422290 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 910806 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 910806 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 2333096 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 2333096 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 2333096 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 2333096 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1324144 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 1324144 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220697 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 220697 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 7 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 7 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 1544841 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 1544841 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 1544848 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 1544848 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27090401500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 27090401500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1844259187 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 1844259187 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 932500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 932500 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28934660687 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 28934660687 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28935593187 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 28935593187 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015830 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015830 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002690 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002690 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000100 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000100 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009323 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.009323 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009319 # mshr miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20458.803197 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20458.803197 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8356.521326 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8356.521326 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 133214.285714 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 133214.285714 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18729.863259 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 18729.863259 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18730.382010 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 18730.382010 # average overall mshr miss latency
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-system.cpu.icache.tags.replacements 727442 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.812488 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 81555981 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 727954 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 112.034526 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 348938500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.812488 # Average occupied blocks per requestor
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-system.cpu.icache.tags.occ_percent::total 0.999634 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 98 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 67 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu.icache.ReadReq_misses::total 735249 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 735249 # number of demand (read+write) misses
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-system.cpu.icache.ReadReq_miss_latency::total 8470113937 # number of ReadReq miss cycles
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-system.cpu.icache.demand_avg_miss_latency::total 11520.061825 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 11520.061825 # average overall miss latency
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 7937418446 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 7937418446 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 7937418446 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 7937418446 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 7937418446 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 10903.466680 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10903.466680 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 10903.466680 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10903.466680 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 10903.466680 # average overall mshr miss latency
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-system.cpu.l2cache.prefetcher.num_hwpf_issued 402290 # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified 402345 # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit 51 # number of redundant prefetches already in prefetch queue
-system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage 28015 # number of prefetches not generated due to page crossing
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-system.cpu.l2cache.tags.replacements 0 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 5251.876732 # Cycle average of tags in use
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-system.cpu.l2cache.tags.avg_refs 288.209568 # Average number of references to valid blocks.
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-system.cpu.l2cache.tags.occ_blocks::writebacks 5160.149937 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 91.726796 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_blocks::1024 6128 # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2 48 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3 2 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4 101 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 547 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 740 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 550 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4130 # Occupied blocks per task id
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-system.cpu.l2cache.tags.data_accesses 70659625 # Number of data accesses
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-system.cpu.l2cache.WritebackClean_hits::total 1048519 # number of WritebackClean hits
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-system.cpu.l2cache.overall_hits::total 2014188 # number of overall hits
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-system.cpu.l2cache.ReadCleanReq_misses::total 29612 # number of ReadCleanReq misses
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-system.cpu.l2cache.overall_mshr_hits::cpu.data 91 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 102 # number of overall MSHR hits
-system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 54077 # number of HardPFReq MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_misses::total 54077 # number of HardPFReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 18 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::total 18 # number of UpgradeReq MSHR misses
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-system.cpu.l2cache.ReadExReq_mshr_misses::total 735 # number of ReadExReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 29601 # number of ReadCleanReq MSHR misses
-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 29601 # number of ReadCleanReq MSHR misses
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-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 228098 # number of ReadSharedReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst 29601 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.data 228833 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::total 258434 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst 29601 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.data 228833 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 54077 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 312511 # number of overall MSHR misses
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 203156315 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 203156315 # number of HardPFReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 279000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 279000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64169000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64169000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 2480103000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 2480103000 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16573484500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16573484500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 2480103000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16637653500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 19117756500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 2480103000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16637653500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 203156315 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 19320912815 # number of overall MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003330 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003330 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.040667 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.172262 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.172262 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.113711 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.040667 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148128 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.137505 # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 3756.797067 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15500 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15500 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87304.761905 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87304.761905 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 83784.432958 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 83784.432958 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72659.490658 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72659.490658 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 73975.392170 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 83784.432958 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72706.530527 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 3756.797067 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61824.744777 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 4544579 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 2271779 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254895 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 51433 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 51432 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
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-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124340889500 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 2052102 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 968794 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1302965 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq 55467 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadExResp 220698 # Transaction distribution
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-system.cpu.toL2Bus.snoops 55544 # Total snoops (count)
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-system.cpu.toL2Bus.snoop_fanout::mean 0.131576 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.338031 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
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-system.cpu.toL2Bus.respLayer0.occupancy 1092026360 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2317274956 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%)
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-system.membus.snoops 0 # Total snoops (count)
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+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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+system.cpu.toL2Bus.snoop_filter.tot_requests 4544579
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 2271779
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 254895
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+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1
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+system.cpu.toL2Bus.trans_dist::WritebackClean 1302965
+system.cpu.toL2Bus.trans_dist::HardPFReq 55467
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+system.cpu.toL2Bus.pkt_count::total 6817321
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93141504
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 197705344
+system.cpu.toL2Bus.pkt_size::total 290846848
+system.cpu.toL2Bus.snoops 55544
+system.cpu.toL2Bus.snoopTraffic 4928
+system.cpu.toL2Bus.snoop_fanout::samples 2328287
+system.cpu.toL2Bus.snoop_fanout::mean 0.131576
+system.cpu.toL2Bus.snoop_fanout::stdev 0.338031
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 2021941 86.84% 86.84%
+system.cpu.toL2Bus.snoop_fanout::1 306345 13.16% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 2328287
+system.cpu.toL2Bus.reqLayer0.occupancy 4544048500
+system.cpu.toL2Bus.reqLayer0.utilization 3.7
+system.cpu.toL2Bus.respLayer0.occupancy 1092026360
+system.cpu.toL2Bus.respLayer0.utilization 0.9
+system.cpu.toL2Bus.respLayer1.occupancy 2317274956
+system.cpu.toL2Bus.respLayer1.utilization 1.9
+system.membus.snoop_filter.tot_requests 261096
+system.membus.snoop_filter.hit_single_requests 253777
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 124340889500
+system.membus.trans_dist::ReadResp 260342
+system.membus.trans_dist::UpgradeReq 18
+system.membus.trans_dist::ReadExReq 735
+system.membus.trans_dist::ReadExResp 735
+system.membus.trans_dist::ReadSharedReq 260343
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 522173
+system.membus.pkt_count::total 522173
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16708928
+system.membus.pkt_size::total 16708928
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 261096
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 261096 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 261096
+system.membus.reqLayer0.occupancy 316188421
+system.membus.reqLayer0.utilization 0.3
+system.membus.respLayer1.occupancy 1389693354
+system.membus.respLayer1.utilization 1.1
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index 1b5061343..89604511e 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -90,6 +90,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -165,8 +166,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -177,8 +176,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -239,7 +236,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
drivers=
@@ -248,14 +245,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
@@ -279,6 +277,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -290,7 +289,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -298,6 +297,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -306,6 +312,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -313,7 +320,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
index c881283f7..a91025695 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
@@ -1,10 +1,13 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
+info: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
@@ -31,6 +34,8 @@ col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
0 8 14
1 8 14
2 8 14
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
index 154af3aae..728509d4f 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
@@ -3,17 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:54:12
-gem5 executing on e108600-lin, pid 23918
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/simple-atomic
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 17:56:13
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54231
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
Eon, Version 1.1
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
OO-style eon Time= 0.200000
-Exiting @ tick 201717314000 because target called exit()
+Exiting @ tick 201717314000 because exiting with last active thread context
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
index 5ec20d23b..2e5c48f3e 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.201717 # Number of seconds simulated
-sim_ticks 201717314000 # Number of ticks simulated
-final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1476968 # Simulator instruction rate (inst/s)
-host_op_rate 1773264 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1091168515 # Simulator tick rate (ticks/s)
-host_mem_usage 268416 # Number of bytes of host memory used
-host_seconds 184.86 # Real time elapsed on the host
-sim_insts 273037595 # Number of instructions simulated
-sim_ops 327811950 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 1394641096 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 480709216 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1875350312 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1394641096 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1394641096 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 400047763 # Number of bytes written to this memory
-system.physmem.bytes_written::total 400047763 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 348660274 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 86300511 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 434960785 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 82063567 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 82063567 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 6913839315 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2383083566 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 9296922881 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 6913839315 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 6913839315 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1983209845 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1983209845 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 6913839315 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4366293411 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 11280132726 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 191 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 201717314000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 403434629 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 273037595 # Number of instructions committed
-system.cpu.committedOps 327811950 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 258331481 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
-system.cpu.num_func_calls 12448615 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15799338 # number of instructions that are conditional controls
-system.cpu.num_int_insts 258331481 # number of integer instructions
-system.cpu.num_fp_insts 114216705 # number of float instructions
-system.cpu.num_int_register_reads 938030601 # number of times the integer registers were read
-system.cpu.num_int_register_writes 162499657 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 985884626 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 76361749 # number of times the CC registers were written
-system.cpu.num_mem_refs 168107829 # number of memory refs
-system.cpu.num_load_insts 85732235 # Number of load instructions
-system.cpu.num_store_insts 82375594 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 403434628.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 30563491 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 104312493 31.82% 31.82% # Class of executed instruction
-system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
-system.cpu.op_class::MemRead 44185161 13.48% 62.20% # Class of executed instruction
-system.cpu.op_class::MemWrite 55008376 16.78% 78.98% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 327812145 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 434895828 # Transaction distribution
-system.membus.trans_dist::ReadResp 434906723 # Transaction distribution
-system.membus.trans_dist::WriteReq 82052672 # Transaction distribution
-system.membus.trans_dist::WriteResp 82052672 # Transaction distribution
-system.membus.trans_dist::SoftPFReq 54062 # Transaction distribution
-system.membus.trans_dist::SoftPFResp 54062 # Transaction distribution
-system.membus.trans_dist::LoadLockedReq 10895 # Transaction distribution
-system.membus.trans_dist::StoreCondReq 10895 # Transaction distribution
-system.membus.trans_dist::StoreCondResp 10895 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1034048704 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 517024352 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 517024352 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 517024352 # Request fanout histogram
+sim_seconds 0.201717
+sim_ticks 201717314000
+final_tick 201717314000
+sim_freq 1000000000000
+host_inst_rate 634159
+host_op_rate 761378
+host_tick_rate 468510100
+host_mem_usage 279924
+host_seconds 430.55
+sim_insts 273037595
+sim_ops 327811950
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 201717314000
+system.physmem.bytes_read::cpu.inst 1394641096
+system.physmem.bytes_read::cpu.data 480709216
+system.physmem.bytes_read::total 1875350312
+system.physmem.bytes_inst_read::cpu.inst 1394641096
+system.physmem.bytes_inst_read::total 1394641096
+system.physmem.bytes_written::cpu.data 400047763
+system.physmem.bytes_written::total 400047763
+system.physmem.num_reads::cpu.inst 348660274
+system.physmem.num_reads::cpu.data 86300511
+system.physmem.num_reads::total 434960785
+system.physmem.num_writes::cpu.data 82063567
+system.physmem.num_writes::total 82063567
+system.physmem.bw_read::cpu.inst 6913839315
+system.physmem.bw_read::cpu.data 2383083566
+system.physmem.bw_read::total 9296922881
+system.physmem.bw_inst_read::cpu.inst 6913839315
+system.physmem.bw_inst_read::total 6913839315
+system.physmem.bw_write::cpu.data 1983209845
+system.physmem.bw_write::total 1983209845
+system.physmem.bw_total::cpu.inst 6913839315
+system.physmem.bw_total::cpu.data 4366293411
+system.physmem.bw_total::total 11280132726
+system.pwrStateResidencyTicks::UNDEFINED 201717314000
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000
+system.cpu.dtb.walker.walks 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dtb.walker.walkRequestOrigin::total 0
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.flush_tlb 0
+system.cpu.dtb.flush_tlb_mva 0
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 0
+system.cpu.dtb.align_faults 0
+system.cpu.dtb.prefetch_faults 0
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 201717314000
+system.cpu.itb.walker.walks 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.itb.walker.walkRequestOrigin::total 0
+system.cpu.itb.inst_hits 0
+system.cpu.itb.inst_misses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 0
+system.cpu.itb.flush_tlb_mva 0
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 0
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 191
+system.cpu.pwrStateResidencyTicks::ON 201717314000
+system.cpu.numCycles 403434629
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 273037595
+system.cpu.committedOps 327811950
+system.cpu.num_int_alu_accesses 258331481
+system.cpu.num_fp_alu_accesses 114216705
+system.cpu.num_func_calls 12448615
+system.cpu.num_conditional_control_insts 15799338
+system.cpu.num_int_insts 258331481
+system.cpu.num_fp_insts 114216705
+system.cpu.num_int_register_reads 938030601
+system.cpu.num_int_register_writes 162499657
+system.cpu.num_fp_register_reads 180262959
+system.cpu.num_fp_register_writes 126152315
+system.cpu.num_cc_register_reads 985884626
+system.cpu.num_cc_register_writes 76361749
+system.cpu.num_mem_refs 168107829
+system.cpu.num_load_insts 85732235
+system.cpu.num_store_insts 82375594
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 403434629
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 30563491
+system.cpu.op_class::No_OpClass 0 0.00% 0.00%
+system.cpu.op_class::IntAlu 104312493 31.82% 31.82%
+system.cpu.op_class::IntMult 2145905 0.65% 32.48%
+system.cpu.op_class::IntDiv 0 0.00% 32.48%
+system.cpu.op_class::FloatAdd 0 0.00% 32.48%
+system.cpu.op_class::FloatCmp 0 0.00% 32.48%
+system.cpu.op_class::FloatCvt 0 0.00% 32.48%
+system.cpu.op_class::FloatMult 0 0.00% 32.48%
+system.cpu.op_class::FloatMultAcc 0 0.00% 32.48%
+system.cpu.op_class::FloatDiv 0 0.00% 32.48%
+system.cpu.op_class::FloatMisc 0 0.00% 32.48%
+system.cpu.op_class::FloatSqrt 0 0.00% 32.48%
+system.cpu.op_class::SimdAdd 0 0.00% 32.48%
+system.cpu.op_class::SimdAddAcc 0 0.00% 32.48%
+system.cpu.op_class::SimdAlu 0 0.00% 32.48%
+system.cpu.op_class::SimdCmp 0 0.00% 32.48%
+system.cpu.op_class::SimdCvt 0 0.00% 32.48%
+system.cpu.op_class::SimdMisc 0 0.00% 32.48%
+system.cpu.op_class::SimdMult 0 0.00% 32.48%
+system.cpu.op_class::SimdMultAcc 0 0.00% 32.48%
+system.cpu.op_class::SimdShift 0 0.00% 32.48%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48%
+system.cpu.op_class::SimdSqrt 0 0.00% 32.48%
+system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49%
+system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91%
+system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86%
+system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34%
+system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33%
+system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51%
+system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66%
+system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72%
+system.cpu.op_class::MemRead 44185161 13.48% 62.20%
+system.cpu.op_class::MemWrite 55008376 16.78% 78.98%
+system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65%
+system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 327812145
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 201717314000
+system.membus.trans_dist::ReadReq 434895828
+system.membus.trans_dist::ReadResp 434906723
+system.membus.trans_dist::WriteReq 82052672
+system.membus.trans_dist::WriteResp 82052672
+system.membus.trans_dist::SoftPFReq 54062
+system.membus.trans_dist::SoftPFResp 54062
+system.membus.trans_dist::LoadLockedReq 10895
+system.membus.trans_dist::StoreCondReq 10895
+system.membus.trans_dist::StoreCondResp 10895
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 697320548
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 336728156
+system.membus.pkt_count::total 1034048704
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1394641096
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979
+system.membus.pkt_size::total 2275398075
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 517024352
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 517024352 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 517024352
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index 0faba130d..e57f29bfa 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -87,6 +87,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
drivers=
@@ -411,14 +414,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/eon
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -461,6 +466,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
index c881283f7..a91025695 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
@@ -1,10 +1,13 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
+info: Increasing stack size by one page.
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
@@ -31,6 +34,8 @@ col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
0 8 14
1 8 14
2 8 14
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index bd192fb8a..7aa5c7a76 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
@@ -3,17 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 15:00:59
-gem5 executing on e108600-lin, pid 24143
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/30.eon/arm/linux/simple-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 17:56:13
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54216
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
Eon, Version 1.1
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
OO-style eon Time= 0.510000
-Exiting @ tick 517291025500 because target called exit()
+Exiting @ tick 517297855500 because exiting with last active thread context
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
index 9e7563574..c9e238fff 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
@@ -1,675 +1,675 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.517298 # Number of seconds simulated
-sim_ticks 517297855500 # Number of ticks simulated
-final_tick 517297855500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1075622 # Simulator instruction rate (inst/s)
-host_op_rate 1291325 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2040106124 # Simulator tick rate (ticks/s)
-host_mem_usage 278152 # Number of bytes of host memory used
-host_seconds 253.56 # Real time elapsed on the host
-sim_insts 272739286 # Number of instructions simulated
-sim_ops 327433744 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 166912 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 270336 # Number of bytes read from this memory
-system.physmem.bytes_read::total 437248 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 166912 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 166912 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 2608 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 4224 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 6832 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 322661 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 522593 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 845254 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 322661 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 322661 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 322661 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 522593 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 845254 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 517297855500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 191 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 517297855500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1034595711 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 272739286 # Number of instructions committed
-system.cpu.committedOps 327433744 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 258331537 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
-system.cpu.num_func_calls 12448615 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15799349 # number of instructions that are conditional controls
-system.cpu.num_int_insts 258331537 # number of integer instructions
-system.cpu.num_fp_insts 114216705 # number of float instructions
-system.cpu.num_int_register_reads 979511506 # number of times the integer registers were read
-system.cpu.num_int_register_writes 162499693 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 180262959 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 126152315 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 1242915503 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 76361814 # number of times the CC registers were written
-system.cpu.num_mem_refs 168107847 # number of memory refs
-system.cpu.num_load_insts 85732248 # Number of load instructions
-system.cpu.num_store_insts 82375599 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 1034595710.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 30563503 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 104312544 31.82% 31.82% # Class of executed instruction
-system.cpu.op_class::IntMult 2145905 0.65% 32.48% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 32.48% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 6594343 2.01% 34.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 34.49% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 7943502 2.42% 36.91% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 3118180 0.95% 37.86% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 1563217 0.48% 38.34% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 19652356 6.00% 44.33% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 7136937 2.18% 46.51% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 7062098 2.15% 48.66% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 175285 0.05% 48.72% # Class of executed instruction
-system.cpu.op_class::MemRead 44185174 13.48% 62.20% # Class of executed instruction
-system.cpu.op_class::MemWrite 55008381 16.78% 78.98% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 41547074 12.67% 91.65% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 27367218 8.35% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 327812214 # Class of executed instruction
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-system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks.
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-system.cpu.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id
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-system.cpu.dcache.ReadReq_hits::total 86233963 # number of ReadReq hits
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-system.cpu.dcache.WriteReq_hits::total 82049805 # number of WriteReq hits
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-system.cpu.dcache.SoftPFReq_hits::total 54059 # number of SoftPFReq hits
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-system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 168283768 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 168283768 # number of demand (read+write) hits
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-system.cpu.dcache.overall_hits::total 168337827 # number of overall hits
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-system.cpu.dcache.ReadReq_misses::total 1604 # number of ReadReq misses
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-system.cpu.dcache.WriteReq_misses::total 2872 # number of WriteReq misses
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-system.cpu.dcache.demand_misses::total 4476 # number of demand (read+write) misses
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-system.cpu.dcache.overall_misses::total 4479 # number of overall misses
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-system.cpu.dcache.WriteReq_miss_latency::total 180278500 # number of WriteReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total 269696500 # number of demand (read+write) miss cycles
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-system.cpu.dcache.overall_miss_latency::total 269696500 # number of overall miss cycles
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-system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.SoftPFReq_accesses::total 54062 # number of SoftPFReq accesses(hits+misses)
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-system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 168288244 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 168342306 # number of overall (read+write) accesses
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 62771.065460 # average WriteReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60213.552132 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60213.552132 # average overall miss latency
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-system.cpu.dcache.ReadReq_mshr_misses::total 1603 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2872 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2872 # number of WriteReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses
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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 186000 # number of SoftPFReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265359500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 265359500 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54751.715533 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54751.715533 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61771.065460 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61771.065460 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59256.648045 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59256.648045 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59258.485931 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59258.485931 # average overall mshr miss latency
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-system.cpu.icache.tags.replacements 13796 # number of replacements
-system.cpu.icache.tags.tagsinuse 1765.939670 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 348644750 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 22344.725373 # Average number of references to valid blocks.
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-system.cpu.icache.tags.occ_blocks::cpu.inst 1765.939670 # Average occupied blocks per requestor
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-system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id
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-system.cpu.icache.ReadReq_hits::total 348644750 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 348644750 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 15603 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 15603 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 341054000 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 341054000 # number of demand (read+write) miss cycles
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-system.cpu.icache.overall_miss_latency::total 341054000 # number of overall miss cycles
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-system.cpu.icache.ReadReq_accesses::total 348660353 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 348660353 # number of demand (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21858.232391 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 21858.232391 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 21858.232391 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 21858.232391 # average overall miss latency
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-system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 325451000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 325451000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 325451000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 325451000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 325451000 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20858.232391 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20858.232391 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 20858.232391 # average overall mshr miss latency
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-system.cpu.l2cache.tags.total_refs 20712 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 6832 # Sample count of references to valid blocks.
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-system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 227184 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 227184 # Number of data accesses
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-system.cpu.l2cache.WritebackDirty_hits::writebacks 998 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 998 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 6212 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 6212 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 12995 # number of ReadCleanReq hits
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-system.cpu.l2cache.ReadSharedReq_hits::total 238 # number of ReadSharedReq hits
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+system.cpu.l2cache.tags.sampled_refs 6832
+system.cpu.l2cache.tags.avg_refs 3.031616
+system.cpu.l2cache.tags.warmup_cycle 0
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 2407.314356
+system.cpu.l2cache.tags.occ_blocks::cpu.data 3494.038437
+system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073465
+system.cpu.l2cache.tags.occ_percent::cpu.data 0.106630
+system.cpu.l2cache.tags.occ_percent::total 0.180095
+system.cpu.l2cache.tags.occ_task_id_blocks::1024 6832
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2 33
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 758
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5967
+system.cpu.l2cache.tags.occ_task_id_percent::1024 0.208496
+system.cpu.l2cache.tags.tag_accesses 227184
+system.cpu.l2cache.tags.data_accesses 227184
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 517297855500
+system.cpu.l2cache.WritebackDirty_hits::writebacks 998
+system.cpu.l2cache.WritebackDirty_hits::total 998
+system.cpu.l2cache.WritebackClean_hits::writebacks 6212
+system.cpu.l2cache.WritebackClean_hits::total 6212
+system.cpu.l2cache.ReadExReq_hits::cpu.data 16
+system.cpu.l2cache.ReadExReq_hits::total 16
+system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 12995
+system.cpu.l2cache.ReadCleanReq_hits::total 12995
+system.cpu.l2cache.ReadSharedReq_hits::cpu.data 238
+system.cpu.l2cache.ReadSharedReq_hits::total 238
+system.cpu.l2cache.demand_hits::cpu.inst 12995
+system.cpu.l2cache.demand_hits::cpu.data 254
+system.cpu.l2cache.demand_hits::total 13249
+system.cpu.l2cache.overall_hits::cpu.inst 12995
+system.cpu.l2cache.overall_hits::cpu.data 254
+system.cpu.l2cache.overall_hits::total 13249
+system.cpu.l2cache.ReadExReq_misses::cpu.data 2856
+system.cpu.l2cache.ReadExReq_misses::total 2856
+system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2608
+system.cpu.l2cache.ReadCleanReq_misses::total 2608
+system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1368
+system.cpu.l2cache.ReadSharedReq_misses::total 1368
+system.cpu.l2cache.demand_misses::cpu.inst 2608
+system.cpu.l2cache.demand_misses::cpu.data 4224
+system.cpu.l2cache.demand_misses::total 6832
+system.cpu.l2cache.overall_misses::cpu.inst 2608
+system.cpu.l2cache.overall_misses::cpu.data 4224
+system.cpu.l2cache.overall_misses::total 6832
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 172926500
+system.cpu.l2cache.ReadExReq_miss_latency::total 172926500
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 157900000
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 157900000
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 82959000
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 82959000
+system.cpu.l2cache.demand_miss_latency::cpu.inst 157900000
+system.cpu.l2cache.demand_miss_latency::cpu.data 255885500
+system.cpu.l2cache.demand_miss_latency::total 413785500
+system.cpu.l2cache.overall_miss_latency::cpu.inst 157900000
+system.cpu.l2cache.overall_miss_latency::cpu.data 255885500
+system.cpu.l2cache.overall_miss_latency::total 413785500
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 998
+system.cpu.l2cache.WritebackDirty_accesses::total 998
+system.cpu.l2cache.WritebackClean_accesses::writebacks 6212
+system.cpu.l2cache.WritebackClean_accesses::total 6212
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872
+system.cpu.l2cache.ReadExReq_accesses::total 2872
+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 15603
+system.cpu.l2cache.ReadCleanReq_accesses::total 15603
+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1606
+system.cpu.l2cache.ReadSharedReq_accesses::total 1606
+system.cpu.l2cache.demand_accesses::cpu.inst 15603
+system.cpu.l2cache.demand_accesses::cpu.data 4478
+system.cpu.l2cache.demand_accesses::total 20081
+system.cpu.l2cache.overall_accesses::cpu.inst 15603
+system.cpu.l2cache.overall_accesses::cpu.data 4478
+system.cpu.l2cache.overall_accesses::total 20081
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429
+system.cpu.l2cache.ReadExReq_miss_rate::total 0.994429
+system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.167147
+system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.167147
+system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.851806
+system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.851806
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167147
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.943278
+system.cpu.l2cache.demand_miss_rate::total 0.340222
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167147
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.943278
+system.cpu.l2cache.overall_miss_rate::total 0.340222
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60548.494398
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60548.494398
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60544.478528
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60544.478528
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60642.543860
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60642.543860
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60544.478528
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60578.953598
+system.cpu.l2cache.demand_avg_miss_latency::total 60565.793326
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60544.478528
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60578.953598
+system.cpu.l2cache.overall_avg_miss_latency::total 60565.793326
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856
+system.cpu.l2cache.ReadExReq_mshr_misses::total 2856
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2608
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2608
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1368
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1368
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2608
+system.cpu.l2cache.demand_mshr_misses::cpu.data 4224
+system.cpu.l2cache.demand_mshr_misses::total 6832
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2608
+system.cpu.l2cache.overall_mshr_misses::cpu.data 4224
+system.cpu.l2cache.overall_mshr_misses::total 6832
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 144366500
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 144366500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 131820000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 131820000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 69279000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 69279000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 131820000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 213645500
+system.cpu.l2cache.demand_mshr_miss_latency::total 345465500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 131820000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 213645500
+system.cpu.l2cache.overall_mshr_miss_latency::total 345465500
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994429
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.167147
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.167147
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.851806
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.851806
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167147
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943278
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167147
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943278
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50548.494398
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50548.494398
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50544.478528
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50544.478528
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50642.543860
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50642.543860
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50544.478528
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50578.953598
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50565.793326
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50544.478528
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50578.953598
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50565.793326
+system.cpu.toL2Bus.snoop_filter.tot_requests 35209
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 15221
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7665
+system.cpu.toL2Bus.snoop_filter.tot_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 517297855500
+system.cpu.toL2Bus.trans_dist::ReadResp 17209
+system.cpu.toL2Bus.trans_dist::WritebackDirty 998
+system.cpu.toL2Bus.trans_dist::WritebackClean 13796
+system.cpu.toL2Bus.trans_dist::CleanEvict 334
+system.cpu.toL2Bus.trans_dist::ReadExReq 2872
+system.cpu.toL2Bus.trans_dist::ReadExResp 2872
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 15603
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 1606
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45002
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10288
+system.cpu.toL2Bus.pkt_count::total 55290
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1881536
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350464
+system.cpu.toL2Bus.pkt_size::total 2232000
+system.cpu.toL2Bus.snoops 0
+system.cpu.toL2Bus.snoopTraffic 0
+system.cpu.toL2Bus.snoop_fanout::samples 20081
+system.cpu.toL2Bus.snoop_fanout::mean 0.386335
+system.cpu.toL2Bus.snoop_fanout::stdev 0.486921
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 12323 61.37% 61.37%
+system.cpu.toL2Bus.snoop_fanout::1 7758 38.63% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 1
+system.cpu.toL2Bus.snoop_fanout::total 20081
+system.cpu.toL2Bus.reqLayer0.occupancy 32398500
+system.cpu.toL2Bus.reqLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 23404500
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 6717000
+system.cpu.toL2Bus.respLayer1.utilization 0.0
+system.membus.snoop_filter.tot_requests 6833
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 517297855500
+system.membus.trans_dist::ReadResp 3976
+system.membus.trans_dist::ReadExReq 2856
+system.membus.trans_dist::ReadExResp 2856
+system.membus.trans_dist::ReadSharedReq 3976
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13664
+system.membus.pkt_count::total 13664
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 437248
+system.membus.pkt_size::total 437248
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 6833
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 6833 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 6833
+system.membus.reqLayer0.occupancy 7281500
+system.membus.reqLayer0.utilization 0.0
+system.membus.respLayer1.occupancy 34160000
+system.membus.respLayer1.utilization 0.0
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 5d9ef8c4a..721f1a541 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -817,7 +817,7 @@ executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/li
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
pgid=100
pid=100
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index fb1e27e73..6aa244964 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Apr 2 2017 11:48:43
-gem5 started Apr 2 2017 11:49:00
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87253
+gem5 compiled Apr 3 2017 04:18:56
+gem5 started Apr 3 2017 04:19:11
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 3566
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
@@ -647,4 +647,4 @@ Global frequency set at 1000000000000 ticks per second
2000: 2845746745
1000: 2068042552
0: 290958364
-Exiting @ tick 339069355000 because target called exit()
+Exiting @ tick 339069355000 because exiting with last active thread context
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
index 48dadbf2b..51dd3b610 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.339069
sim_ticks 339069355000
final_tick 339069355000
sim_freq 1000000000000
-host_inst_rate 200289
-host_op_rate 246583
-host_tick_rate 106004783
-host_mem_usage 288044
-host_seconds 3198.62
+host_inst_rate 210410
+host_op_rate 259043
+host_tick_rate 111361442
+host_mem_usage 288088
+host_seconds 3044.76
sim_insts 640649299
sim_ops 788724958
system.voltage_domain.voltage 1
@@ -458,7 +458,7 @@ system.cpu.fetch.Insts 824295259
system.cpu.fetch.Branches 175312537
system.cpu.fetch.predictedBranches 103250498
system.cpu.fetch.Cycles 638595633
-system.cpu.fetch.SquashCycles 8083491
+system.cpu.fetch.SquashCycles 8083490
system.cpu.fetch.MiscStallCycles 2728
system.cpu.fetch.PendingTrapStallCycles 17
system.cpu.fetch.IcacheWaitRetryStallCycles 3109
@@ -516,7 +516,7 @@ system.cpu.iq.iqInstsAdded 899826395
system.cpu.iq.iqNonSpecInstsAdded 12582
system.cpu.iq.iqInstsIssued 860048195
system.cpu.iq.iqSquashedInstsIssued 9222152
-system.cpu.iq.iqSquashedInstsExamined 111114019
+system.cpu.iq.iqSquashedInstsExamined 111114018
system.cpu.iq.iqSquashedOperandsExamined 244270336
system.cpu.iq.iqSquashedNonSpecRemoved 428
system.cpu.iq.issued_per_cycle::samples 677669366
@@ -617,7 +617,7 @@ system.cpu.iq.rate 1.268248
system.cpu.iq.fu_busy_cnt 277608649
system.cpu.iq.fu_busy_rate 0.322783
system.cpu.iq.int_inst_queue_reads 2621941266
-system.cpu.iq.int_inst_queue_writes 980329396
+system.cpu.iq.int_inst_queue_writes 980329395
system.cpu.iq.int_inst_queue_wakeup_accesses 820105906
system.cpu.iq.fp_inst_queue_reads 62655291
system.cpu.iq.fp_inst_queue_writes 30642249
@@ -735,7 +735,7 @@ system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
system.cpu.commit.op_class_0::total 788730070
system.cpu.commit.bw_lim_events 29951867
system.cpu.rob.rob_reads 1525019812
-system.cpu.rob.rob_writes 1798395927
+system.cpu.rob.rob_writes 1798395926
system.cpu.timesIdled 10540
system.cpu.idleCycles 469345
system.cpu.committedInsts 640649299
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 5997dda79..8d15582fe 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -90,6 +90,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -165,8 +166,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -177,8 +176,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -239,7 +236,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
drivers=
@@ -248,14 +245,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
@@ -279,6 +277,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -290,7 +289,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -298,6 +297,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -306,6 +312,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -313,7 +320,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
index 937e051a4..92c744310 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
@@ -1,3 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: fcntl64(3, 2) passed through to host
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
index 74eea3e5b..2146043b6 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -3,15 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-at
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:51:02
-gem5 executing on e108600-lin, pid 23320
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 17:56:15
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54237
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
637000: 2581848540
636000: 4117852332
635000: 329081094
@@ -650,4 +647,4 @@ info: Increasing stack size by one page.
2000: 2845746745
1000: 2068042552
0: 290958364
-Exiting @ tick 395726778500 because target called exit()
+Exiting @ tick 395726778500 because exiting with last active thread context
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
index c1630ee45..b1e10c075 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.395727 # Number of seconds simulated
-sim_ticks 395726778500 # Number of ticks simulated
-final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1825974 # Simulator instruction rate (inst/s)
-host_op_rate 2248015 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1127888505 # Simulator tick rate (ticks/s)
-host_mem_usage 268260 # Number of bytes of host memory used
-host_seconds 350.86 # Real time elapsed on the host
-sim_insts 640654411 # Number of instructions simulated
-sim_ops 788730070 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 2573511596 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1144718516 # Number of bytes read from this memory
-system.physmem.bytes_read::total 3718230112 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 2573511596 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 2573511596 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 523317413 # Number of bytes written to this memory
-system.physmem.bytes_written::total 523317413 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 643377899 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 250335238 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 893713137 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 128957216 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 128957216 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 6503253598 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2892699151 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 9395952748 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 6503253598 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 6503253598 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1322421027 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1322421027 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 6503253598 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4215120178 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 10718373776 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 673 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 395726778500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 791453558 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 640654411 # Number of instructions committed
-system.cpu.committedOps 788730070 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
-system.cpu.num_func_calls 37261296 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
-system.cpu.num_int_insts 682251400 # number of integer instructions
-system.cpu.num_fp_insts 24239771 # number of float instructions
-system.cpu.num_int_register_reads 1268495038 # number of times the integer registers were read
-system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 2369173294 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
-system.cpu.num_mem_refs 381221435 # number of memory refs
-system.cpu.num_load_insts 252240938 # Number of load instructions
-system.cpu.num_store_insts 128980497 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 791453557.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 137364860 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
-system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
-system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction
-system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 788730744 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 893703778 # Transaction distribution
-system.membus.trans_dist::ReadResp 893709517 # Transaction distribution
-system.membus.trans_dist::WriteReq 128951477 # Transaction distribution
-system.membus.trans_dist::WriteResp 128951477 # Transaction distribution
-system.membus.trans_dist::SoftPFReq 3620 # Transaction distribution
-system.membus.trans_dist::SoftPFResp 3620 # Transaction distribution
-system.membus.trans_dist::LoadLockedReq 5739 # Transaction distribution
-system.membus.trans_dist::StoreCondReq 5739 # Transaction distribution
-system.membus.trans_dist::StoreCondResp 5739 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 2045340706 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 1022670353 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 1022670353 # Request fanout histogram
+sim_seconds 0.395727
+sim_ticks 395726778500
+final_tick 395726778500
+sim_freq 1000000000000
+host_inst_rate 761557
+host_op_rate 937577
+host_tick_rate 470407263
+host_mem_usage 279508
+host_seconds 841.24
+sim_insts 640654411
+sim_ops 788730070
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 395726778500
+system.physmem.bytes_read::cpu.inst 2573511596
+system.physmem.bytes_read::cpu.data 1144718516
+system.physmem.bytes_read::total 3718230112
+system.physmem.bytes_inst_read::cpu.inst 2573511596
+system.physmem.bytes_inst_read::total 2573511596
+system.physmem.bytes_written::cpu.data 523317413
+system.physmem.bytes_written::total 523317413
+system.physmem.num_reads::cpu.inst 643377899
+system.physmem.num_reads::cpu.data 250335238
+system.physmem.num_reads::total 893713137
+system.physmem.num_writes::cpu.data 128957216
+system.physmem.num_writes::total 128957216
+system.physmem.bw_read::cpu.inst 6503253598
+system.physmem.bw_read::cpu.data 2892699151
+system.physmem.bw_read::total 9395952748
+system.physmem.bw_inst_read::cpu.inst 6503253598
+system.physmem.bw_inst_read::total 6503253598
+system.physmem.bw_write::cpu.data 1322421027
+system.physmem.bw_write::total 1322421027
+system.physmem.bw_total::cpu.inst 6503253598
+system.physmem.bw_total::cpu.data 4215120178
+system.physmem.bw_total::total 10718373776
+system.pwrStateResidencyTicks::UNDEFINED 395726778500
+system.cpu_clk_domain.clock 500
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500
+system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.read_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.read_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_hits 0
+system.cpu.dstage2_mmu.stage2_tlb.write_misses 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.dstage2_mmu.stage2_tlb.align_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.dstage2_mmu.stage2_tlb.hits 0
+system.cpu.dstage2_mmu.stage2_tlb.misses 0
+system.cpu.dstage2_mmu.stage2_tlb.accesses 0
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500
+system.cpu.dtb.walker.walks 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.dtb.walker.walkRequestOrigin::total 0
+system.cpu.dtb.inst_hits 0
+system.cpu.dtb.inst_misses 0
+system.cpu.dtb.read_hits 0
+system.cpu.dtb.read_misses 0
+system.cpu.dtb.write_hits 0
+system.cpu.dtb.write_misses 0
+system.cpu.dtb.flush_tlb 0
+system.cpu.dtb.flush_tlb_mva 0
+system.cpu.dtb.flush_tlb_mva_asid 0
+system.cpu.dtb.flush_tlb_asid 0
+system.cpu.dtb.flush_entries 0
+system.cpu.dtb.align_faults 0
+system.cpu.dtb.prefetch_faults 0
+system.cpu.dtb.domain_faults 0
+system.cpu.dtb.perms_faults 0
+system.cpu.dtb.read_accesses 0
+system.cpu.dtb.write_accesses 0
+system.cpu.dtb.inst_accesses 0
+system.cpu.dtb.hits 0
+system.cpu.dtb.misses 0
+system.cpu.dtb.accesses 0
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500
+system.cpu.istage2_mmu.stage2_tlb.walker.walks 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0
+system.cpu.istage2_mmu.stage2_tlb.inst_hits 0
+system.cpu.istage2_mmu.stage2_tlb.inst_misses 0
+system.cpu.istage2_mmu.stage2_tlb.read_hits 0
+system.cpu.istage2_mmu.stage2_tlb.read_misses 0
+system.cpu.istage2_mmu.stage2_tlb.write_hits 0
+system.cpu.istage2_mmu.stage2_tlb.write_misses 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0
+system.cpu.istage2_mmu.stage2_tlb.flush_entries 0
+system.cpu.istage2_mmu.stage2_tlb.align_faults 0
+system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0
+system.cpu.istage2_mmu.stage2_tlb.domain_faults 0
+system.cpu.istage2_mmu.stage2_tlb.perms_faults 0
+system.cpu.istage2_mmu.stage2_tlb.read_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.write_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0
+system.cpu.istage2_mmu.stage2_tlb.hits 0
+system.cpu.istage2_mmu.stage2_tlb.misses 0
+system.cpu.istage2_mmu.stage2_tlb.accesses 0
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 395726778500
+system.cpu.itb.walker.walks 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 0
+system.cpu.itb.walker.walkRequestOrigin::total 0
+system.cpu.itb.inst_hits 0
+system.cpu.itb.inst_misses 0
+system.cpu.itb.read_hits 0
+system.cpu.itb.read_misses 0
+system.cpu.itb.write_hits 0
+system.cpu.itb.write_misses 0
+system.cpu.itb.flush_tlb 0
+system.cpu.itb.flush_tlb_mva 0
+system.cpu.itb.flush_tlb_mva_asid 0
+system.cpu.itb.flush_tlb_asid 0
+system.cpu.itb.flush_entries 0
+system.cpu.itb.align_faults 0
+system.cpu.itb.prefetch_faults 0
+system.cpu.itb.domain_faults 0
+system.cpu.itb.perms_faults 0
+system.cpu.itb.read_accesses 0
+system.cpu.itb.write_accesses 0
+system.cpu.itb.inst_accesses 0
+system.cpu.itb.hits 0
+system.cpu.itb.misses 0
+system.cpu.itb.accesses 0
+system.cpu.workload.numSyscalls 673
+system.cpu.pwrStateResidencyTicks::ON 395726778500
+system.cpu.numCycles 791453558
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 640654411
+system.cpu.committedOps 788730070
+system.cpu.num_int_alu_accesses 682251400
+system.cpu.num_fp_alu_accesses 24239771
+system.cpu.num_func_calls 37261296
+system.cpu.num_conditional_control_insts 91575866
+system.cpu.num_int_insts 682251400
+system.cpu.num_fp_insts 24239771
+system.cpu.num_int_register_reads 1268495038
+system.cpu.num_int_register_writes 468423268
+system.cpu.num_fp_register_reads 28064643
+system.cpu.num_fp_register_writes 21684311
+system.cpu.num_cc_register_reads 2369173294
+system.cpu.num_cc_register_writes 351919006
+system.cpu.num_mem_refs 381221435
+system.cpu.num_load_insts 252240938
+system.cpu.num_store_insts 128980497
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 791453558
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 137364860
+system.cpu.op_class::No_OpClass 0 0.00% 0.00%
+system.cpu.op_class::IntAlu 385757467 48.91% 48.91%
+system.cpu.op_class::IntMult 5173441 0.66% 49.56%
+system.cpu.op_class::IntDiv 0 0.00% 49.56%
+system.cpu.op_class::FloatAdd 0 0.00% 49.56%
+system.cpu.op_class::FloatCmp 0 0.00% 49.56%
+system.cpu.op_class::FloatCvt 0 0.00% 49.56%
+system.cpu.op_class::FloatMult 0 0.00% 49.56%
+system.cpu.op_class::FloatMultAcc 0 0.00% 49.56%
+system.cpu.op_class::FloatDiv 0 0.00% 49.56%
+system.cpu.op_class::FloatMisc 0 0.00% 49.56%
+system.cpu.op_class::FloatSqrt 0 0.00% 49.56%
+system.cpu.op_class::SimdAdd 0 0.00% 49.56%
+system.cpu.op_class::SimdAddAcc 0 0.00% 49.56%
+system.cpu.op_class::SimdAlu 0 0.00% 49.56%
+system.cpu.op_class::SimdCmp 0 0.00% 49.56%
+system.cpu.op_class::SimdCvt 0 0.00% 49.56%
+system.cpu.op_class::SimdMisc 0 0.00% 49.56%
+system.cpu.op_class::SimdMult 0 0.00% 49.56%
+system.cpu.op_class::SimdMultAcc 0 0.00% 49.56%
+system.cpu.op_class::SimdShift 0 0.00% 49.56%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56%
+system.cpu.op_class::SimdSqrt 0 0.00% 49.56%
+system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65%
+system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05%
+system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37%
+system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67%
+system.cpu.op_class::SimdFloatMult 0 0.00% 51.67%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67%
+system.cpu.op_class::MemRead 245222568 31.09% 82.76%
+system.cpu.op_class::MemWrite 125149823 15.87% 98.62%
+system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51%
+system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 788730744
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 395726778500
+system.membus.trans_dist::ReadReq 893703778
+system.membus.trans_dist::ReadResp 893709517
+system.membus.trans_dist::WriteReq 128951477
+system.membus.trans_dist::WriteResp 128951477
+system.membus.trans_dist::SoftPFReq 3620
+system.membus.trans_dist::SoftPFResp 3620
+system.membus.trans_dist::LoadLockedReq 5739
+system.membus.trans_dist::StoreCondReq 5739
+system.membus.trans_dist::StoreCondResp 5739
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 1286755798
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 758584908
+system.membus.pkt_count::total 2045340706
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 2573511596
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929
+system.membus.pkt_size::total 4241547525
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1022670353
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1022670353 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1022670353
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index ab5a083f3..b54691470 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -87,6 +87,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=perlbmk -I. -I lib mdred.makerand.pl
cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
drivers=
@@ -411,14 +414,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/perlbmk
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -461,6 +466,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
index 937e051a4..92c744310 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
@@ -1,3 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: fcntl64(3, 2) passed through to host
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index 75004ec86..e660db33d 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -3,15 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-ti
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:46:39
-gem5 executing on e108600-lin, pid 23194
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 18:24:09
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 59398
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
637000: 2581848540
636000: 4117852332
635000: 329081094
@@ -650,4 +647,4 @@ info: Increasing stack size by one page.
2000: 2845746745
1000: 2068042552
0: 290958364
-Exiting @ tick 1045756396500 because target called exit()
+Exiting @ tick 1046047111500 because exiting with last active thread context
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
index e6b9bff19..be07be0d5 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
@@ -1,686 +1,686 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 1.046047 # Number of seconds simulated
-sim_ticks 1046047111500 # Number of ticks simulated
-final_tick 1046047111500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1255251 # Simulator instruction rate (inst/s)
-host_op_rate 1542152 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2053674689 # Simulator tick rate (ticks/s)
-host_mem_usage 277480 # Number of bytes of host memory used
-host_seconds 509.35 # Real time elapsed on the host
-sim_insts 639366787 # Number of instructions simulated
-sim_ops 785501035 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 112576 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 18471424 # Number of bytes read from this memory
-system.physmem.bytes_read::total 18584000 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 112576 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 112576 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory
-system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1759 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 288616 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 290375 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 107620 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 17658310 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 17765930 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 107620 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 107620 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4044055 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4044055 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4044055 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 107620 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 17658310 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 21809985 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 673 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 1046047111500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 2092094223 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 639366787 # Number of instructions committed
-system.cpu.committedOps 785501035 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 682251400 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 24239771 # Number of float alu accesses
-system.cpu.num_func_calls 37261296 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 91575866 # number of instructions that are conditional controls
-system.cpu.num_int_insts 682251400 # number of integer instructions
-system.cpu.num_fp_insts 24239771 # number of float instructions
-system.cpu.num_int_register_reads 1272307653 # number of times the integer registers were read
-system.cpu.num_int_register_writes 468423268 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 28064643 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 21684311 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 3116296060 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 351919006 # number of times the CC registers were written
-system.cpu.num_mem_refs 381221435 # number of memory refs
-system.cpu.num_load_insts 252240938 # Number of load instructions
-system.cpu.num_store_insts 128980497 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 2092094222.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 137364860 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 385757467 48.91% 48.91% # Class of executed instruction
-system.cpu.op_class::IntMult 5173441 0.66% 49.56% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 49.56% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 637528 0.08% 49.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 49.65% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 3187668 0.40% 50.05% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 2550131 0.32% 50.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 50.37% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 10203074 1.29% 51.67% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 51.67% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 51.67% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 51.67% # Class of executed instruction
-system.cpu.op_class::MemRead 245222568 31.09% 82.76% # Class of executed instruction
-system.cpu.op_class::MemWrite 125149823 15.87% 98.62% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 7018370 0.89% 99.51% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 3830674 0.49% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 788730744 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1046047111500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 778046 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4093.536872 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 1048273500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4093.536872 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999399 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999399 # Average percentage of cache occupancy
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20632.983934 # average overall mshr miss latency
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-system.cpu.l2cache.ReadCleanReq_hits::total 8449 # number of ReadCleanReq hits
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+system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0 89
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+system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1440
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+system.cpu.l2cache.tags.occ_task_id_percent::1024 1
+system.cpu.l2cache.tags.tag_accesses 12914999
+system.cpu.l2cache.tags.data_accesses 12914999
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+system.cpu.l2cache.WritebackDirty_hits::writebacks 88967
+system.cpu.l2cache.WritebackDirty_hits::total 88967
+system.cpu.l2cache.WritebackClean_hits::writebacks 8752
+system.cpu.l2cache.WritebackClean_hits::total 8752
+system.cpu.l2cache.ReadExReq_hits::cpu.data 3230
+system.cpu.l2cache.ReadExReq_hits::total 3230
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+system.cpu.l2cache.ReadCleanReq_hits::total 8449
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3998679500
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+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 106512500
+system.cpu.l2cache.ReadCleanReq_miss_latency::total 106512500
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13462920000
+system.cpu.l2cache.ReadSharedReq_miss_latency::total 13462920000
+system.cpu.l2cache.demand_miss_latency::cpu.inst 106512500
+system.cpu.l2cache.demand_miss_latency::cpu.data 17461599500
+system.cpu.l2cache.demand_miss_latency::total 17568112000
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+system.cpu.l2cache.overall_miss_latency::cpu.data 17461599500
+system.cpu.l2cache.overall_miss_latency::total 17568112000
+system.cpu.l2cache.WritebackDirty_accesses::writebacks 88967
+system.cpu.l2cache.WritebackDirty_accesses::total 88967
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+system.cpu.l2cache.WritebackClean_accesses::total 8752
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+system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 10208
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+system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712819
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+system.cpu.l2cache.demand_accesses::cpu.inst 10208
+system.cpu.l2cache.demand_accesses::cpu.data 782142
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+system.cpu.l2cache.overall_accesses::cpu.data 782142
+system.cpu.l2cache.overall_accesses::total 792350
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953407
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+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.801900
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+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60552.870949
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+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.writebacks::writebacks 66098
+system.cpu.l2cache.writebacks::total 66098
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66093
+system.cpu.l2cache.ReadExReq_mshr_misses::total 66093
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 88922500
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 88922500
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+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312173
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.172316
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+system.cpu.l2cache.demand_mshr_miss_rate::total 0.366473
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.172316
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369007
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.366473
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.801900
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.801900
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50552.870949
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50552.870949
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50501.251556
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50501.251556
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50552.870949
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.461903
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50552.870949
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.461903
+system.cpu.toL2Bus.snoop_filter.tot_requests 1579165
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 786845
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1110
+system.cpu.toL2Bus.snoop_filter.tot_snoops 1590
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1583
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 7
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1046047111500
+system.cpu.toL2Bus.trans_dist::ReadResp 723027
+system.cpu.toL2Bus.trans_dist::WritebackDirty 155065
+system.cpu.toL2Bus.trans_dist::WritebackClean 8769
+system.cpu.toL2Bus.trans_dist::CleanEvict 880772
+system.cpu.toL2Bus.trans_dist::ReadExReq 69323
+system.cpu.toL2Bus.trans_dist::ReadExResp 69323
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 10208
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 712819
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 29185
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342330
+system.cpu.toL2Bus.pkt_count::total 2371515
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1214528
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55750976
+system.cpu.toL2Bus.pkt_size::total 56965504
+system.cpu.toL2Bus.snoops 257791
+system.cpu.toL2Bus.snoopTraffic 4230272
+system.cpu.toL2Bus.snoop_fanout::samples 1050141
+system.cpu.toL2Bus.snoop_fanout::mean 0.002606
+system.cpu.toL2Bus.snoop_fanout::stdev 0.051116
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 1047411 99.74% 99.74%
+system.cpu.toL2Bus.snoop_fanout::1 2723 0.26% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 7 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 1050141
+system.cpu.toL2Bus.reqLayer0.occupancy 887318500
+system.cpu.toL2Bus.reqLayer0.utilization 0.1
+system.cpu.toL2Bus.respLayer0.occupancy 15312000
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 1173213000
+system.cpu.toL2Bus.respLayer1.utilization 0.1
+system.membus.snoop_filter.tot_requests 546577
+system.membus.snoop_filter.hit_single_requests 256223
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 1046047111500
+system.membus.trans_dist::ReadResp 224282
+system.membus.trans_dist::WritebackDirty 66098
+system.membus.trans_dist::CleanEvict 190103
+system.membus.trans_dist::ReadExReq 66093
+system.membus.trans_dist::ReadExResp 66093
+system.membus.trans_dist::ReadSharedReq 224282
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 836951
+system.membus.pkt_count::total 836951
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22814272
+system.membus.pkt_size::total 22814272
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 290376
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 290376 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 290376
+system.membus.reqLayer0.occupancy 811341000
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 1451875000
+system.membus.respLayer1.utilization 0.1
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index e2ac8f237..609dcfe4d 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=vortex lendian.raw
cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
index bbcd9d751..9acbe6def 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
@@ -1,3 +1,5 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index 77b319c20..05ef3fbb2 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -3,12 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:59:48
-gem5 executing on e108600-lin, pid 17544
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 17:56:13
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54227
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-Exiting @ tick 37982056000 because target called exit()
+Exiting @ tick 37944194500 because exiting with last active thread context
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
index 8304f1e87..477f394fc 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
@@ -1,1266 +1,1266 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.037944 # Number of seconds simulated
-sim_ticks 37944194500 # Number of ticks simulated
-final_tick 37944194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 220724 # Simulator instruction rate (inst/s)
-host_op_rate 282280 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 118113932 # Simulator tick rate (ticks/s)
-host_mem_usage 283128 # Number of bytes of host memory used
-host_seconds 321.25 # Real time elapsed on the host
-sim_insts 70907652 # Number of instructions simulated
-sim_ops 90682607 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 2366464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 5687552 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 6178176 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14232192 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 2366464 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 2366464 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6224000 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6224000 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 36976 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 88868 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 96534 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 222378 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 97250 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 97250 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 62366958 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 149892548 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 162822695 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 375082201 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 62366958 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 62366958 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 164030363 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 164030363 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 164030363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 62366958 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 149892548 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 162822695 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 539112564 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 222379 # Number of read requests accepted
-system.physmem.writeReqs 97250 # Number of write requests accepted
-system.physmem.readBursts 222379 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 97250 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 14222400 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9856 # Total number of bytes read from write queue
-system.physmem.bytesWritten 6222336 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 14232256 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 6224000 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 154 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 9631 # Per bank write bursts
-system.physmem.perBankRdBursts::1 9947 # Per bank write bursts
-system.physmem.perBankRdBursts::2 12518 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24674 # Per bank write bursts
-system.physmem.perBankRdBursts::4 17362 # Per bank write bursts
-system.physmem.perBankRdBursts::5 22065 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11751 # Per bank write bursts
-system.physmem.perBankRdBursts::7 14087 # Per bank write bursts
-system.physmem.perBankRdBursts::8 11655 # Per bank write bursts
-system.physmem.perBankRdBursts::9 16110 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11699 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11328 # Per bank write bursts
-system.physmem.perBankRdBursts::12 9447 # Per bank write bursts
-system.physmem.perBankRdBursts::13 9546 # Per bank write bursts
-system.physmem.perBankRdBursts::14 9858 # Per bank write bursts
-system.physmem.perBankRdBursts::15 20547 # Per bank write bursts
-system.physmem.perBankWrBursts::0 5941 # Per bank write bursts
-system.physmem.perBankWrBursts::1 6221 # Per bank write bursts
-system.physmem.perBankWrBursts::2 6116 # Per bank write bursts
-system.physmem.perBankWrBursts::3 6136 # Per bank write bursts
-system.physmem.perBankWrBursts::4 6032 # Per bank write bursts
-system.physmem.perBankWrBursts::5 6294 # Per bank write bursts
-system.physmem.perBankWrBursts::6 6000 # Per bank write bursts
-system.physmem.perBankWrBursts::7 5967 # Per bank write bursts
-system.physmem.perBankWrBursts::8 5964 # Per bank write bursts
-system.physmem.perBankWrBursts::9 6073 # Per bank write bursts
-system.physmem.perBankWrBursts::10 6219 # Per bank write bursts
-system.physmem.perBankWrBursts::11 5919 # Per bank write bursts
-system.physmem.perBankWrBursts::12 6077 # Per bank write bursts
-system.physmem.perBankWrBursts::13 6073 # Per bank write bursts
-system.physmem.perBankWrBursts::14 6160 # Per bank write bursts
-system.physmem.perBankWrBursts::15 6032 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 37944183500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 222379 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 97250 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 111691 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 60016 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 15678 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 10788 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 6218 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 5274 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 4596 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4274 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3538 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 92 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 47 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 9 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1121 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1197 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 1883 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 2533 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3231 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 4047 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 4920 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 5457 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 5977 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6465 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 6839 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 7294 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7804 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 8411 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8593 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 8015 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6688 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6307 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 104 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 40 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 33 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 132661 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 154.093818 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 102.620444 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 209.524421 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 82661 62.31% 62.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 32331 24.37% 86.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6343 4.78% 91.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2828 2.13% 93.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1153 0.87% 94.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1000 0.75% 95.22% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 785 0.59% 95.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 836 0.63% 96.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4724 3.56% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 132661 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5873 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 37.833986 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 211.191475 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511 5868 99.91% 99.91% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023 4 0.07% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::15360-15871 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5873 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.554401 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.514141 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.221324 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 4642 79.04% 79.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 60 1.02% 80.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 721 12.28% 92.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 237 4.04% 96.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 117 1.99% 98.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 50 0.85% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 21 0.36% 99.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 10 0.17% 99.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 9 0.15% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 3 0.05% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads
-system.physmem.totQLat 8400725955 # Total ticks spent queuing
-system.physmem.totMemAccLat 12567444705 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1111125000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 37802.79 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 56552.79 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 374.82 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 163.99 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 375.08 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 164.03 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 4.21 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.93 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 1.28 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.37 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing
-system.physmem.readRowHits 156951 # Number of row buffer hits during reads
-system.physmem.writeRowHits 29827 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 70.63 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 30.67 # Row buffer hit rate for writes
-system.physmem.avgGap 118713.21 # Average gap between requests
-system.physmem.pageHitRate 58.46 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 506618700 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 269259045 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 871329900 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 254250540 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3004974960.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 2939010630 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 75129120 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 12925802790 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 1053663840 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 77310705 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 21977801430 # Total energy per rank (pJ)
-system.physmem_0.averagePower 579.213801 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 31303061618 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 43527335 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1271434000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 212368250 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 2743799817 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 5326073297 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 28346991801 # Time in different power states
-system.physmem_1.actEnergy 440652240 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 234189450 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 715349460 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 253258740 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 2887578720.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 2772991290 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 73095360 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 11918051910 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 1378656480 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 511952955 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 21185918985 # Total energy per rank (pJ)
-system.physmem_1.averagePower 558.344142 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 31672221792 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 50102341 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1221978000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 1946071250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 3589983863 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 4999892367 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 26136166679 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 17059712 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11436495 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 610883 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9177884 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7343978 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 80.018205 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1859096 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 101568 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 235599 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 198019 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 37580 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 22235 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 1946 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 75888390 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 5573583 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 87028801 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 17059712 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9401093 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 65975948 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1248205 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 11552 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 20 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 32118 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 22429818 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 69336 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 72217323 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.523317 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.330813 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 27066857 37.48% 37.48% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 8167411 11.31% 48.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 9106696 12.61% 61.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 27876359 38.60% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 72217323 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.224800 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.146800 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 8951903 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 26171728 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 30965562 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 5674558 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 453572 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 6946604 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 172649 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 100221832 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 2852875 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 453572 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 13609160 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 11386876 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 864961 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 31760902 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 14141852 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 98228803 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 864073 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 4236637 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 68346 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 4658326 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 5438830 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 103135317 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 453117590 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 114171014 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 768 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 93629369 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 9505948 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 19046 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 19073 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12792135 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 24137829 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21734716 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1433415 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2312086 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97293576 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 34871 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 94397579 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 595173 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6645840 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 17792691 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 1085 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 72217323 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.307132 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.170641 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 24111122 33.39% 33.39% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 17469676 24.19% 57.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 17013658 23.56% 81.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 11592271 16.05% 97.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 2029206 2.81% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1390 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 72217323 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 6732689 22.67% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 34 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 11048676 37.21% 59.88% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 11914326 40.12% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 49 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 21 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 49269666 52.19% 52.19% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 86409 0.09% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 33 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 12 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 19 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.29% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 23933468 25.35% 77.64% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21107870 22.36% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 70 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 32 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 94397579 # Type of FU issued
-system.cpu.iq.rate 1.243900 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 29695795 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.314582 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 291303077 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 103985333 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 93134762 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 690 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 96 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 124093153 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1368431 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1271567 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 1549 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11881 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1178978 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 147641 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 185447 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 453572 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 612952 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1120138 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 97344492 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 24137829 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21734716 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 18951 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1593 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1115880 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11881 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 249751 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 231660 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 481411 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 93615083 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 23674361 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 782496 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 16045 # number of nop insts executed
-system.cpu.iew.exec_refs 44580255 # number of memory reference insts executed
-system.cpu.iew.exec_branches 14200394 # Number of branches executed
-system.cpu.iew.exec_stores 20905894 # Number of stores executed
-system.cpu.iew.exec_rate 1.233589 # Inst execution rate
-system.cpu.iew.wb_sent 93237318 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 93134858 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 44916796 # num instructions producing a value
-system.cpu.iew.wb_consumers 76568590 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.227261 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.586622 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 5786029 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 440353 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 71261477 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.272611 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.107279 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 37792643 53.03% 53.03% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 16691471 23.42% 76.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 4304606 6.04% 82.50% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4169247 5.85% 88.35% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1943443 2.73% 91.08% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1235947 1.73% 92.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 743394 1.04% 93.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 579944 0.81% 94.67% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 3800782 5.33% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 71261477 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 70913204 # Number of instructions committed
-system.cpu.commit.committedOps 90688159 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 43422000 # Number of memory references committed
-system.cpu.commit.loads 22866262 # Number of loads committed
-system.cpu.commit.membars 15920 # Number of memory barriers committed
-system.cpu.commit.branches 13741468 # Number of branches committed
-system.cpu.commit.fp_insts 56 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 81528527 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1679850 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 47186033 52.03% 52.03% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 22866242 25.21% 77.33% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 20555706 22.67% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 20 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 32 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 90688159 # Class of committed instruction
-system.cpu.commit.bw_lim_events 3800782 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 163909584 # The number of ROB reads
-system.cpu.rob.rob_writes 193905843 # The number of ROB writes
-system.cpu.timesIdled 54309 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 3671067 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 70907652 # Number of Instructions Simulated
-system.cpu.committedOps 90682607 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.070243 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.070243 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.934368 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.934368 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 101911048 # number of integer regfile reads
-system.cpu.int_regfile_writes 56566498 # number of integer regfile writes
-system.cpu.fp_regfile_reads 60 # number of floating regfile reads
-system.cpu.fp_regfile_writes 50 # number of floating regfile writes
-system.cpu.cc_regfile_reads 344842465 # number of cc regfile reads
-system.cpu.cc_regfile_writes 38739142 # number of cc regfile writes
-system.cpu.misc_regfile_reads 44068796 # number of misc regfile reads
-system.cpu.misc_regfile_writes 31840 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 484861 # number of replacements
-system.cpu.dcache.tags.tagsinuse 510.868864 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40324171 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 485373 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 83.078727 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 154340500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 510.868864 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.997791 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.997791 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 456 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 84436477 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 84436477 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 21401665 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 21401665 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18831129 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18831129 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 60098 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 60098 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 15305 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 15305 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 40232794 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 40232794 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 40292892 # number of overall hits
-system.cpu.dcache.overall_hits::total 40292892 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 563103 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 563103 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1018772 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1018772 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 68943 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 68943 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 618 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 618 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 1581875 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1581875 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1650818 # number of overall misses
-system.cpu.dcache.overall_misses::total 1650818 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 14421291500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 14421291500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 14222478926 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 14222478926 # number of WriteReq miss cycles
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-system.cpu.dcache.LoadLockedReq_miss_latency::total 5900000 # number of LoadLockedReq miss cycles
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-system.cpu.dcache.demand_miss_latency::total 28643770426 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 28643770426 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 28643770426 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 21964768 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 21964768 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 129041 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 129041 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15923 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 15923 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
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-system.cpu.dcache.demand_accesses::total 41814669 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 41943710 # number of overall (read+write) accesses
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-system.cpu.dcache.WriteReq_miss_rate::total 0.051324 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.534272 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.534272 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038812 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038812 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.037831 # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::cpu.data 0.039358 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.039358 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25610.397210 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25610.397210 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 13960.414034 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 13960.414034 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9546.925566 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9546.925566 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 18107.480317 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 18107.480317 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 17351.258846 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 17351.258846 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 104 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 2957939 # number of cycles access was blocked
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-system.cpu.dcache.blocked::no_targets 131286 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 6.933333 # average number of cycles each access was blocked
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-system.cpu.dcache.writebacks::writebacks 484861 # number of writebacks
-system.cpu.dcache.writebacks::total 484861 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 263994 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 263994 # number of ReadReq MSHR hits
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-system.cpu.dcache.WriteReq_mshr_hits::total 870189 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 618 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 618 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 1134183 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 1134183 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 1134183 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 1134183 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299109 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 299109 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148583 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 148583 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37695 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 37695 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 447692 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 447692 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 485387 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 485387 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7100123000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 7100123000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2335671469 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 2335671469 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2001428000 # number of SoftPFReq MSHR miss cycles
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-system.cpu.dcache.demand_mshr_miss_latency::total 9435794469 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11437222469 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 11437222469 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013618 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013618 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007485 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007485 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.292116 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.292116 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010707 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.010707 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011572 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.011572 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23737.577271 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23737.577271 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15719.641339 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15719.641339 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53095.317681 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53095.317681 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21076.531341 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21076.531341 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23563.100102 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 23563.100102 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 325105 # number of replacements
-system.cpu.icache.tags.tagsinuse 510.398248 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 22092527 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 325617 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 67.848199 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 1172472500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.398248 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.996872 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.996872 # Average percentage of cache occupancy
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-system.cpu.icache.tags.age_task_id_blocks_1024::0 84 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 333 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 8 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 45184842 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 45184842 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
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-system.cpu.icache.ReadReq_misses::total 337079 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 337079 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 337079 # number of overall misses
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-system.cpu.icache.ReadReq_miss_latency::total 5811924859 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency::total 5811924859 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 22429606 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses::total 22429606 # number of overall (read+write) accesses
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-system.cpu.icache.overall_miss_rate::total 0.015028 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17242.025932 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 17242.025932 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 17242.025932 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 17242.025932 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 17242.025932 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 559324 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 118 # number of cycles access was blocked
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-system.cpu.icache.writebacks::total 325105 # number of writebacks
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-system.cpu.icache.demand_mshr_hits::cpu.inst 11448 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 11448 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 11448 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 11448 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 325631 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 325631 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 325631 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 325631 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 325631 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 325631 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 5369635927 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5369635927 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 5369635927 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5369635927 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 5369635927 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014518 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.014518 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014518 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.014518 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16489.940844 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16489.940844 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16489.940844 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 16489.940844 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16489.940844 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 16489.940844 # average overall mshr miss latency
-system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.prefetcher.num_hwpf_issued 822760 # number of hwpf issued
-system.cpu.l2cache.prefetcher.pfIdentified 825879 # number of prefetch candidates identified
-system.cpu.l2cache.prefetcher.pfBufferHit 2736 # number of redundant prefetches already in prefetch queue
-system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
-system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu.l2cache.prefetcher.pfSpanPage 78985 # number of prefetches not generated due to page crossing
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.tags.replacements 125384 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 15697.006900 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 681705 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 141714 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 4.810428 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 15640.024987 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 56.981913 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.954591 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.003478 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.958069 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1022 23 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 16307 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3 10 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4 3 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2537 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12202 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 564 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 868 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001404 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 25485617 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 25485617 # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 37944194500 # Cumulative time (in ticks) in various power states
-system.cpu.l2cache.WritebackDirty_hits::writebacks 259863 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackDirty_hits::total 259863 # number of WritebackDirty hits
-system.cpu.l2cache.WritebackClean_hits::writebacks 470316 # number of WritebackClean hits
-system.cpu.l2cache.WritebackClean_hits::total 470316 # number of WritebackClean hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 137267 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 137267 # number of ReadExReq hits
-system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 288609 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadCleanReq_hits::total 288609 # number of ReadCleanReq hits
-system.cpu.l2cache.ReadSharedReq_hits::cpu.data 256036 # number of ReadSharedReq hits
-system.cpu.l2cache.ReadSharedReq_hits::total 256036 # number of ReadSharedReq hits
-system.cpu.l2cache.demand_hits::cpu.inst 288609 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 393303 # number of demand (read+write) hits
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-system.cpu.l2cache.overall_hits::cpu.inst 288609 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 393303 # number of overall hits
-system.cpu.l2cache.overall_hits::total 681912 # number of overall hits
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183092 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89620.579120 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15464.285714 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15464.285714 # average UpgradeReq mshr miss latency
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87021.110573 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78997.944668 # average ReadCleanReq mshr miss latency
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-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79570.072703 # average ReadSharedReq mshr miss latency
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-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80263.126210 # average overall mshr miss latency
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-system.cpu.toL2Bus.snoop_filter.hit_single_requests 810002 # Number of requests hitting in the snoop filter with a single holder of the requested data.
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-system.cpu.toL2Bus.snoop_filter.tot_snoops 18528 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18483 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
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-system.cpu.toL2Bus.trans_dist::WritebackClean 550103 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::HardPFReq 146171 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 14 # Transaction distribution
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-system.cpu.toL2Bus.snoops 271569 # Total snoops (count)
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-system.cpu.toL2Bus.snoop_fanout::mean 0.091409 # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::total 1082573 # Request fanout histogram
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-system.cpu.toL2Bus.respLayer0.occupancy 488577734 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
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-system.membus.trans_dist::ReadExResp 8266 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 214113 # Transaction distribution
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-system.membus.pkt_count::total 570155 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 20456192 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 222393 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 222393 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 222393 # Request fanout histogram
-system.membus.reqLayer0.occupancy 835299244 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1174434906 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 3.1 # Layer utilization (%)
+sim_seconds 0.037944
+sim_ticks 37944194500
+final_tick 37944194500
+sim_freq 1000000000000
+host_inst_rate 98071
+host_op_rate 125422
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+sim_insts 70907652
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+system.voltage_domain.voltage 1
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+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.113560
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.113560
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.239348
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.239348
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113560
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.183092
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.155175
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113560
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.183092
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.297026
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 89620.579120
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15464.285714
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15464.285714
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87021.110573
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87021.110573
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 78997.944668
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 78997.944668
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79570.072703
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79570.072703
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 78997.944668
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 80263.126210
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 79891.378283
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 78997.944668
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 80263.126210
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 89620.579120
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 84537.774963
+system.cpu.toL2Bus.snoop_filter.tot_requests 1620984
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 810002
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 80349
+system.cpu.toL2Bus.snoop_filter.tot_snoops 18528
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 18483
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 45
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 37944194500
+system.cpu.toL2Bus.trans_dist::ReadResp 662386
+system.cpu.toL2Bus.trans_dist::WritebackDirty 357113
+system.cpu.toL2Bus.trans_dist::WritebackClean 550103
+system.cpu.toL2Bus.trans_dist::CleanEvict 28134
+system.cpu.toL2Bus.trans_dist::HardPFReq 146171
+system.cpu.toL2Bus.trans_dist::UpgradeReq 14
+system.cpu.toL2Bus.trans_dist::UpgradeResp 14
+system.cpu.toL2Bus.trans_dist::ReadExReq 148617
+system.cpu.toL2Bus.trans_dist::ReadExResp 148617
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 325631
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 336756
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 976352
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1455635
+system.cpu.toL2Bus.pkt_count::total 2431987
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 41646144
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 62094976
+system.cpu.toL2Bus.pkt_size::total 103741120
+system.cpu.toL2Bus.snoops 271569
+system.cpu.toL2Bus.snoopTraffic 6224896
+system.cpu.toL2Bus.snoop_fanout::samples 1082573
+system.cpu.toL2Bus.snoop_fanout::mean 0.091409
+system.cpu.toL2Bus.snoop_fanout::stdev 0.288334
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 983661 90.86% 90.86%
+system.cpu.toL2Bus.snoop_fanout::1 98867 9.13% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 45 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 1082573
+system.cpu.toL2Bus.reqLayer0.occupancy 1620458000
+system.cpu.toL2Bus.reqLayer0.utilization 4.3
+system.cpu.toL2Bus.respLayer0.occupancy 488577734
+system.cpu.toL2Bus.respLayer0.utilization 1.3
+system.cpu.toL2Bus.respLayer1.occupancy 728149334
+system.cpu.toL2Bus.respLayer1.utilization 1.9
+system.membus.snoop_filter.tot_requests 347777
+system.membus.snoop_filter.hit_single_requests 205067
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 37944194500
+system.membus.trans_dist::ReadResp 214112
+system.membus.trans_dist::WritebackDirty 97250
+system.membus.trans_dist::CleanEvict 28134
+system.membus.trans_dist::UpgradeReq 14
+system.membus.trans_dist::ReadExReq 8266
+system.membus.trans_dist::ReadExResp 8266
+system.membus.trans_dist::ReadSharedReq 214113
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 570155
+system.membus.pkt_count::total 570155
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 20456192
+system.membus.pkt_size::total 20456192
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 222393
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 222393 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 222393
+system.membus.reqLayer0.occupancy 835299244
+system.membus.reqLayer0.utilization 2.2
+system.membus.respLayer1.occupancy 1174434906
+system.membus.respLayer1.utilization 3.1
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index 5a7d7b1a5..5da6802d2 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
index caeab8324..5467490ac 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
@@ -1,4 +1,8 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index fbc8b4e01..19305f061 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:48:52
-gem5 executing on e108600-lin, pid 17438
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 17:56:14
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54235
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 787742202500 because target called exit()
+Exiting @ tick 787835965500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
index 5ac1aa00b..6256fdd50 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
@@ -1,1282 +1,1282 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.787836 # Number of seconds simulated
-sim_ticks 787835965500 # Number of ticks simulated
-final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 263266 # Simulator instruction rate (inst/s)
-host_op_rate 283629 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 134283963 # Simulator tick rate (ticks/s)
-host_mem_usage 329624 # Number of bytes of host memory used
-host_seconds 5866.94 # Real time elapsed on the host
-sim_insts 1544563024 # Number of instructions simulated
-sim_ops 1664032416 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 65344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 236015808 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 63804544 # Number of bytes read from this memory
-system.physmem.bytes_read::total 299885696 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 65344 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 65344 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 104593152 # Number of bytes written to this memory
-system.physmem.bytes_written::total 104593152 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1021 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3687747 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 996946 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 4685714 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1634268 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1634268 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 82941 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 299574808 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 80987092 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 380644841 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 82941 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 82941 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 132760062 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 132760062 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 132760062 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 82941 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 299574808 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 80987092 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 513404904 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 4685714 # Number of read requests accepted
-system.physmem.writeReqs 1634268 # Number of write requests accepted
-system.physmem.readBursts 4685714 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 1634268 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 299374336 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 511360 # Total number of bytes read from write queue
-system.physmem.bytesWritten 104589440 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 299885696 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 104593152 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 7990 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 28 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 301500 # Per bank write bursts
-system.physmem.perBankRdBursts::1 301960 # Per bank write bursts
-system.physmem.perBankRdBursts::2 285447 # Per bank write bursts
-system.physmem.perBankRdBursts::3 288137 # Per bank write bursts
-system.physmem.perBankRdBursts::4 288946 # Per bank write bursts
-system.physmem.perBankRdBursts::5 285921 # Per bank write bursts
-system.physmem.perBankRdBursts::6 281288 # Per bank write bursts
-system.physmem.perBankRdBursts::7 278400 # Per bank write bursts
-system.physmem.perBankRdBursts::8 294011 # Per bank write bursts
-system.physmem.perBankRdBursts::9 300115 # Per bank write bursts
-system.physmem.perBankRdBursts::10 292046 # Per bank write bursts
-system.physmem.perBankRdBursts::11 297684 # Per bank write bursts
-system.physmem.perBankRdBursts::12 299531 # Per bank write bursts
-system.physmem.perBankRdBursts::13 298464 # Per bank write bursts
-system.physmem.perBankRdBursts::14 294115 # Per bank write bursts
-system.physmem.perBankRdBursts::15 290159 # Per bank write bursts
-system.physmem.perBankWrBursts::0 103775 # Per bank write bursts
-system.physmem.perBankWrBursts::1 101738 # Per bank write bursts
-system.physmem.perBankWrBursts::2 99347 # Per bank write bursts
-system.physmem.perBankWrBursts::3 99748 # Per bank write bursts
-system.physmem.perBankWrBursts::4 99113 # Per bank write bursts
-system.physmem.perBankWrBursts::5 98946 # Per bank write bursts
-system.physmem.perBankWrBursts::6 102275 # Per bank write bursts
-system.physmem.perBankWrBursts::7 103989 # Per bank write bursts
-system.physmem.perBankWrBursts::8 105110 # Per bank write bursts
-system.physmem.perBankWrBursts::9 104316 # Per bank write bursts
-system.physmem.perBankWrBursts::10 101973 # Per bank write bursts
-system.physmem.perBankWrBursts::11 102390 # Per bank write bursts
-system.physmem.perBankWrBursts::12 102662 # Per bank write bursts
-system.physmem.perBankWrBursts::13 102242 # Per bank write bursts
-system.physmem.perBankWrBursts::14 104082 # Per bank write bursts
-system.physmem.perBankWrBursts::15 102504 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 787835924500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 4685714 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 1634268 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 2727826 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1050681 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 326941 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 233426 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 158423 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 90275 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 39813 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 24457 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 17994 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 4464 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1780 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 895 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 261 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 24253 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 26721 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 55721 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 72860 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 84494 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 93247 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 99524 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 103226 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 104977 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 106102 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 106319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 107599 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 108399 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 109635 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 109963 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 109142 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 102277 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 101239 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 4710 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 1941 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 910 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 451 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 127 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 40 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 4259361 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 94.841028 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 78.814946 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 102.698820 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 4259361 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 98005 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 47.729004 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 99.044358 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-255 95588 97.53% 97.53% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::256-511 1180 1.20% 98.74% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-767 706 0.72% 99.46% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::768-1023 397 0.41% 99.86% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-1279 101 0.10% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1536-1791 5 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-2303 3 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 98005 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 98005 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.674761 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.634865 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 1.202481 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16 70360 71.79% 71.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::17 1982 2.02% 73.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::18 17660 18.02% 91.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::19 5209 5.32% 97.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20 1729 1.76% 98.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::21 596 0.61% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::22 225 0.23% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::23 114 0.12% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24 71 0.07% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::25 31 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::26 17 0.02% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::27 4 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::31 2 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 98005 # Writes before turning the bus around for reads
-system.physmem.totQLat 162836208305 # Total ticks spent queuing
-system.physmem.totMemAccLat 250543533305 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 23388620000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 34810.99 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 53560.99 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 380.00 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 132.76 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 4.01 # Data bus utilization in percentage
-system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing
-system.physmem.readRowHits 1712017 # Number of row buffer hits during reads
-system.physmem.writeRowHits 340548 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 36.60 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 20.84 # Row buffer hit rate for writes
-system.physmem.avgGap 124657.94 # Average gap between requests
-system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 15118935720 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 8035889730 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 16504816860 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 4222619820 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 59457815040.000015 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 64415436660 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1624122240 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 222796740750 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 36224267040 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 16152645360 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 444563646270 # Total energy per rank (pJ)
-system.physmem_0.averagePower 564.284526 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 642315388170 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 1436139102 # Time in different power states
-system.physmem_0.memoryStateTime::REF 25173062000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 59398115500 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 94331998561 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 118911366978 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 488585283359 # Time in different power states
-system.physmem_1.actEnergy 15292958940 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 8128385265 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 16894132500 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4307956380 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 58918161120.000015 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 64834688190 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1616111040 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 219342669570 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 35641510560 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 18222503400 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 443208649005 # Total energy per rank (pJ)
-system.physmem_1.averagePower 562.564626 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 641423107931 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 1455389769 # Time in different power states
-system.physmem_1.memoryStateTime::REF 24945910000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 67593570250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 92814429154 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 120009883050 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 481016783277 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 286288991 # Number of BP lookups
-system.cpu.branchPred.condPredicted 223379889 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 14638803 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 157014468 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 150316303 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 95.734046 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 16636731 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 3547 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 2042 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 1505 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 46 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1575671932 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 1546978368 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 29302455 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.IcacheWaitRetryStallCycles 1029 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 656906223 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 925 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 1575573272 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.405744 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.233501 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 493163312 31.30% 31.30% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 465492881 29.54% 60.84% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 101391668 6.44% 67.28% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 515525411 32.72% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 1575573272 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.181693 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.312107 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 74679257 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 578142352 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 849952798 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 58148325 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 14650540 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 135611620 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 746 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 2037153887 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 52516232 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 14650540 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 139761664 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 493000122 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 16309 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 837842196 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 90302441 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1976324662 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 26749907 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 45308958 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 126668 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 1624936 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 29276583 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 1985726338 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 9127758695 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 2432766069 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 161 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 310827393 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 177 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 111376144 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 542477238 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 199268014 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 26870545 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 28963209 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1947887828 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 229 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1857408251 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 13517769 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 283855641 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 647022412 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 59 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 1575573272 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.178878 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.151815 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 622703787 39.52% 39.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 326030740 20.69% 60.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 378156304 24.00% 84.22% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 219671219 13.94% 98.16% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 29004864 1.84% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 6358 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 1575573272 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 166096777 40.98% 40.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 2401 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 191354081 47.22% 88.20% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 47812478 11.80% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1138249696 61.28% 61.28% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 803001 0.04% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 34 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 532063614 28.65% 89.97% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 186291823 10.03% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 37 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1857408251 # Type of FU issued
-system.cpu.iq.rate 1.178804 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 405265784 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.218189 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 5709173052 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2231756417 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1805664221 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 288 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 75 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 2262673874 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 17815816 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 84170904 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 66799 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 13274 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 24420969 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 4535474 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 4852528 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 14650540 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 25426885 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1470128 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1947888203 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 542477238 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 199268014 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 167 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 159099 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 1309527 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 13274 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 7696809 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 8718333 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 16415142 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1827780120 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 516898840 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 29628131 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 146 # number of nop insts executed
-system.cpu.iew.exec_refs 698650840 # number of memory reference insts executed
-system.cpu.iew.exec_branches 229565077 # Number of branches executed
-system.cpu.iew.exec_stores 181752000 # Number of stores executed
-system.cpu.iew.exec_rate 1.160000 # Inst execution rate
-system.cpu.iew.wb_sent 1808693799 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1805664296 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1169145221 # num instructions producing a value
-system.cpu.iew.wb_consumers 1689395973 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.145965 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.692049 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 257953466 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 14638116 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 1536081048 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.083297 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.009309 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 955788021 62.22% 62.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 250630730 16.32% 78.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 110093475 7.17% 85.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 55285008 3.60% 89.31% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 29278263 1.91% 91.21% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 34064309 2.22% 93.43% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 24750177 1.61% 95.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 18104449 1.18% 96.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 58086616 3.78% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 1536081048 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 1544563042 # Number of instructions committed
-system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 633153379 # Number of memory references committed
-system.cpu.commit.loads 458306334 # Number of loads committed
-system.cpu.commit.membars 62 # Number of memory barriers committed
-system.cpu.commit.branches 213462427 # Number of branches committed
-system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
-system.cpu.commit.function_calls 13665177 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 174847021 10.51% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction
-system.cpu.commit.bw_lim_events 58086616 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 3399979733 # The number of ROB reads
-system.cpu.rob.rob_writes 3883469027 # The number of ROB writes
-system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 98660 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1544563024 # Number of Instructions Simulated
-system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.020141 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.020141 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.980257 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.980257 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 2175723378 # number of integer regfile reads
-system.cpu.int_regfile_writes 1261531313 # number of integer regfile writes
-system.cpu.fp_regfile_reads 42 # number of floating regfile reads
-system.cpu.fp_regfile_writes 57 # number of floating regfile writes
-system.cpu.cc_regfile_reads 6965468307 # number of cc regfile reads
-system.cpu.cc_regfile_writes 551796531 # number of cc regfile writes
-system.cpu.misc_regfile_reads 675796862 # number of misc regfile reads
-system.cpu.misc_regfile_writes 124 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 17001793 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.963908 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 638014747 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 17002305 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 81846500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.963908 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1335598455 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1335598455 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 469297691 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 469297691 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 168716899 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 168716899 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 638014590 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 638014590 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 638014590 # number of overall hits
-system.cpu.dcache.overall_hits::total 638014590 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 17414213 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 17414213 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3869148 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3869148 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 21283361 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 21283361 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 21283363 # number of overall misses
-system.cpu.dcache.overall_misses::total 21283363 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 440649629000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 440649629000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 157410000348 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 157410000348 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 389500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 389500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 598059629348 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 598059629348 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 598059629348 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 598059629348 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 486711904 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 486711904 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 659297951 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 659297951 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 659297953 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 659297953 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022419 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.022419 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25304.022008 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 25304.022008 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40683.375345 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 40683.375345 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 97375 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 97375 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 28099.867749 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 28099.867749 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 28099.865108 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 28099.865108 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 21246265 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 3823077 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 940794 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 67416 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.583334 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 56.708749 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 17001793 # number of writebacks
-system.cpu.dcache.writebacks::total 17001793 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149457 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 3149457 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1131591 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 1131591 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14264756 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 14264756 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737557 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 2737557 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 354315671500 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency::total 475454764643 # number of overall MSHR miss cycles
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24838.537126 # average ReadReq mshr miss latency
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-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency
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-system.cpu.dcache.demand_avg_mshr_miss_latency::total 27964.118155 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27964.120922 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 27964.120922 # average overall mshr miss latency
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-system.cpu.icache.tags.total_refs 656904625 # Total number of references to valid blocks.
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-system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83603.615242 # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency
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-system.cpu.l2cache.prefetcher.pfIdentified 11644306 # number of prefetch candidates identified
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-system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
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-system.cpu.l2cache.prefetcher.pfSpanPage 4655502 # number of prefetches not generated due to page crossing
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-system.cpu.l2cache.tags.replacements 4647569 # number of replacements
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-system.cpu.l2cache.tags.occ_blocks::writebacks 15652.012265 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 218.779684 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4017 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7150 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2693 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1496 # Occupied blocks per task id
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-system.cpu.l2cache.ReadCleanReq_hits::total 54 # number of ReadCleanReq hits
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-system.cpu.l2cache.ReadSharedReq_hits::total 11509702 # number of ReadSharedReq hits
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-system.cpu.l2cache.overall_hits::cpu.data 13266344 # number of overall hits
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-system.cpu.l2cache.ReadCleanReq_misses::total 1022 # number of ReadCleanReq misses
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86581.702544 # average ReadCleanReq miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::total 96687.184020 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86581.702544 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96689.948450 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 96687.184020 # average overall miss latency
-system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.l2cache.unused_prefetches 58080 # number of HardPF blocks evicted w/o reference
-system.cpu.l2cache.writebacks::writebacks 1634268 # number of writebacks
-system.cpu.l2cache.writebacks::total 1634268 # number of writebacks
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-system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
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-system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45595 # number of ReadSharedReq MSHR hits
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-system.cpu.l2cache.demand_mshr_hits::cpu.data 49537 # number of demand (read+write) MSHR hits
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-system.cpu.l2cache.ReadExReq_mshr_misses::total 977021 # number of ReadExReq MSHR misses
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-system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1021 # number of ReadCleanReq MSHR misses
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-system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709403 # number of ReadSharedReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 137500 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98257390500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98257390500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 82266500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 82266500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237433882500 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237433882500 # number of ReadSharedReq MSHR miss cycles
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-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335691273000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 335773539500 # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335691273000 # number of overall MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::total 420136839936 # number of overall MSHR miss cycles
-system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
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-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356889 # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.948885 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189938 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189938 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.216865 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.287383 # mshr miss rate for overall accesses
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average HardPFReq mshr miss latency
-system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70358.802876 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100568.350629 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100568.350629 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80574.436827 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80574.436827 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.283974 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.283974 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91058.589213 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85979.286956 # average overall mshr miss latency
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-system.cpu.toL2Bus.snoop_filter.hit_single_requests 17002402 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21251 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 202098 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 202097 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
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+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51006435
+system.cpu.toL2Bus.pkt_count::total 51009177
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176263168
+system.cpu.toL2Bus.pkt_size::total 2176369792
+system.cpu.toL2Bus.snoops 6143430
+system.cpu.toL2Bus.snoopTraffic 104594048
+system.cpu.toL2Bus.snoop_fanout::samples 23146806
+system.cpu.toL2Bus.snoop_fanout::mean 0.009650
+system.cpu.toL2Bus.snoop_fanout::stdev 0.097758
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 22923448 99.04% 99.04%
+system.cpu.toL2Bus.snoop_fanout::1 223357 0.96% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 23146806
+system.cpu.toL2Bus.reqLayer0.occupancy 34005271029
+system.cpu.toL2Bus.reqLayer0.utilization 4.3
+system.cpu.toL2Bus.snoopLayer0.occupancy 21045
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer0.occupancy 1613498
+system.cpu.toL2Bus.respLayer0.utilization 0.0
+system.cpu.toL2Bus.respLayer1.occupancy 25503465992
+system.cpu.toL2Bus.respLayer1.utilization 3.2
+system.membus.snoop_filter.tot_requests 9333292
+system.membus.snoop_filter.hit_single_requests 4668829
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500
+system.membus.trans_dist::ReadResp 3708542
+system.membus.trans_dist::WritebackDirty 1634268
+system.membus.trans_dist::CleanEvict 3013301
+system.membus.trans_dist::UpgradeReq 9
+system.membus.trans_dist::ReadExReq 977171
+system.membus.trans_dist::ReadExResp 977171
+system.membus.trans_dist::ReadSharedReq 3708543
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14019005
+system.membus.pkt_count::total 14019005
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404478784
+system.membus.pkt_size::total 404478784
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 4685723
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 4685723 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 4685723
+system.membus.reqLayer0.occupancy 17639856241
+system.membus.reqLayer0.utilization 2.2
+system.membus.respLayer1.occupancy 25447920698
+system.membus.respLayer1.utilization 3.2
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index 0bd2c9396..36301b9e3 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -90,6 +90,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -165,8 +166,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -177,8 +176,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -239,7 +236,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
drivers=
@@ -248,14 +245,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
@@ -279,6 +277,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -290,7 +289,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -298,6 +297,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -306,6 +312,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -313,7 +320,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
index aadc3d011..43d70058a 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index c1b3d9c87..61d98894f 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:38:22
-gem5 executing on e108600-lin, pid 23077
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 18:15:54
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 57397
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 832017490500 because target called exit()
+Exiting @ tick 832017490500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
index 2806362a5..5e4ef201f 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
@@ -1,262 +1,262 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.832017 # Number of seconds simulated
-sim_ticks 832017490500 # Number of ticks simulated
-final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2178592 # Simulator instruction rate (inst/s)
-host_op_rate 2347103 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1173553065 # Simulator tick rate (ticks/s)
-host_mem_usage 260024 # Number of bytes of host memory used
-host_seconds 708.97 # Real time elapsed on the host
-sim_insts 1544563042 # Number of instructions simulated
-sim_ops 1664032434 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory
-system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory
-system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 46 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 832017490500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 1664034982 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 1544563042 # Number of instructions committed
-system.cpu.committedOps 1664032434 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
-system.cpu.num_func_calls 27330256 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1477900422 # number of integer instructions
-system.cpu.num_fp_insts 36 # number of float instructions
-system.cpu.num_int_register_reads 2605402867 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 4992096239 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
-system.cpu.num_mem_refs 633153380 # number of memory refs
-system.cpu.num_load_insts 458306334 # Number of load instructions
-system.cpu.num_store_insts 174847046 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 1664034981.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 213462427 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
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-system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
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-system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction
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-system.cpu.op_class::total 1664032481 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 1999474725 # Transaction distribution
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-system.membus.trans_dist::SoftPFResp 1 # Transaction distribution
-system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution
-system.membus.trans_dist::StoreCondReq 61 # Transaction distribution
-system.membus.trans_dist::StoreCondResp 61 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131180 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4344121790 # Packet count per connected master and slave (bytes)
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-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 2172060895 # Request fanout histogram
+sim_seconds 0.832017
+sim_ticks 832017490500
+final_tick 832017490500
+sim_freq 1000000000000
+host_inst_rate 917891
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+system.physmem.bytes_written::cpu.data 624158392
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+system.physmem.num_reads::total 1999474787
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+system.cpu.op_class::MemRead 458306322 27.54% 89.49%
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+system.cpu.op_class::total 1664032481
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+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 2172060895 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 2172060895
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 65c2bbf99..c5f8c8ed0 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -87,6 +87,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -96,14 +97,14 @@ icache_port=system.cpu.icache.cpu_side
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -117,6 +118,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -129,15 +131,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -193,14 +196,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -214,6 +217,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -226,15 +230,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=ArmInterrupts
@@ -253,8 +258,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=17
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -265,8 +268,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -325,14 +326,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -346,6 +347,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -358,15 +360,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -402,7 +405,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=bzip2 input.source 1
cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
drivers=
@@ -411,14 +414,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/bzip2
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
@@ -442,6 +446,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -453,7 +458,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -461,6 +466,13 @@ width=16
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -469,6 +481,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -476,7 +489,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
index aadc3d011..43d70058a 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index 4382bd2ba..3fe74519c 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -3,20 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:37:41
-gem5 started Jul 21 2016 14:49:25
-gem5 executing on e108600-lin, pid 23292
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 17:57:50
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 54313
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2377029670500 because target called exit()
+Exiting @ tick 2379921906500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
index 11790cc5e..fd3a8134b 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
@@ -1,682 +1,682 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.379922 # Number of seconds simulated
-sim_ticks 2379921906500 # Number of ticks simulated
-final_tick 2379921906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1526036 # Simulator instruction rate (inst/s)
-host_op_rate 1644518 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2360243305 # Simulator tick rate (ticks/s)
-host_mem_usage 271808 # Number of bytes of host memory used
-host_seconds 1008.34 # Real time elapsed on the host
-sim_insts 1538759602 # Number of instructions simulated
-sim_ops 1658228915 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 126077056 # Number of bytes read from this memory
-system.physmem.bytes_read::total 126116480 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 66029376 # Number of bytes written to this memory
-system.physmem.bytes_written::total 66029376 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1969954 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1970570 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1031709 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1031709 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 16565 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 52975291 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 52991856 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 16565 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 16565 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 27744346 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 27744346 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 27744346 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 16565 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 52975291 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 80736202 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 46 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 4759843813 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 1538759602 # Number of instructions committed
-system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
-system.cpu.num_func_calls 27330256 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
-system.cpu.num_int_insts 1477900422 # number of integer instructions
-system.cpu.num_fp_insts 36 # number of float instructions
-system.cpu.num_int_register_reads 2601860297 # number of times the integer registers were read
-system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 6356387678 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
-system.cpu.num_mem_refs 633153380 # number of memory refs
-system.cpu.num_load_insts 458306334 # Number of load instructions
-system.cpu.num_store_insts 174847046 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 4759843812.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 213462427 # Number of branches fetched
-system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 1030178776 61.91% 61.91% # Class of executed instruction
-system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
-system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
-system.cpu.op_class::MemRead 458306322 27.54% 89.49% # Class of executed instruction
-system.cpu.op_class::MemWrite 174847022 10.51% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 12 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 24 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 1664032481 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 9111140 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4083.747199 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 25232837500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4083.747199 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.997009 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.997009 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 1149 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2648 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 147 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits
-system.cpu.dcache.overall_hits::total 618379947 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
-system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
-system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 152766688500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 152766688500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 64243803000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 64243803000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 217010491500 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 217010491500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 217010491500 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 217010491500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21141.000605 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 21141.000605 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34006.742189 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 34006.742189 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 23807.448903 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 23807.448903 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 23807.446291 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 23807.446291 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 3667054 # number of writebacks
-system.cpu.dcache.writebacks::total 3667054 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 145540602500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 145540602500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62354654000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 62354654000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 207895256500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 207895256500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 207895318500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 207895318500 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20141.000605 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 20141.000605 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33006.742189 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33006.742189 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22807.448903 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22807.448903 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22807.453203 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22807.453203 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 7 # number of replacements
-system.cpu.icache.tags.tagsinuse 515.169434 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 1544564953 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 2420948.202194 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 515.169434 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.251548 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.251548 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 3089131820 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 3089131820 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 2379921906500 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 1544564953 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 1544564953 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 1544564953 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 1544564953 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 1544564953 # number of overall hits
-system.cpu.icache.overall_hits::total 1544564953 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
-system.cpu.icache.overall_misses::total 638 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 39132000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 39132000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 39132000 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 39132000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 39132000 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 39132000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 1544565591 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 1544565591 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 1544565591 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 1544565591 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 1544565591 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 1544565591 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61335.423197 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 61335.423197 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 61335.423197 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 61335.423197 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 61335.423197 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 7 # number of writebacks
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-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60335.423197 # average overall mshr miss latency
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-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2874 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1739 # Occupied blocks per task id
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.083155 # average ReadExReq miss latency
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-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60521.103896 # average ReadCleanReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60521.103896 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60506.976051 # average overall miss latency
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-system.cpu.l2cache.writebacks::total 1031709 # number of writebacks
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-system.cpu.l2cache.CleanEvict_mshr_misses::total 220 # number of CleanEvict MSHR misses
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-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 59414705500 # number of ReadSharedReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 99496419500 # number of overall MSHR miss cycles
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-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50521.103896 # average ReadCleanReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50506.976051 # average overall mshr miss latency
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-system.cpu.toL2Bus.snoop_filter.tot_snoops 1220 # Total number of snoops made to the snoop filter.
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-system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadSharedReq 7226087 # Transaction distribution
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-system.cpu.toL2Bus.reqLayer0.occupancy 12780571500 # Layer occupancy (ticks)
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+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 11051609 99.98% 99.98%
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+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00%
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+system.cpu.toL2Bus.respLayer1.utilization 0.6
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+system.membus.snoop_filter.tot_snoops 0
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+system.membus.trans_dist::ReadExReq 793696
+system.membus.trans_dist::ReadExResp 793696
+system.membus.trans_dist::ReadSharedReq 1176874
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878253
+system.membus.pkt_count::total 5878253
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+system.membus.pkt_size::total 192145856
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1970570
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1970570 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1970570
+system.membus.reqLayer0.occupancy 8048170000
+system.membus.reqLayer0.utilization 0.3
+system.membus.respLayer1.occupancy 9852850000
+system.membus.respLayer1.utilization 0.4
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 3f64cee84..2dc49338c 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=atomic
@@ -88,6 +89,7 @@ simulate_data_stalls=false
simulate_inst_stalls=false
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
width=1
@@ -167,7 +169,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=bzip2 input.source 1
cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
drivers=
@@ -176,14 +178,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
@@ -207,6 +210,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -218,7 +222,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -226,6 +230,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -234,6 +245,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -241,7 +253,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
index aadc3d011..43d70058a 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index 715860400..c93c64d50 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:17
-gem5 executing on e108600-lin, pid 18539
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:06:24
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87211
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 2846007227500 because target called exit()
+Exiting @ tick 2846007227500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
index 213b5c5af..3d3e0703d 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
@@ -1,145 +1,145 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.846007 # Number of seconds simulated
-sim_ticks 2846007227500 # Number of ticks simulated
-final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1654731 # Simulator instruction rate (inst/s)
-host_op_rate 2578221 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1565575242 # Simulator tick rate (ticks/s)
-host_mem_usage 262288 # Number of bytes of host memory used
-host_seconds 1817.87 # Real time elapsed on the host
-sim_insts 3008081022 # Number of instructions simulated
-sim_ops 4686862596 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory
-system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 32105863056 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 32105863056 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::cpu.data 1544656792 # Number of bytes written to this memory
-system.physmem.bytes_written::total 1544656792 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 4013232882 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1239184746 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 5252417628 # Number of read requests responded to by this memory
-system.physmem.num_writes::cpu.data 438528338 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 438528338 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 11281019509 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1765233867 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 13046253376 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 11281019509 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 11281019509 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 542745211 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 542745211 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 46 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 2846007227500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 5692014456 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 3008081022 # Number of instructions committed
-system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 33534539 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4684368009 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
-system.cpu.num_mem_refs 1677713084 # number of memory refs
-system.cpu.num_load_insts 1239184746 # Number of load instructions
-system.cpu.num_store_insts 438528338 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 5692014455.998000 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 248500691 # Number of branches fetched
-system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
-system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
-system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
-system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 4686862596 # Class of executed instruction
-system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
-system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
-system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
-system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 5690945966 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
+sim_seconds 2.846007
+sim_ticks 2846007227500
+final_tick 2846007227500
+sim_freq 1000000000000
+host_inst_rate 877028
+host_op_rate 1366490
+host_tick_rate 829774485
+host_mem_usage 274188
+host_seconds 3429.86
+sim_insts 3008081022
+sim_ops 4686862596
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.physmem.pwrStateResidencyTicks::UNDEFINED 2846007227500
+system.physmem.bytes_read::cpu.inst 32105863056
+system.physmem.bytes_read::cpu.data 5023868345
+system.physmem.bytes_read::total 37129731401
+system.physmem.bytes_inst_read::cpu.inst 32105863056
+system.physmem.bytes_inst_read::total 32105863056
+system.physmem.bytes_written::cpu.data 1544656792
+system.physmem.bytes_written::total 1544656792
+system.physmem.num_reads::cpu.inst 4013232882
+system.physmem.num_reads::cpu.data 1239184746
+system.physmem.num_reads::total 5252417628
+system.physmem.num_writes::cpu.data 438528338
+system.physmem.num_writes::total 438528338
+system.physmem.bw_read::cpu.inst 11281019509
+system.physmem.bw_read::cpu.data 1765233867
+system.physmem.bw_read::total 13046253376
+system.physmem.bw_inst_read::cpu.inst 11281019509
+system.physmem.bw_inst_read::total 11281019509
+system.physmem.bw_write::cpu.data 542745211
+system.physmem.bw_write::total 542745211
+system.physmem.bw_total::cpu.inst 11281019509
+system.physmem.bw_total::cpu.data 2307979078
+system.physmem.bw_total::total 13588998587
+system.pwrStateResidencyTicks::UNDEFINED 2846007227500
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500
+system.cpu.apic_clk_domain.clock 8000
+system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 2846007227500
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2846007227500
+system.cpu.workload.numSyscalls 46
+system.cpu.pwrStateResidencyTicks::ON 2846007227500
+system.cpu.numCycles 5692014456
+system.cpu.numWorkItemsStarted 0
+system.cpu.numWorkItemsCompleted 0
+system.cpu.committedInsts 3008081022
+system.cpu.committedOps 4686862596
+system.cpu.num_int_alu_accesses 4684368009
+system.cpu.num_fp_alu_accesses 0
+system.cpu.num_func_calls 33534539
+system.cpu.num_conditional_control_insts 182173300
+system.cpu.num_int_insts 4684368009
+system.cpu.num_fp_insts 0
+system.cpu.num_int_register_reads 10688755601
+system.cpu.num_int_register_writes 3999841477
+system.cpu.num_fp_register_reads 0
+system.cpu.num_fp_register_writes 0
+system.cpu.num_cc_register_reads 1226718827
+system.cpu.num_cc_register_writes 1355930461
+system.cpu.num_mem_refs 1677713084
+system.cpu.num_load_insts 1239184746
+system.cpu.num_store_insts 438528338
+system.cpu.num_idle_cycles 0
+system.cpu.num_busy_cycles 5692014456
+system.cpu.not_idle_fraction 1
+system.cpu.idle_fraction 0
+system.cpu.Branches 248500691
+system.cpu.op_class::No_OpClass 2494522 0.05% 0.05%
+system.cpu.op_class::IntAlu 3006647871 64.15% 64.20%
+system.cpu.op_class::IntMult 6215 0.00% 64.20%
+system.cpu.op_class::IntDiv 904 0.00% 64.20%
+system.cpu.op_class::FloatAdd 0 0.00% 64.20%
+system.cpu.op_class::FloatCmp 0 0.00% 64.20%
+system.cpu.op_class::FloatCvt 0 0.00% 64.20%
+system.cpu.op_class::FloatMult 0 0.00% 64.20%
+system.cpu.op_class::FloatMultAcc 0 0.00% 64.20%
+system.cpu.op_class::FloatDiv 0 0.00% 64.20%
+system.cpu.op_class::FloatMisc 0 0.00% 64.20%
+system.cpu.op_class::FloatSqrt 0 0.00% 64.20%
+system.cpu.op_class::SimdAdd 0 0.00% 64.20%
+system.cpu.op_class::SimdAddAcc 0 0.00% 64.20%
+system.cpu.op_class::SimdAlu 0 0.00% 64.20%
+system.cpu.op_class::SimdCmp 0 0.00% 64.20%
+system.cpu.op_class::SimdCvt 0 0.00% 64.20%
+system.cpu.op_class::SimdMisc 0 0.00% 64.20%
+system.cpu.op_class::SimdMult 0 0.00% 64.20%
+system.cpu.op_class::SimdMultAcc 0 0.00% 64.20%
+system.cpu.op_class::SimdShift 0 0.00% 64.20%
+system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20%
+system.cpu.op_class::SimdSqrt 0 0.00% 64.20%
+system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20%
+system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20%
+system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20%
+system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20%
+system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20%
+system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20%
+system.cpu.op_class::SimdFloatMult 0 0.00% 64.20%
+system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20%
+system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20%
+system.cpu.op_class::MemRead 1239184746 26.44% 90.64%
+system.cpu.op_class::MemWrite 438528338 9.36% 100.00%
+system.cpu.op_class::FloatMemRead 0 0.00% 100.00%
+system.cpu.op_class::FloatMemWrite 0 0.00% 100.00%
+system.cpu.op_class::IprAccess 0 0.00% 100.00%
+system.cpu.op_class::InstPrefetch 0 0.00% 100.00%
+system.cpu.op_class::total 4686862596
+system.membus.snoop_filter.tot_requests 0
+system.membus.snoop_filter.hit_single_requests 0
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 2846007227500
+system.membus.trans_dist::ReadReq 5252417628
+system.membus.trans_dist::ReadResp 5252417628
+system.membus.trans_dist::WriteReq 438528338
+system.membus.trans_dist::WriteResp 438528338
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764
+system.membus.pkt_count_system.cpu.icache_port::total 8026465764
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168
+system.membus.pkt_count_system.cpu.dcache_port::total 3355426168
+system.membus.pkt_count::total 11381891932
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056
+system.membus.pkt_size_system.cpu.icache_port::total 32105863056
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137
+system.membus.pkt_size_system.cpu.dcache_port::total 6568525137
+system.membus.pkt_size::total 38674388193
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 5690945966
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 5690945966 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 5690945966
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index 1048d999e..136c4396f 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -20,6 +20,7 @@ exit_on_work_items=false
init_param=0
kernel=
kernel_addr_check=true
+kvm_vm=Null
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
@@ -85,6 +86,7 @@ progress_interval=0
simpoint_start_insts=
socket_id=0
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
workload=system.cpu.workload
@@ -100,14 +102,14 @@ eventq_index=0
[system.cpu.dcache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
@@ -121,6 +123,7 @@ response_latency=2
sequential_access=false
size=262144
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=20
write_buffers=8
@@ -133,15 +136,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=262144
+tag_latency=2
[system.cpu.dtb]
type=X86TLB
@@ -166,14 +170,14 @@ port=system.cpu.toL2Bus.slave[3]
[system.cpu.icache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
@@ -187,6 +191,7 @@ response_latency=2
sequential_access=false
size=131072
system=system
+tag_latency=2
tags=system.cpu.icache.tags
tgts_per_mshr=20
write_buffers=8
@@ -199,15 +204,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=131072
+tag_latency=2
[system.cpu.interrupts]
type=X86LocalApic
@@ -253,14 +259,14 @@ port=system.cpu.toL2Bus.slave[2]
[system.cpu.l2cache]
type=Cache
children=tags
-addr_ranges=0:18446744073709551615
+addr_ranges=0:18446744073709551615:0:0:0:0
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=20
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
@@ -274,6 +280,7 @@ response_latency=20
sequential_access=false
size=2097152
system=system
+tag_latency=20
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
write_buffers=8
@@ -286,15 +293,16 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=20
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=20
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=2097152
+tag_latency=20
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -330,7 +338,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=bzip2 input.source 1
cwd=build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
drivers=
@@ -339,14 +347,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/x86/linux/bzip2
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/bzip2
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
@@ -370,6 +379,7 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
+children=snoop_filter
clk_domain=system.clk_domain
default_p_state=UNDEFINED
eventq_index=0
@@ -381,7 +391,7 @@ p_state_clk_gate_min=1000
point_of_coherency=true
power_model=Null
response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
snoop_response_latency=4
system=system
use_default_range=false
@@ -389,6 +399,13 @@ width=16
master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave
slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000
@@ -397,6 +414,7 @@ conf_table_reported=true
default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
+kvm_map=true
latency=30000
latency_var=0
null=false
@@ -404,7 +422,7 @@ p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
-range=0:134217727
+range=0:134217727:0:0:0:0
port=system.membus.master[0]
[system.voltage_domain]
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
index aadc3d011..43d70058a 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
@@ -1,2 +1,6 @@
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 0337bc6ef..f2fd8c974 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -3,20 +3,16 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 21 2016 14:35:23
-gem5 started Jul 21 2016 14:36:20
-gem5 executing on e108600-lin, pid 18569
-command line: /work/curdun01/gem5-external.hg/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing
+gem5 compiled Apr 3 2017 19:05:53
+gem5 started Apr 3 2017 19:06:21
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87163
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
@@ -27,4 +23,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
-Exiting @ tick 5895947852500 because target called exit()
+Exiting @ tick 5898831348500 because exiting with last active thread context
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
index 4f06487d9..01185a8e0 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
@@ -1,541 +1,541 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.898831 # Number of seconds simulated
-sim_ticks 5898831348500 # Number of ticks simulated
-final_tick 5898831348500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1175665 # Simulator instruction rate (inst/s)
-host_op_rate 1831792 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2305472192 # Simulator tick rate (ticks/s)
-host_mem_usage 275096 # Number of bytes of host memory used
-host_seconds 2558.62 # Real time elapsed on the host
-sim_insts 3008081022 # Number of instructions simulated
-sim_ops 4686862596 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 126068992 # Number of bytes read from this memory
-system.physmem.bytes_read::total 126112192 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 43200 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 43200 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 66108032 # Number of bytes written to this memory
-system.physmem.bytes_written::total 66108032 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 675 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 1969828 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1970503 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1032938 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1032938 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7323 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 21371859 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 21379183 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7323 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7323 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 11206971 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 11206971 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 11206971 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7323 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 21371859 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 32586154 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
-system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
-system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
-system.cpu.workload.numSyscalls 46 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 5898831348500 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 11797662697 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 3008081022 # Number of instructions committed
-system.cpu.committedOps 4686862596 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 4684368009 # Number of integer alu accesses
-system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
-system.cpu.num_func_calls 33534539 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 182173300 # number of instructions that are conditional controls
-system.cpu.num_int_insts 4684368009 # number of integer instructions
-system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 10688755601 # number of times the integer registers were read
-system.cpu.num_int_register_writes 3999841477 # number of times the integer registers were written
-system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
-system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 1226718827 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 1355930461 # number of times the CC registers were written
-system.cpu.num_mem_refs 1677713084 # number of memory refs
-system.cpu.num_load_insts 1239184746 # Number of load instructions
-system.cpu.num_store_insts 438528338 # Number of store instructions
-system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu.num_busy_cycles 11797662696.997999 # Number of busy cycles
-system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu.Branches 248500691 # Number of branches fetched
-system.cpu.op_class::No_OpClass 2494522 0.05% 0.05% # Class of executed instruction
-system.cpu.op_class::IntAlu 3006647871 64.15% 64.20% # Class of executed instruction
-system.cpu.op_class::IntMult 6215 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::IntDiv 904 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatCvt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatMult 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatMultAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatDiv 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatMisc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::FloatSqrt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdAdd 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdAddAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdAlu 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdCmp 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdCvt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdMisc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdMult 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdMultAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdShift 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdShiftAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdSqrt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatAdd 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatAlu 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatMisc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction
-system.cpu.op_class::MemRead 1239184746 26.44% 90.64% # Class of executed instruction
-system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 4686862596 # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 9108581 # number of replacements
-system.cpu.dcache.tags.tagsinuse 4084.589706 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 58922805500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 4084.589706 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 898 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 2768 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 329 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 5898831348500 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits
-system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses
-system.cpu.dcache.overall_misses::total 9112677 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 152690255000 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 152690255000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 64265951000 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 64265951000 # number of WriteReq miss cycles
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+system.membus.pwrStateResidencyTicks::UNDEFINED 5898831348500
+system.membus.trans_dist::ReadResp 1176539
+system.membus.trans_dist::WritebackDirty 1032938
+system.membus.trans_dist::CleanEvict 904164
+system.membus.trans_dist::ReadExReq 793964
+system.membus.trans_dist::ReadExResp 793964
+system.membus.trans_dist::ReadSharedReq 1176539
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5878108
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5878108
+system.membus.pkt_count::total 5878108
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 192220224
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 192220224
+system.membus.pkt_size::total 192220224
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 1970503
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 1970503 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 1970503
+system.membus.reqLayer0.occupancy 8039359500
+system.membus.reqLayer0.utilization 0.1
+system.membus.respLayer1.occupancy 9852515000
+system.membus.respLayer1.utilization 0.2
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index 3c414751d..87b4a600e 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -141,6 +141,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -176,10 +177,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=2
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=6
@@ -193,6 +194,7 @@ response_latency=2
sequential_access=false
size=32768
system=system
+tag_latency=2
tags=system.cpu.dcache.tags
tgts_per_mshr=8
write_buffers=16
@@ -205,15 +207,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=2
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=2
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=2
[system.cpu.dstage2_mmu]
type=ArmStage2MMU
@@ -316,38 +319,52 @@ pipelined=true
[system.cpu.fuPool.FUList2]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList2.opList
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1
-[system.cpu.fuPool.FUList2.opList]
+[system.cpu.fuPool.FUList2.opList0]
type=OpDesc
eventq_index=0
opClass=MemRead
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemRead
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList3]
type=FUDesc
-children=opList
+children=opList0 opList1
count=1
eventq_index=0
-opList=system.cpu.fuPool.FUList3.opList
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1
-[system.cpu.fuPool.FUList3.opList]
+[system.cpu.fuPool.FUList3.opList0]
type=OpDesc
eventq_index=0
opClass=MemWrite
opLat=2
pipelined=true
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+eventq_index=0
+opClass=FloatMemWrite
+opLat=2
+pipelined=true
+
[system.cpu.fuPool.FUList4]
type=FUDesc
-children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25
+children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27
count=2
eventq_index=0
-opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25
+opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27
[system.cpu.fuPool.FUList4.opList00]
type=OpDesc
@@ -479,7 +496,7 @@ pipelined=true
type=OpDesc
eventq_index=0
opClass=SimdFloatMultAcc
-opLat=1
+opLat=5
pipelined=true
[system.cpu.fuPool.FUList4.opList19]
@@ -531,6 +548,20 @@ opClass=FloatMult
opLat=4
pipelined=true
+[system.cpu.fuPool.FUList4.opList26]
+type=OpDesc
+eventq_index=0
+opClass=FloatMultAcc
+opLat=5
+pipelined=true
+
+[system.cpu.fuPool.FUList4.opList27]
+type=OpDesc
+eventq_index=0
+opClass=FloatMisc
+opLat=3
+pipelined=true
+
[system.cpu.icache]
type=Cache
children=tags
@@ -538,10 +569,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+data_latency=1
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=1
is_read_only=true
max_miss_count=0
mshrs=2
@@ -555,6 +586,7 @@ response_latency=1
sequential_access=false
size=32768
system=system
+tag_latency=1
tags=system.cpu.icache.tags
tgts_per_mshr=8
write_buffers=8
@@ -567,15 +599,16 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=1
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=1
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=32768
+tag_latency=1
[system.cpu.interrupts]
type=ArmInterrupts
@@ -594,8 +627,6 @@ id_aa64isar0_el1=0
id_aa64isar1_el1=0
id_aa64mmfr0_el1=15728642
id_aa64mmfr1_el1=0
-id_aa64pfr0_el1=34
-id_aa64pfr1_el1=0
id_isar0=34607377
id_isar1=34677009
id_isar2=555950401
@@ -606,8 +637,6 @@ id_mmfr0=270536963
id_mmfr1=0
id_mmfr2=19070976
id_mmfr3=34611729
-id_pfr0=49
-id_pfr1=4113
midr=1091551472
pmu=Null
system=system
@@ -670,10 +699,10 @@ addr_ranges=0:18446744073709551615:0:0:0:0
assoc=16
clk_domain=system.cpu_clk_domain
clusivity=mostly_excl
+data_latency=12
default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
-hit_latency=12
is_read_only=false
max_miss_count=0
mshrs=16
@@ -687,6 +716,7 @@ response_latency=12
sequential_access=false
size=1048576
system=system
+tag_latency=12
tags=system.cpu.l2cache.tags
tgts_per_mshr=8
write_buffers=8
@@ -729,15 +759,16 @@ type=RandomRepl
assoc=16
block_size=64
clk_domain=system.cpu_clk_domain
+data_latency=12
default_p_state=UNDEFINED
eventq_index=0
-hit_latency=12
p_state_clk_gate_bins=20
p_state_clk_gate_max=1000000000000
p_state_clk_gate_min=1000
power_model=Null
sequential_access=false
size=1048576
+tag_latency=12
[system.cpu.toL2Bus]
type=CoherentXBar
@@ -773,7 +804,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload]
-type=LiveProcess
+type=Process
cmd=twolf smred
cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
drivers=
@@ -782,14 +813,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/twolf
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
kvmInSE=false
-max_stack_size=67108864
+maxStackSize=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
index bbcd9d751..9acbe6def 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
@@ -1,3 +1,5 @@
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (128 Mbytes)
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 8c06d056d..0119254bf 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -3,21 +3,19 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 11 2016 00:00:58
-gem5 started Oct 13 2016 20:43:01
-gem5 executing on e108600-lin, pid 17342
-command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing
+gem5 compiled Apr 3 2017 17:55:48
+gem5 started Apr 3 2017 18:24:01
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 59389
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/70.twolf/arm/linux/o3-timing
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
-info: Increasing stack size by one page.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
@@ -26,4 +24,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 86053034000 because target called exit()
+122 123 124 Exiting @ tick 85986203000 because exiting with last active thread context
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
index 1ab6131a6..407dc44a0 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
@@ -1,1233 +1,1233 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.085986 # Number of seconds simulated
-sim_ticks 85986203000 # Number of ticks simulated
-final_tick 85986203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 210936 # Simulator instruction rate (inst/s)
-host_op_rate 222361 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 105265513 # Simulator tick rate (ticks/s)
-host_mem_usage 272504 # Number of bytes of host memory used
-host_seconds 816.85 # Real time elapsed on the host
-sim_insts 172303022 # Number of instructions simulated
-sim_ops 181635954 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 651776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 193408 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.l2cache.prefetcher 71680 # Number of bytes read from this memory
-system.physmem.bytes_read::total 916864 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 651776 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 651776 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 10184 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 3022 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.l2cache.prefetcher 1120 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 14326 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 7580007 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2249291 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 833622 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 10662920 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 7580007 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 7580007 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 7580007 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2249291 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 833622 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 10662920 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 14327 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 14327 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 916928 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 916928 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 1379 # Per bank write bursts
-system.physmem.perBankRdBursts::1 501 # Per bank write bursts
-system.physmem.perBankRdBursts::2 5100 # Per bank write bursts
-system.physmem.perBankRdBursts::3 815 # Per bank write bursts
-system.physmem.perBankRdBursts::4 2265 # Per bank write bursts
-system.physmem.perBankRdBursts::5 427 # Per bank write bursts
-system.physmem.perBankRdBursts::6 394 # Per bank write bursts
-system.physmem.perBankRdBursts::7 623 # Per bank write bursts
-system.physmem.perBankRdBursts::8 270 # Per bank write bursts
-system.physmem.perBankRdBursts::9 230 # Per bank write bursts
-system.physmem.perBankRdBursts::10 354 # Per bank write bursts
-system.physmem.perBankRdBursts::11 345 # Per bank write bursts
-system.physmem.perBankRdBursts::12 321 # Per bank write bursts
-system.physmem.perBankRdBursts::13 266 # Per bank write bursts
-system.physmem.perBankRdBursts::14 239 # Per bank write bursts
-system.physmem.perBankRdBursts::15 798 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 85986194000 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 14327 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 12781 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 1074 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 181 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 85 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 31 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 8483 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 107.969350 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 86.508882 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 122.734500 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 5897 69.52% 69.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 2092 24.66% 94.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 251 2.96% 97.14% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 65 0.77% 97.90% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 38 0.45% 98.35% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 36 0.42% 98.77% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 15 0.18% 98.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 8483 # Bytes accessed per row activation
-system.physmem.totQLat 1497477800 # Total ticks spent queuing
-system.physmem.totMemAccLat 1766109050 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 71635000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 104521.38 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 123271.38 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 10.66 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 10.66 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.08 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.08 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 5838 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 6001688.70 # Average gap between requests
-system.physmem.pageHitRate 40.75 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 51557940 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 27392310 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 82138560 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 5188176240.000001 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1121049780 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 275286240 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 12230933460 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 8389841280 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 9251896980 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 36621408690 # Total energy per rank (pJ)
-system.physmem_0.averagePower 425.898657 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 82802255264 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 532741000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 2206324000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 34133171250 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 21848572364 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 443169236 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 26822225150 # Time in different power states
-system.physmem_1.actEnergy 9046380 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 4800675 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 20149080 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 880164480.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 198118890 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 50592480 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 1982659500 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 1381296480 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 18795083175 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 23322152130 # Total energy per rank (pJ)
-system.physmem_1.averagePower 271.231327 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 85419499755 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 100592000 # Time in different power states
-system.physmem_1.memoryStateTime::REF 374546000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 77474388250 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 3597111150 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 91565245 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 4348000355 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 85644201 # Number of BP lookups
-system.cpu.branchPred.condPredicted 68263451 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 5948841 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 39900262 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 38156956 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 95.630841 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 3658994 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 81907 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 654149 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 629298 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 24851 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 40566 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.dtb.walker.walks 0 # Table walker walks requested
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.inst_hits 0 # ITB inst hits
-system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 0 # DTB read hits
-system.cpu.dtb.read_misses 0 # DTB read misses
-system.cpu.dtb.write_hits 0 # DTB write hits
-system.cpu.dtb.write_misses 0 # DTB write misses
-system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 0 # DTB read accesses
-system.cpu.dtb.write_accesses 0 # DTB write accesses
-system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 0 # DTB hits
-system.cpu.dtb.misses 0 # DTB misses
-system.cpu.dtb.accesses 0 # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
-system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
-system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
-system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
-system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
-system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
-system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
-system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
-system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
-system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
-system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.itb.walker.walks 0 # Table walker walks requested
-system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 0 # ITB inst hits
-system.cpu.itb.inst_misses 0 # ITB inst misses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
-system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
-system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
-system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 0 # ITB inst accesses
-system.cpu.itb.hits 0 # DTB hits
-system.cpu.itb.misses 0 # DTB misses
-system.cpu.itb.accesses 0 # DTB accesses
-system.cpu.workload.numSyscalls 400 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 171972407 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 5684699 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 346733793 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 85644201 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 42445248 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 158074641 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 11911485 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 4331 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingQuiesceStallCycles 80 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 4750 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 78152122 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 17905 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 169724243 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.137034 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 1.057596 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 18311667 10.79% 10.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 29948653 17.65% 28.43% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 31633861 18.64% 47.07% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 89830062 52.93% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 169724243 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.498011 # Number of branch fetches per cycle
-system.cpu.fetch.rate 2.016218 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 17545924 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 18077628 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 121579812 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 6764631 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 5756248 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 32661376 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 214759 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 304427843 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 27289068 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 5756248 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 37507593 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 8946109 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 602389 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 108088153 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 8823751 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 276998119 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 13097154 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 3089202 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 850461 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 2596711 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 40764 # Number of times rename has blocked due to SQ full
-system.cpu.rename.FullRegisterEvents 26854 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 480912034 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1185877305 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 296009785 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 3004340 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 187935105 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 23572 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 23567 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13428642 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 33801265 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 14384966 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 2539582 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1819756 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 263460878 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 45929 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 214221426 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 5142742 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 81870853 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 215931448 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 713 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 169724243 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.262173 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.018049 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 53012533 31.23% 31.23% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 36041444 21.24% 52.47% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 65469642 38.57% 91.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 13608265 8.02% 99.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 1546158 0.91% 99.97% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 45935 0.03% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 266 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 169724243 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 35637562 66.14% 66.14% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 153239 0.28% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 1065 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.43% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 35742 0.07% 66.49% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 263 0.00% 66.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 559 0.00% 66.50% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 40182 0.07% 66.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.57% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 13886588 25.77% 92.34% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3846845 7.14% 99.48% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 141772 0.26% 99.75% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 136229 0.25% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 166877725 77.90% 77.90% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 919560 0.43% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.33% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.34% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 165187 0.08% 78.42% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 245719 0.11% 78.54% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.57% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 460300 0.21% 78.79% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 206641 0.10% 78.88% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.92% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 318 0.00% 78.92% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 31220842 14.57% 93.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 13220710 6.17% 99.66% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 576371 0.27% 99.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 147395 0.07% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 214221426 # Type of FU issued
-system.cpu.iq.rate 1.245673 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 53880251 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.251517 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 653198075 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 343375917 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 204156399 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 3992013 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 2008700 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 1806249 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 265928183 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 2173494 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1586831 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 5905121 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6947 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 7000 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1740332 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 25012 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 810 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 5756248 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 5611049 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 173372 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 263527171 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 33801265 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 14384966 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 23521 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 3789 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 166382 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 7000 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 3130012 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 3255540 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 6385552 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 206995589 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 30591856 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 7225837 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 20364 # number of nop insts executed
-system.cpu.iew.exec_refs 43730352 # number of memory reference insts executed
-system.cpu.iew.exec_branches 44853428 # Number of branches executed
-system.cpu.iew.exec_stores 13138496 # Number of stores executed
-system.cpu.iew.exec_rate 1.203656 # Inst execution rate
-system.cpu.iew.wb_sent 206269583 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 205962648 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 129302452 # num instructions producing a value
-system.cpu.iew.wb_consumers 221536410 # num instructions consuming a value
-system.cpu.iew.wb_rate 1.197649 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.583662 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 68402964 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 5749347 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 158452610 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.146402 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.651768 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 73893836 46.63% 46.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 41104048 25.94% 72.58% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 22555911 14.24% 86.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 9496527 5.99% 92.80% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 3557786 2.25% 95.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 2129951 1.34% 96.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1320929 0.83% 97.23% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 1010558 0.64% 97.86% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 3383064 2.14% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 158452610 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 172317410 # Number of instructions committed
-system.cpu.commit.committedOps 181650342 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 40540778 # Number of memory references committed
-system.cpu.commit.loads 27896144 # Number of loads committed
-system.cpu.commit.membars 22408 # Number of memory barriers committed
-system.cpu.commit.branches 40300312 # Number of branches committed
-system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 143085667 # Number of committed integer instructions.
-system.cpu.commit.function_calls 1848934 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 138987813 76.51% 76.51% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 908940 0.50% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 77.01% # Class of committed instruction
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-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 77.01% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 32754 0.02% 77.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 77.03% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 154829 0.09% 77.12% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 238880 0.13% 77.25% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 76016 0.04% 77.29% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 437591 0.24% 77.53% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 200806 0.11% 77.64% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 71617 0.04% 77.68% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 318 0.00% 77.68% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 27348059 15.06% 92.74% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 12498388 6.88% 99.62% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 548085 0.30% 99.92% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 146246 0.08% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 181650342 # Class of committed instruction
-system.cpu.commit.bw_lim_events 3383064 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 405117651 # The number of ROB reads
-system.cpu.rob.rob_writes 511394543 # The number of ROB writes
-system.cpu.timesIdled 9924 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 2248164 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 172303022 # Number of Instructions Simulated
-system.cpu.committedOps 181635954 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 0.998081 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.998081 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.001922 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.001922 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 218599432 # number of integer regfile reads
-system.cpu.int_regfile_writes 114087616 # number of integer regfile writes
-system.cpu.fp_regfile_reads 2903991 # number of floating regfile reads
-system.cpu.fp_regfile_writes 2441715 # number of floating regfile writes
-system.cpu.cc_regfile_reads 707769294 # number of cc regfile reads
-system.cpu.cc_regfile_writes 229397390 # number of cc regfile writes
-system.cpu.misc_regfile_reads 57427586 # number of misc regfile reads
-system.cpu.misc_regfile_writes 820036 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements 72391 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.400200 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40997604 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 72903 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 562.358257 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 554902500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.400200 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.998829 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.998829 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 230 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 44 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 82292817 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 82292817 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 28611296 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 28611296 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 12341384 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 12341384 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 362 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 362 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 22154 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 22154 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 40952680 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 40952680 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 40953042 # number of overall hits
-system.cpu.dcache.overall_hits::total 40953042 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 89081 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 89081 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 22903 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 22903 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 117 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 117 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 253 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 253 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::cpu.data 111984 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 111984 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 112101 # number of overall misses
-system.cpu.dcache.overall_misses::total 112101 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 1981259500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 1981259500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 246570499 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 246570499 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2257000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 2257000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 2227829999 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 2227829999 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 2227829999 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 2227829999 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 28700377 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 28700377 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 41064664 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 41064664 # number of demand (read+write) accesses
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-system.cpu.dcache.overall_accesses::total 41065143 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003104 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.003104 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001852 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.001852 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.244259 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.244259 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011291 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011291 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.002727 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.002727 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.002730 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.002730 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22241.100796 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 22241.100796 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10765.860324 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 10765.860324 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8920.948617 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8920.948617 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 19894.181303 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 19894.181303 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 19873.417713 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 19873.417713 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 180 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 11209 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 865 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 90 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets 12.958382 # average number of cycles each access was blocked
-system.cpu.dcache.writebacks::writebacks 72391 # number of writebacks
-system.cpu.dcache.writebacks::total 72391 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24849 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 24849 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14345 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 14345 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 253 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 253 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 39194 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 39194 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 39194 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 39194 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64232 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 64232 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8558 # number of WriteReq MSHR misses
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-system.cpu.dcache.demand_mshr_misses::total 72790 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 72904 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency::total 1056234000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 88380499 # number of WriteReq MSHR miss cycles
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-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 977000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 1144614499 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 1144614499 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 1145591499 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 1145591499 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002238 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000692 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000692 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.237996 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.237996 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001773 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.001773 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001775 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.001775 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16444.046581 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16444.046581 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10327.237556 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 10327.237556 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8570.175439 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8570.175439 # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15724.886647 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 15724.886647 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15713.698823 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 15713.698823 # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.tags.replacements 53106 # number of replacements
-system.cpu.icache.tags.tagsinuse 510.578015 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 78094905 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 53618 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 1456.505371 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 85215430500 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.578015 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.997223 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.997223 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 276 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::4 49 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 156357779 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 156357779 # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.icache.ReadReq_hits::cpu.inst 78094905 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 78094905 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 78094905 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 57175 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 57175 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 57175 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 57175 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 57175 # number of overall misses
-system.cpu.icache.overall_misses::total 57175 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 2239186435 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 2239186435 # number of ReadReq miss cycles
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-system.cpu.icache.demand_miss_latency::total 2239186435 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 2239186435 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 2239186435 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 78152080 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 78152080 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 78152080 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 78152080 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 78152080 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_miss_rate::total 0.000732 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::total 0.000732 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.000732 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.000732 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39163.733013 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 39163.733013 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 39163.733013 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 39163.733013 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 39163.733013 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 91615 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 88 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 29.176752 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets 29.333333 # average number of cycles each access was blocked
-system.cpu.icache.writebacks::writebacks 53106 # number of writebacks
-system.cpu.icache.writebacks::total 53106 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3554 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 3554 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 3554 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 3554 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 3554 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 3554 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 53621 # number of ReadReq MSHR misses
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-system.cpu.icache.demand_mshr_miss_latency::total 2047106952 # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38177.336342 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 38177.336342 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38177.336342 # average overall mshr miss latency
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-system.cpu.l2cache.prefetcher.pfIdentified 9132 # number of prefetch candidates identified
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-system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
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-system.cpu.l2cache.prefetcher.pfSpanPage 1308 # number of prefetches not generated due to page crossing
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-system.cpu.l2cache.tags.tagsinuse 1811.625085 # Cycle average of tags in use
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-system.cpu.l2cache.tags.occ_blocks::writebacks 1727.578627 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 84.046457 # Average occupied blocks per requestor
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-system.cpu.l2cache.tags.occ_task_id_blocks::1022 138 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 2706 # Occupied blocks per task id
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-system.cpu.l2cache.tags.age_task_id_blocks_1022::2 46 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1022::4 77 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1128 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 205 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 955 # Occupied blocks per task id
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-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 189525.734081 # average overall miss latency
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-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 865 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 117896 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackDirty 64558 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 60939 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::HardPFReq 2337 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 8626 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 8626 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 53621 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 64277 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160345 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218199 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 378544 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6830336 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9298816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 16129152 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 2338 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 64 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 128862 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0.088172 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.283573 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 117501 91.18% 91.18% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 11360 8.82% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 128862 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 251508000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 80437981 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 109359491 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 14328 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 10478 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 85986203000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 14090 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 1 # Transaction distribution
-system.membus.trans_dist::ReadExReq 235 # Transaction distribution
-system.membus.trans_dist::ReadExResp 235 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 14092 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28653 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 28653 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 916800 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 14328 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 14328 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 14328 # Request fanout histogram
-system.membus.reqLayer0.occupancy 18011178 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 77254535 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
+sim_seconds 0.085986
+sim_ticks 85986203000
+final_tick 85986203000
+sim_freq 1000000000000
+host_inst_rate 102101
+host_op_rate 107631
+host_tick_rate 50952414
+host_mem_usage 284176
+host_seconds 1687.58
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+sim_ops 181635954
+system.voltage_domain.voltage 1
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+system.physmem.bytes_read::cpu.data 193408
+system.physmem.bytes_read::cpu.l2cache.prefetcher 71680
+system.physmem.bytes_read::total 916864
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+system.physmem.bytes_inst_read::total 651776
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+system.physmem.num_reads::cpu.data 3022
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+system.physmem.bw_read::cpu.data 2249291
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+system.physmem.bytesReadDRAM 916928
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+system.physmem.bytesReadSys 916928
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+system.physmem.bytesPerActivate::gmean 86.508882
+system.physmem.bytesPerActivate::stdev 122.734500
+system.physmem.bytesPerActivate::0-127 5897 69.52% 69.52%
+system.physmem.bytesPerActivate::128-255 2092 24.66% 94.18%
+system.physmem.bytesPerActivate::256-383 251 2.96% 97.14%
+system.physmem.bytesPerActivate::384-511 65 0.77% 97.90%
+system.physmem.bytesPerActivate::512-639 38 0.45% 98.35%
+system.physmem.bytesPerActivate::640-767 36 0.42% 98.77%
+system.physmem.bytesPerActivate::768-895 15 0.18% 98.95%
+system.physmem.bytesPerActivate::896-1023 10 0.12% 99.07%
+system.physmem.bytesPerActivate::1024-1151 79 0.93% 100.00%
+system.physmem.bytesPerActivate::total 8483
+system.physmem.totQLat 1497477800
+system.physmem.totMemAccLat 1766109050
+system.physmem.totBusLat 71635000
+system.physmem.avgQLat 104521.38
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 123271.38
+system.physmem.avgRdBW 10.66
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 10.66
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 0.08
+system.physmem.busUtilRead 0.08
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 1.02
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 5838
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 40.75
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 6001688.70
+system.physmem.pageHitRate 40.75
+system.physmem_0.actEnergy 51557940
+system.physmem_0.preEnergy 27392310
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+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 5188176240.000001
+system.physmem_0.actBackEnergy 1121049780
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+system.physmem_0.totalIdleTime 82802255264
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+system.physmem_1.actEnergy 9046380
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+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 880164480.000000
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+system.physmem_1.actPowerDownEnergy 1982659500
+system.physmem_1.prePowerDownEnergy 1381296480
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+system.physmem_1.totalEnergy 23322152130
+system.physmem_1.averagePower 271.231327
+system.physmem_1.totalIdleTime 85419499755
+system.physmem_1.memoryStateTime::IDLE 100592000
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+system.cpu.branchPred.BTBHitPct 95.630841
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 189525.734081
+system.cpu.l2cache.demand_avg_miss_latency::total 172680.470464
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 167669.872424
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 189525.734081
+system.cpu.l2cache.overall_avg_miss_latency::total 172680.470464
+system.cpu.l2cache.blocked_cycles::no_mshrs 0
+system.cpu.l2cache.blocked_cycles::no_targets 0
+system.cpu.l2cache.blocked::no_mshrs 0
+system.cpu.l2cache.blocked::no_targets 0
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan
+system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1
+system.cpu.l2cache.ReadExReq_mshr_hits::total 1
+system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 5
+system.cpu.l2cache.ReadCleanReq_mshr_hits::total 5
+system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 8
+system.cpu.l2cache.ReadSharedReq_mshr_hits::total 8
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 5
+system.cpu.l2cache.demand_mshr_hits::cpu.data 9
+system.cpu.l2cache.demand_mshr_hits::total 14
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 5
+system.cpu.l2cache.overall_mshr_hits::cpu.data 9
+system.cpu.l2cache.overall_mshr_hits::total 14
+system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1986
+system.cpu.l2cache.HardPFReq_mshr_misses::total 1986
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 1
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235
+system.cpu.l2cache.ReadExReq_mshr_misses::total 235
+system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 10185
+system.cpu.l2cache.ReadCleanReq_mshr_misses::total 10185
+system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2787
+system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2787
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 10185
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3022
+system.cpu.l2cache.demand_mshr_misses::total 13207
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 10185
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3022
+system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1986
+system.cpu.l2cache.overall_mshr_misses::total 15193
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 99174661
+system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 99174661
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 16000
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 16000
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 19399000
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 19399000
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1646592500
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1646592500
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 536158000
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 536158000
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1646592500
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 555557000
+system.cpu.l2cache.demand_mshr_miss_latency::total 2202149500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1646592500
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 555557000
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 99174661
+system.cpu.l2cache.overall_mshr_miss_latency::total 2301324161
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf
+system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027243
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027243
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.189948
+system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.189948
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.043359
+system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.043359
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.189948
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.041452
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.104384
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.189948
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.041452
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.120081
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721
+system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 49936.888721
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 16000
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16000
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82548.936170
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82548.936170
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 161668.384880
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 161668.384880
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 192378.184428
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 192378.184428
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 161668.384880
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 183837.524818
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 166741.084273
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 161668.384880
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 183837.524818
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 49936.888721
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 151472.662476
+system.cpu.toL2Bus.snoop_filter.tot_requests 252022
+system.cpu.toL2Bus.snoop_filter.hit_single_requests 125518
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests 10474
+system.cpu.toL2Bus.snoop_filter.tot_snoops 866
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops 865
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 85986203000
+system.cpu.toL2Bus.trans_dist::ReadResp 117896
+system.cpu.toL2Bus.trans_dist::WritebackDirty 64558
+system.cpu.toL2Bus.trans_dist::WritebackClean 60939
+system.cpu.toL2Bus.trans_dist::HardPFReq 2337
+system.cpu.toL2Bus.trans_dist::UpgradeReq 1
+system.cpu.toL2Bus.trans_dist::UpgradeResp 1
+system.cpu.toL2Bus.trans_dist::ReadExReq 8626
+system.cpu.toL2Bus.trans_dist::ReadExResp 8626
+system.cpu.toL2Bus.trans_dist::ReadCleanReq 53621
+system.cpu.toL2Bus.trans_dist::ReadSharedReq 64277
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 160345
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 218199
+system.cpu.toL2Bus.pkt_count::total 378544
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6830336
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9298816
+system.cpu.toL2Bus.pkt_size::total 16129152
+system.cpu.toL2Bus.snoops 2338
+system.cpu.toL2Bus.snoopTraffic 64
+system.cpu.toL2Bus.snoop_fanout::samples 128862
+system.cpu.toL2Bus.snoop_fanout::mean 0.088172
+system.cpu.toL2Bus.snoop_fanout::stdev 0.283573
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 117501 91.18% 91.18%
+system.cpu.toL2Bus.snoop_fanout::1 11360 8.82% 100.00%
+system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
+system.cpu.toL2Bus.snoop_fanout::min_value 0
+system.cpu.toL2Bus.snoop_fanout::max_value 2
+system.cpu.toL2Bus.snoop_fanout::total 128862
+system.cpu.toL2Bus.reqLayer0.occupancy 251508000
+system.cpu.toL2Bus.reqLayer0.utilization 0.3
+system.cpu.toL2Bus.respLayer0.occupancy 80437981
+system.cpu.toL2Bus.respLayer0.utilization 0.1
+system.cpu.toL2Bus.respLayer1.occupancy 109359491
+system.cpu.toL2Bus.respLayer1.utilization 0.1
+system.membus.snoop_filter.tot_requests 14328
+system.membus.snoop_filter.hit_single_requests 10478
+system.membus.snoop_filter.hit_multi_requests 0
+system.membus.snoop_filter.tot_snoops 0
+system.membus.snoop_filter.hit_single_snoops 0
+system.membus.snoop_filter.hit_multi_snoops 0
+system.membus.pwrStateResidencyTicks::UNDEFINED 85986203000
+system.membus.trans_dist::ReadResp 14090
+system.membus.trans_dist::UpgradeReq 1
+system.membus.trans_dist::ReadExReq 235
+system.membus.trans_dist::ReadExResp 235
+system.membus.trans_dist::ReadSharedReq 14092
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 28653
+system.membus.pkt_count::total 28653
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 916800
+system.membus.pkt_size::total 916800
+system.membus.snoops 0
+system.membus.snoopTraffic 0
+system.membus.snoop_fanout::samples 14328
+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 14328 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
+system.membus.snoop_fanout::max_value 0
+system.membus.snoop_fanout::total 14328
+system.membus.reqLayer0.occupancy 18011178
+system.membus.reqLayer0.utilization 0.0
+system.membus.respLayer1.occupancy 77254535
+system.membus.respLayer1.utilization 0.1
---------- End Simulation Statistics ----------
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 2531961c1..4f7383f25 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 30 2017 17:14:30
-gem5 started Mar 30 2017 17:14:43
-gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 80103
+gem5 compiled Mar 31 2017 16:17:52
+gem5 started Mar 31 2017 16:18:04
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 50433
command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py long/se/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
@@ -24,4 +24,4 @@ Authors: Carl Sechen, Bill Swartz
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
-122 123 124 Exiting @ tick 102720088500 because target called exit()
+122 123 124 Exiting @ tick 102720088500 because exiting with last active thread context
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
index c833a13ad..0cd025b0c 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.102720
sim_ticks 102720088500
final_tick 102720088500
sim_freq 1000000000000
-host_inst_rate 110078
-host_op_rate 184500
-host_tick_rate 85614304
-host_mem_usage 318036
-host_seconds 1199.80
+host_inst_rate 108111
+host_op_rate 181205
+host_tick_rate 84085065
+host_mem_usage 318048
+host_seconds 1221.62
sim_insts 132071192
sim_ops 221363384
system.voltage_domain.voltage 1
@@ -290,7 +290,7 @@ system.cpu.fetch.Insts 415890076
system.cpu.fetch.Branches 40475084
system.cpu.fetch.predictedBranches 13128503
system.cpu.fetch.Cycles 151898082
-system.cpu.fetch.SquashCycles 14677483
+system.cpu.fetch.SquashCycles 14677482
system.cpu.fetch.TlbCycles 200
system.cpu.fetch.MiscStallCycles 5835
system.cpu.fetch.PendingTrapStallCycles 64355
@@ -352,7 +352,7 @@ system.cpu.iq.iqInstsAdded 486700641
system.cpu.iq.iqNonSpecInstsAdded 63617
system.cpu.iq.iqInstsIssued 336591190
system.cpu.iq.iqSquashedInstsIssued 1075815
-system.cpu.iq.iqSquashedInstsExamined 265400874
+system.cpu.iq.iqSquashedInstsExamined 265400873
system.cpu.iq.iqSquashedOperandsExamined 520101528
system.cpu.iq.iqSquashedNonSpecRemoved 62372
system.cpu.iq.issued_per_cycle::samples 205201489
@@ -453,7 +453,7 @@ system.cpu.iq.rate 1.638390
system.cpu.iq.fu_busy_cnt 3927876
system.cpu.iq.fu_busy_rate 0.011670
system.cpu.iq.int_inst_queue_reads 875282503
-system.cpu.iq.int_inst_queue_writes 737961959
+system.cpu.iq.int_inst_queue_writes 737961958
system.cpu.iq.int_inst_queue_wakeup_accesses 314539840
system.cpu.iq.fp_inst_queue_reads 8105057
system.cpu.iq.fp_inst_queue_writes 15024545
@@ -503,11 +503,11 @@ system.cpu.iew.wb_fanout 0.588199
system.cpu.commit.commitSquashedInsts 265431246
system.cpu.commit.commitNonSpecStalls 1245
system.cpu.commit.branchMispredicts 6620627
-system.cpu.commit.committed_per_cycle::samples 163282867
+system.cpu.commit.committed_per_cycle::samples 163282868
system.cpu.commit.committed_per_cycle::mean 1.355705
system.cpu.commit.committed_per_cycle::stdev 1.936594
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00%
-system.cpu.commit.committed_per_cycle::0 66681317 40.84% 40.84%
+system.cpu.commit.committed_per_cycle::0 66681318 40.84% 40.84%
system.cpu.commit.committed_per_cycle::1 54877393 33.61% 74.45%
system.cpu.commit.committed_per_cycle::2 13218924 8.10% 82.54%
system.cpu.commit.committed_per_cycle::3 10716776 6.56% 89.11%
@@ -519,7 +519,7 @@ system.cpu.commit.committed_per_cycle::8 6989165 4.28% 100.00%
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00%
system.cpu.commit.committed_per_cycle::min_value 0
system.cpu.commit.committed_per_cycle::max_value 8
-system.cpu.commit.committed_per_cycle::total 163282867
+system.cpu.commit.committed_per_cycle::total 163282868
system.cpu.commit.committedInsts 132071192
system.cpu.commit.committedOps 221363384
system.cpu.commit.swp_count 0
@@ -570,8 +570,8 @@ system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00%
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00%
system.cpu.commit.op_class_0::total 221363384
system.cpu.commit.bw_lim_events 6989165
-system.cpu.rob.rob_reads 643088332
-system.cpu.rob.rob_writes 1015902506
+system.cpu.rob.rob_reads 643088333
+system.cpu.rob.rob_writes 1015902505
system.cpu.timesIdled 2802
system.cpu.idleCycles 238689
system.cpu.committedInsts 132071192