diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:33 -0600 |
| commit | f3585c841e964c98911784a187fc4f081a02a0a6 (patch) | |
| tree | 2a5a3edeaeb0ffe37ca3a04b884f8f66c7538bbf /tests/long | |
| parent | cfc4a999828a5b51f4c514e3a7c47b4eebc450b9 (diff) | |
| download | gem5-f3585c841e964c98911784a187fc4f081a02a0a6.tar.xz | |
stats: update stats for cache occupancy and clock domain changes
Diffstat (limited to 'tests/long')
276 files changed, 4259 insertions, 42382 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini index 38f343beb..01fef3e75 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini @@ -15,16 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -175,6 +175,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -191,6 +192,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -520,6 +522,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -536,6 +539,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -545,6 +549,7 @@ eventq_index=0 [system.cpu0.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu0.itb] type=AlphaTLB @@ -675,6 +680,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags @@ -691,6 +697,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.dtb] @@ -1020,6 +1027,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags @@ -1036,6 +1044,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.interrupts] @@ -1045,6 +1054,7 @@ eventq_index=0 [system.cpu1.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu1.itb] type=AlphaTLB @@ -1081,7 +1091,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -1104,7 +1114,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -1138,6 +1148,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -1154,6 +1165,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -1171,6 +1183,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -1187,6 +1200,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] @@ -1267,7 +1281,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr index 0bcb6e870..20fe2d682 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr @@ -2,4 +2,3 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout index ef1ae1471..d125f29b8 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout @@ -1,13 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:30:57 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 125036000 -Exiting @ tick 1902738973500 because m5_exit instruction encountered +info: Launching CPU 1 @ 126320000 +Exiting @ tick 1903338216000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 3ddbcdbc7..4177c2e35 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.903338 # Nu sim_ticks 1903338216000 # Number of ticks simulated final_tick 1903338216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100362 # Simulator instruction rate (inst/s) -host_op_rate 100362 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3404824916 # Simulator tick rate (ticks/s) -host_mem_usage 359096 # Number of bytes of host memory used -host_seconds 559.01 # Real time elapsed on the host +host_inst_rate 150214 # Simulator instruction rate (inst/s) +host_op_rate 150214 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5096064990 # Simulator tick rate (ticks/s) +host_mem_usage 314972 # Number of bytes of host memory used +host_seconds 373.49 # Real time elapsed on the host sim_insts 56103611 # Number of instructions simulated sim_ops 56103611 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 740992 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 24346432 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2650176 # Number of bytes read from this memory @@ -421,6 +423,7 @@ system.membus.respLayer1.occupancy 3836772510 # La system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 376321991 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 345713 # number of replacements system.l2c.tags.tagsinuse 65292.619294 # Cycle average of tags in use system.l2c.tags.total_refs 2607692 # Total number of references to valid blocks. @@ -438,6 +441,15 @@ system.l2c.tags.occ_percent::cpu0.data 0.085431 # Av system.l2c.tags.occ_percent::cpu1.inst 0.020833 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.008543 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.996286 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 2154 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5524 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6881 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 50473 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.995041 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27399611 # Number of tag accesses +system.l2c.tags.data_accesses 27399611 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 754547 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 572386 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 313557 # number of ReadReq hits @@ -732,6 +744,11 @@ system.iocache.tags.warmup_cycle 1712301131000 # C system.iocache.tags.occ_blocks::tsunami.ide 0.213166 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.013323 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.013323 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375543 # Number of tag accesses +system.iocache.tags.data_accesses 375543 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 175 # number of ReadReq misses system.iocache.ReadReq_misses::total 175 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -1129,8 +1146,8 @@ system.cpu0.int_regfile_reads 59516377 # nu system.cpu0.int_regfile_writes 32453910 # number of integer regfile writes system.cpu0.fp_regfile_reads 110308 # number of floating regfile reads system.cpu0.fp_regfile_writes 111090 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1526243 # number of misc regfile reads -system.cpu0.misc_regfile_writes 747832 # number of misc regfile writes +system.cpu0.misc_regfile_reads 1625466 # number of misc regfile reads +system.cpu0.misc_regfile_writes 747841 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1275,6 +1292,13 @@ system.cpu0.icache.tags.warmup_cycle 26716185250 # Cy system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.693534 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995495 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.995495 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 86 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 314 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7662265 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7662265 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 6090993 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 6090993 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 6090993 # number of demand (read+write) hits @@ -1359,6 +1383,13 @@ system.cpu0.dcache.tags.warmup_cycle 25754000 # Cy system.cpu0.dcache.tags.occ_blocks::cpu0.data 471.490981 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.920881 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.920881 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 220 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 50559091 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 50559091 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 5751167 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 5751167 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3244504 # number of WriteReq hits @@ -1814,8 +1845,8 @@ system.cpu1.int_regfile_reads 18552962 # nu system.cpu1.int_regfile_writes 10191479 # number of integer regfile writes system.cpu1.fp_regfile_reads 58039 # number of floating regfile reads system.cpu1.fp_regfile_writes 58174 # number of floating regfile writes -system.cpu1.misc_regfile_reads 621722 # number of misc regfile reads -system.cpu1.misc_regfile_writes 265027 # number of misc regfile writes +system.cpu1.misc_regfile_reads 1024653 # number of misc regfile reads +system.cpu1.misc_regfile_writes 265032 # number of misc regfile writes system.cpu1.icache.tags.replacements 316719 # number of replacements system.cpu1.icache.tags.tagsinuse 504.225697 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 1849767 # Total number of references to valid blocks. @@ -1825,6 +1856,12 @@ system.cpu1.icache.tags.warmup_cycle 49140510500 # Cy system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.225697 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.984816 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.984816 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 420 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 2498600 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2498600 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 1849767 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 1849767 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 1849767 # number of demand (read+write) hits @@ -1909,6 +1946,12 @@ system.cpu1.dcache.tags.warmup_cycle 42037852500 # Cy system.cpu1.dcache.tags.occ_blocks::cpu1.data 495.920224 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968594 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.968594 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.666016 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 17217310 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 17217310 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 2089496 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 2089496 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 1222054 # number of WriteReq hits diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini index 275c9f168..80c9d1506 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini @@ -15,16 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -175,6 +175,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -191,6 +192,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] @@ -520,6 +522,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -536,6 +539,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] @@ -545,6 +549,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -566,6 +571,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -582,6 +588,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] @@ -625,7 +632,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -648,7 +655,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -682,6 +689,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -698,6 +706,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] @@ -778,7 +787,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr index 0bcb6e870..20fe2d682 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr @@ -2,4 +2,3 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything -hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout index 7f8767e11..6b0c7bafe 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:25:00 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /dist/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1860200687500 because m5_exit instruction encountered +Exiting @ tick 1860197780500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index c08f75535..674a7dfd5 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.860198 # Nu sim_ticks 1860197780500 # Number of ticks simulated final_tick 1860197780500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 103834 # Simulator instruction rate (inst/s) -host_op_rate 103834 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3645751305 # Simulator tick rate (ticks/s) -host_mem_usage 355004 # Number of bytes of host memory used -host_seconds 510.24 # Real time elapsed on the host +host_inst_rate 153122 # Simulator instruction rate (inst/s) +host_op_rate 153122 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5376333902 # Simulator tick rate (ticks/s) +host_mem_usage 310876 # Number of bytes of host memory used +host_seconds 346.00 # Real time elapsed on the host sim_insts 52979882 # Number of instructions simulated sim_ops 52979882 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 963968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24878976 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory @@ -417,6 +419,11 @@ system.iocache.tags.warmup_cycle 1710341603000 # C system.iocache.tags.occ_blocks::tsunami.ide 1.261116 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078820 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078820 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -521,6 +528,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 61.928509 # BTB Hit Percentage system.cpu.branchPred.usedRAS 906521 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 39211 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -814,7 +822,7 @@ system.cpu.int_regfile_reads 73881277 # nu system.cpu.int_regfile_writes 40316653 # number of integer regfile writes system.cpu.fp_regfile_reads 166009 # number of floating regfile reads system.cpu.fp_regfile_writes 167434 # number of floating regfile writes -system.cpu.misc_regfile_reads 1986207 # number of misc regfile reads +system.cpu.misc_regfile_reads 2028435 # number of misc regfile reads system.cpu.misc_regfile_writes 938984 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -952,6 +960,13 @@ system.cpu.icache.tags.warmup_cycle 26489829250 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 509.660060 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.995430 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.995430 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 112 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 324 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 9566377 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9566377 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 7489392 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7489392 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7489392 # number of demand (read+write) hits @@ -1040,6 +1055,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.821654 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081017 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.094308 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.996979 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 492 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3492 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3315 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2416 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55452 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 26727370 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26727370 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 995146 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 827013 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1822159 # number of ReadReq hits @@ -1232,6 +1256,13 @@ system.cpu.dcache.tags.warmup_cycle 25477000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.994567 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 94 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 63738376 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63738376 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 7205308 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 7205308 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4203634 # number of WriteReq hits diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini index 8069712e0..933f62fba 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini @@ -15,16 +15,16 @@ boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 cache_line_size=64 clk_domain=system.clk_domain -console=/scratch/nilay/GEM5/system/binaries/console +console=/dist/binaries/console eventq_index=0 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux +kernel=/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic mem_ranges=0:134217727 memories=system.physmem num_work_ids=16 -pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal +pal=/dist/binaries/ts_osfpal readfile=tests/halt.sh symbolfile= system_rev=1024 @@ -108,6 +108,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -124,6 +125,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -146,6 +148,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -162,6 +165,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -171,6 +175,7 @@ eventq_index=0 [system.cpu0.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu0.itb] type=AlphaTLB @@ -218,6 +223,7 @@ size=64 [system.cpu1.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu1.itb] type=AlphaTLB @@ -646,6 +652,7 @@ opLat=3 [system.cpu2.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu2.itb] type=AlphaTLB @@ -682,7 +689,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -705,7 +712,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -739,6 +746,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -755,6 +763,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -772,6 +781,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -788,6 +798,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] @@ -868,7 +879,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img +image_file=/dist/disks/linux-latest.img read_only=true [system.terminal] diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr index 3c54e08bb..b501a6b40 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simerr @@ -1,6 +1,5 @@ warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout index 6d6f549a2..ecd39bc4a 100755 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout @@ -1,6254 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:47 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:37:21 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: Entering event queue @ 0. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1000000000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2000000000. Starting simulation... -info: Entering event queue @ 2000005000. Starting simulation... -switching cpus -info: Entering event queue @ 2000007000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3000007000. Starting simulation... -switching cpus -info: Entering event queue @ 3000031000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4000031000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5000031000. Starting simulation... -switching cpus -info: Entering event queue @ 5000032000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 6000032000. Starting simulation... -info: Entering event queue @ 7566911500. Starting simulation... -info: Entering event queue @ 7566971250. Starting simulation... -switching cpus -info: Entering event queue @ 7566976000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 8566976000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 9566976000. Starting simulation... -switching cpus -info: Entering event queue @ 9566983500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 10566983500. Starting simulation... -switching cpus -info: Entering event queue @ 10567083000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 11567083000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 12567083000. Starting simulation... -switching cpus -info: Entering event queue @ 12567090500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 13567090500. Starting simulation... -switching cpus -info: Entering event queue @ 13567098000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 14567098000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 15567098000. Starting simulation... -switching cpus -info: Entering event queue @ 15567105500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 16567105500. Starting simulation... -switching cpus -info: Entering event queue @ 16567113000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 17567113000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 18567113000. Starting simulation... -switching cpus -info: Entering event queue @ 18567120500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 19567120500. Starting simulation... -info: Entering event queue @ 19567148000. Starting simulation... -switching cpus -info: Entering event queue @ 19567153500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 20567153500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 21567153500. Starting simulation... -switching cpus -info: Entering event queue @ 21567161000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 22567161000. Starting simulation... -info: Entering event queue @ 22567173500. Starting simulation... -switching cpus -info: Entering event queue @ 22567179000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 23567179000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 24567179000. Starting simulation... -switching cpus -info: Entering event queue @ 24567186500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 25567186500. Starting simulation... -switching cpus -info: Entering event queue @ 25567194000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 26567194000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 27567194000. Starting simulation... -info: Entering event queue @ 27567201500. Starting simulation... -switching cpus -info: Entering event queue @ 27567202500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 28567202500. Starting simulation... -switching cpus -info: Entering event queue @ 28567210000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 29567210000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 30567210000. Starting simulation... -switching cpus -info: Entering event queue @ 30567217500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 31567217500. Starting simulation... -info: Entering event queue @ 31567226000. Starting simulation... -info: Entering event queue @ 31567232000. Starting simulation... -switching cpus -info: Entering event queue @ 31567236500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 32567236500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 33567236500. Starting simulation... -switching cpus -info: Entering event queue @ 33567244000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 34567244000. Starting simulation... -switching cpus -info: Entering event queue @ 34567251500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 35567251500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 36567251500. Starting simulation... -switching cpus -info: Entering event queue @ 36567259000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 37567259000. Starting simulation... -switching cpus -info: Entering event queue @ 37567266500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 38567266500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 39567266500. Starting simulation... -switching cpus -info: Entering event queue @ 39567274000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 40567274000. Starting simulation... -switching cpus -info: Entering event queue @ 40567277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 41567277000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 42567277000. Starting simulation... -switching cpus -info: Entering event queue @ 42567284500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 43567284500. Starting simulation... -switching cpus -info: Entering event queue @ 43945335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 44945335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 45945335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 46945335500. Starting simulation... -switching cpus -info: Entering event queue @ 47851585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 48851585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 49851585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 50851585500. Starting simulation... -switching cpus -info: Entering event queue @ 51757835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 52757835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 53757835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 54757835500. Starting simulation... -switching cpus -info: Entering event queue @ 55664085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 56664085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 57664085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 58664085500. Starting simulation... -switching cpus -info: Entering event queue @ 59570335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 60570335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 61570335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 62570335500. Starting simulation... -switching cpus -info: Entering event queue @ 63476585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 64476585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 65476585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 66476585500. Starting simulation... -switching cpus -info: Entering event queue @ 67382835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 68382835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 69382835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 70382835500. Starting simulation... -switching cpus -info: Entering event queue @ 71289085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 72289085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 73289085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 74289085500. Starting simulation... -switching cpus -info: Entering event queue @ 75195335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 76195335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 77195335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 78195335500. Starting simulation... -switching cpus -info: Entering event queue @ 79101585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 80101585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 81101585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 82101585500. Starting simulation... -switching cpus -info: Entering event queue @ 83007835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 84007835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 85007835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 86007835500. Starting simulation... -switching cpus -info: Entering event queue @ 86914085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 87914085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 88914085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 89914085500. Starting simulation... -switching cpus -info: Entering event queue @ 90820335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 91820335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 92820335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 93820335500. Starting simulation... -switching cpus -info: Entering event queue @ 94726585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 95726585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 96726585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 97726585500. Starting simulation... -switching cpus -info: Entering event queue @ 98632835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 99632835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 100632835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 101632835500. Starting simulation... -switching cpus -info: Entering event queue @ 102539085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 103539085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 104539085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 105539085500. Starting simulation... -switching cpus -info: Entering event queue @ 106445335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 107445335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 108445335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 109445335500. Starting simulation... -switching cpus -info: Entering event queue @ 110351585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 111351585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 112351585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 113351585500. Starting simulation... -switching cpus -info: Entering event queue @ 114257835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 115257835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 116257835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 117257835500. Starting simulation... -switching cpus -info: Entering event queue @ 118164085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 119164085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 120164085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 121164085500. Starting simulation... -switching cpus -info: Entering event queue @ 122070335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 123070335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 124070335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 125070335500. Starting simulation... -switching cpus -info: Entering event queue @ 125976585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 126976585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 127976585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 128976585500. Starting simulation... -switching cpus -info: Entering event queue @ 129882835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 130882835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 131882835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 132882835500. Starting simulation... -switching cpus -info: Entering event queue @ 133789085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 134789085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 135789085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 136789085500. Starting simulation... -switching cpus -info: Entering event queue @ 137695335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 138695335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 139695335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 140695335500. Starting simulation... -switching cpus -info: Entering event queue @ 141601585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 142601585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 143601585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 144601585500. Starting simulation... -switching cpus -info: Entering event queue @ 145507835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 146507835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 147507835500. Starting simulation... -switching cpus -info: Entering event queue @ 147507843000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 148507843000. Starting simulation... -switching cpus -info: Entering event queue @ 149414085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 150414085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 151414085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 152414085500. Starting simulation... -switching cpus -info: Entering event queue @ 153320335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 154320335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 155320335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 156320335500. Starting simulation... -switching cpus -info: Entering event queue @ 157226585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 158226585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 159226585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 160226585500. Starting simulation... -switching cpus -info: Entering event queue @ 161132835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 162132835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 163132835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 164132835500. Starting simulation... -switching cpus -info: Entering event queue @ 165039085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 166039085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 167039085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 168039085500. Starting simulation... -switching cpus -info: Entering event queue @ 168945335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 169945335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 170945335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 171945335500. Starting simulation... -switching cpus -info: Entering event queue @ 172851585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 173851585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 174851585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 175851585500. Starting simulation... -switching cpus -info: Entering event queue @ 176757835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 177757835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 178757835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 179757835500. Starting simulation... -switching cpus -info: Entering event queue @ 180664085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 181664085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 182664085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 183664085500. Starting simulation... -switching cpus -info: Entering event queue @ 184570335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 185570335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 186570335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 187570335500. Starting simulation... -switching cpus -info: Entering event queue @ 188476585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 189476585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 190476585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 191476585500. Starting simulation... -switching cpus -info: Entering event queue @ 192382835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 193382835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 194382835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 195382835500. Starting simulation... -switching cpus -info: Entering event queue @ 196289085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 197289085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 198289085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 199289085500. Starting simulation... -switching cpus -info: Entering event queue @ 200195335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 201195335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 202195335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 203195335500. Starting simulation... -switching cpus -info: Entering event queue @ 204101585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 205101585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 206101585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 207101585500. Starting simulation... -switching cpus -info: Entering event queue @ 208007835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 209007835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 210007835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 211007835500. Starting simulation... -switching cpus -info: Entering event queue @ 211914085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 212914085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 213914085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 214914085500. Starting simulation... -switching cpus -info: Entering event queue @ 215820335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 216820335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 217820335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 218820335500. Starting simulation... -switching cpus -info: Entering event queue @ 219726585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 220726585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 221726585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 222726585500. Starting simulation... -switching cpus -info: Entering event queue @ 223632835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 224632835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 225632835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 226632835500. Starting simulation... -switching cpus -info: Entering event queue @ 227539085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 228539085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 229539085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 230539085500. Starting simulation... -switching cpus -info: Entering event queue @ 231445335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 232445335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 233445335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 234445335500. Starting simulation... -switching cpus -info: Entering event queue @ 235351585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 236351585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 237351585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 238351585500. Starting simulation... -switching cpus -info: Entering event queue @ 239257835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 240257835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 241257835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 242257835500. Starting simulation... -switching cpus -info: Entering event queue @ 243164085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 244164085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 245164085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 246164085500. Starting simulation... -switching cpus -info: Entering event queue @ 247070335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 248070335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 249070335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 250070335500. Starting simulation... -switching cpus -info: Entering event queue @ 250976585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 251976585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 252976585500. Starting simulation... -switching cpus -info: Entering event queue @ 252976593000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 253976593000. Starting simulation... -switching cpus -info: Entering event queue @ 254882835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 255882835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 256882835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 257882835500. Starting simulation... -switching cpus -info: Entering event queue @ 258789085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 259789085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 260789085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 261789085500. Starting simulation... -switching cpus -info: Entering event queue @ 262695335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 263695335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 264695335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 265695335500. Starting simulation... -switching cpus -info: Entering event queue @ 266601585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 267601585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 268601585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 269601585500. Starting simulation... -switching cpus -info: Entering event queue @ 270507835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 271507835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 272507835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 273507835500. Starting simulation... -switching cpus -info: Entering event queue @ 274414085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 275414085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 276414085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 277414085500. Starting simulation... -switching cpus -info: Entering event queue @ 278320335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 279320335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 280320335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 281320335500. Starting simulation... -switching cpus -info: Entering event queue @ 282226585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 283226585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 284226585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 285226585500. Starting simulation... -switching cpus -info: Entering event queue @ 286132835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 287132835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 288132835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 289132835500. Starting simulation... -switching cpus -info: Entering event queue @ 290039085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 291039085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 292039085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 293039085500. Starting simulation... -switching cpus -info: Entering event queue @ 293945335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 294945335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 295945335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 296945335500. Starting simulation... -switching cpus -info: Entering event queue @ 297851585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 298851585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 299851585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 300851585500. Starting simulation... -switching cpus -info: Entering event queue @ 301757835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 302757835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 303757835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 304757835500. Starting simulation... -switching cpus -info: Entering event queue @ 305664085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 306664085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 307664085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 308664085500. Starting simulation... -switching cpus -info: Entering event queue @ 309570335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 310570335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 311570335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 312570335500. Starting simulation... -switching cpus -info: Entering event queue @ 313476585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 314476585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 315476585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 316476585500. Starting simulation... -switching cpus -info: Entering event queue @ 317382835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 318382835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 319382835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 320382835500. Starting simulation... -switching cpus -info: Entering event queue @ 321289085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 322289085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 323289085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 324289085500. Starting simulation... -switching cpus -info: Entering event queue @ 325195335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 326195335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 327195335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 328195335500. Starting simulation... -switching cpus -info: Entering event queue @ 329101585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 330101585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 331101585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 332101585500. Starting simulation... -switching cpus -info: Entering event queue @ 333007835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 334007835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 335007835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 336007835500. Starting simulation... -switching cpus -info: Entering event queue @ 336914085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 337914085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 338914085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 339914085500. Starting simulation... -switching cpus -info: Entering event queue @ 340820335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 341820335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 342820335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 343820335500. Starting simulation... -switching cpus -info: Entering event queue @ 344726585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 345726585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 346726585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 347726585500. Starting simulation... -switching cpus -info: Entering event queue @ 348632835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 349632835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 350632835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 351632835500. Starting simulation... -switching cpus -info: Entering event queue @ 352539085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 353539085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 354539085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 355539085500. Starting simulation... -switching cpus -info: Entering event queue @ 356445335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 357445335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 358445335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 359445335500. Starting simulation... -switching cpus -info: Entering event queue @ 360351585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 361351585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 362351585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 363351585500. Starting simulation... -switching cpus -info: Entering event queue @ 364257835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 365257835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 366257835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 367257835500. Starting simulation... -switching cpus -info: Entering event queue @ 368164085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 369164085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 370164085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 371164085500. Starting simulation... -switching cpus -info: Entering event queue @ 372070335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 373070335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 374070335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 375070335500. Starting simulation... -switching cpus -info: Entering event queue @ 375976585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 376976585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 377976585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 378976585500. Starting simulation... -switching cpus -info: Entering event queue @ 379882835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 380882835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 381882835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 382882835500. Starting simulation... -switching cpus -info: Entering event queue @ 383789085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 384789085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 385789085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 386789085500. Starting simulation... -switching cpus -info: Entering event queue @ 387695335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 388695335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 389695335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 390695335500. Starting simulation... -switching cpus -info: Entering event queue @ 391601585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 392601585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 393601585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 394601585500. Starting simulation... -switching cpus -info: Entering event queue @ 395507835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 396507835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 397507835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 398507835500. Starting simulation... -switching cpus -info: Entering event queue @ 399414085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 400414085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 401414085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 402414085500. Starting simulation... -switching cpus -info: Entering event queue @ 403320335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 404320335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 405320335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 406320335500. Starting simulation... -switching cpus -info: Entering event queue @ 407226585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 408226585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 409226585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 410226585500. Starting simulation... -switching cpus -info: Entering event queue @ 411132835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 412132835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 413132835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 414132835500. Starting simulation... -switching cpus -info: Entering event queue @ 415039085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 416039085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 417039085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 418039085500. Starting simulation... -switching cpus -info: Entering event queue @ 418945335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 419945335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 420945335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 421945335500. Starting simulation... -switching cpus -info: Entering event queue @ 422851585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 423851585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 424851585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 425851585500. Starting simulation... -switching cpus -info: Entering event queue @ 426757835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 427757835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 428757835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 429757835500. Starting simulation... -switching cpus -info: Entering event queue @ 430664085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 431664085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 432664085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 433664085500. Starting simulation... -switching cpus -info: Entering event queue @ 434570335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 435570335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 436570335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 437570335500. Starting simulation... -switching cpus -info: Entering event queue @ 438476585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 439476585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 440476585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 441476585500. Starting simulation... -switching cpus -info: Entering event queue @ 442382835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 443382835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 444382835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 445382835500. Starting simulation... -switching cpus -info: Entering event queue @ 446289085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 447289085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 448289085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 449289085500. Starting simulation... -switching cpus -info: Entering event queue @ 450195335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 451195335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 452195335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 453195335500. Starting simulation... -switching cpus -info: Entering event queue @ 454101585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 455101585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 456101585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 457101585500. Starting simulation... -switching cpus -info: Entering event queue @ 458007835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 459007835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 460007835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 461007835500. Starting simulation... -switching cpus -info: Entering event queue @ 461914085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 462914085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 463914085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 464914085500. Starting simulation... -switching cpus -info: Entering event queue @ 465820335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 466820335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 467820335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 468820335500. Starting simulation... -switching cpus -info: Entering event queue @ 469726585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 470726585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 471726585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 472726585500. Starting simulation... -switching cpus -info: Entering event queue @ 473632835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 474632835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 475632835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 476632835500. Starting simulation... -switching cpus -info: Entering event queue @ 477539085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 478539085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 479539085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 480539085500. Starting simulation... -switching cpus -info: Entering event queue @ 481445335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 482445335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 483445335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 484445335500. Starting simulation... -switching cpus -info: Entering event queue @ 485351585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 486351585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 487351585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 488351585500. Starting simulation... -switching cpus -info: Entering event queue @ 489257835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 490257835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 491257835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 492257835500. Starting simulation... -switching cpus -info: Entering event queue @ 493164085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 494164085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 495164085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 496164085500. Starting simulation... -switching cpus -info: Entering event queue @ 497070335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 498070335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 499070335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 500070335500. Starting simulation... -switching cpus -info: Entering event queue @ 500976585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 501976585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 502976585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 503976585500. Starting simulation... -switching cpus -info: Entering event queue @ 504882835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 505882835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 506882835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 507882835500. Starting simulation... -switching cpus -info: Entering event queue @ 508789085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 509789085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 510789085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 511789085500. Starting simulation... -switching cpus -info: Entering event queue @ 512695335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 513695335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 514695335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 515695335500. Starting simulation... -switching cpus -info: Entering event queue @ 516601585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 517601585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 518601585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 519601585500. Starting simulation... -switching cpus -info: Entering event queue @ 520507835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 521507835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 522507835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 523507835500. Starting simulation... -switching cpus -info: Entering event queue @ 524414085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 525414085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 526414085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 527414085500. Starting simulation... -switching cpus -info: Entering event queue @ 528320335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 529320335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 530320335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 531320335500. Starting simulation... -switching cpus -info: Entering event queue @ 532226585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 533226585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 534226585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 535226585500. Starting simulation... -switching cpus -info: Entering event queue @ 536132835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 537132835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 538132835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 539132835500. Starting simulation... -switching cpus -info: Entering event queue @ 540039085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 541039085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 542039085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 543039085500. Starting simulation... -switching cpus -info: Entering event queue @ 543945335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 544945335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 545945335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 546945335500. Starting simulation... -switching cpus -info: Entering event queue @ 547851585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 548851585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 549851585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 550851585500. Starting simulation... -switching cpus -info: Entering event queue @ 551757835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 552757835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 553757835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 554757835500. Starting simulation... -switching cpus -info: Entering event queue @ 555664085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 556664085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 557664085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 558664085500. Starting simulation... -switching cpus -info: Entering event queue @ 559570335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 560570335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 561570335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 562570335500. Starting simulation... -switching cpus -info: Entering event queue @ 563476585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 564476585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 565476585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 566476585500. Starting simulation... -switching cpus -info: Entering event queue @ 567382835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 568382835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 569382835500. Starting simulation... -switching cpus -info: Entering event queue @ 569382939000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 570382939000. Starting simulation... -switching cpus -info: Entering event queue @ 571289085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 572289085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 573289085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 574289085500. Starting simulation... -switching cpus -info: Entering event queue @ 575195335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 576195335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 577195335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 578195335500. Starting simulation... -switching cpus -info: Entering event queue @ 579101585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 580101585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 581101585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 582101585500. Starting simulation... -switching cpus -info: Entering event queue @ 583007835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 584007835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 585007835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 586007835500. Starting simulation... -switching cpus -info: Entering event queue @ 586914085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 587914085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 588914085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 589914085500. Starting simulation... -switching cpus -info: Entering event queue @ 590820335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 591820335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 592820335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 593820335500. Starting simulation... -switching cpus -info: Entering event queue @ 594726585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 595726585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 596726585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 597726585500. Starting simulation... -switching cpus -info: Entering event queue @ 598632835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 599632835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 600632835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 601632835500. Starting simulation... -switching cpus -info: Entering event queue @ 602539085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 603539085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 604539085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 605539085500. Starting simulation... -switching cpus -info: Entering event queue @ 606445335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 607445335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 608445335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 609445335500. Starting simulation... -switching cpus -info: Entering event queue @ 610351585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 611351585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 612351585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 613351585500. Starting simulation... -switching cpus -info: Entering event queue @ 614257835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 615257835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 616257835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 617257835500. Starting simulation... -switching cpus -info: Entering event queue @ 618164085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 619164085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 620164085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 621164085500. Starting simulation... -switching cpus -info: Entering event queue @ 622070335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 623070335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 624070335500. Starting simulation... -switching cpus -info: Entering event queue @ 624070336500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 625070336500. Starting simulation... -switching cpus -info: Entering event queue @ 625195317000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 626195317000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 627195317000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 628195317000. Starting simulation... -switching cpus -info: Entering event queue @ 628906271500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 629906271500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 630906271500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 631906271500. Starting simulation... -switching cpus -info: Entering event queue @ 632812523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 633812523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 634812523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 635812523000. Starting simulation... -switching cpus -info: Entering event queue @ 636718773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 637718773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 638718773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 639718773000. Starting simulation... -switching cpus -info: Entering event queue @ 640625023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 641625023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 642625023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 643625023000. Starting simulation... -switching cpus -info: Entering event queue @ 644531273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 645531273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 646531273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 647531273000. Starting simulation... -switching cpus -info: Entering event queue @ 648437523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 649437523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 650437523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 651437523000. Starting simulation... -switching cpus -info: Entering event queue @ 652343773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 653343773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 654343773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 655343773000. Starting simulation... -switching cpus -info: Entering event queue @ 656250023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 657250023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 658250023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 659250023000. Starting simulation... -switching cpus -info: Entering event queue @ 660156273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 661156273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 662156273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 663156273000. Starting simulation... -switching cpus -info: Entering event queue @ 664062523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 665062523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 666062523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 667062523000. Starting simulation... -switching cpus -info: Entering event queue @ 667968773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 668968773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 669968773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 670968773000. Starting simulation... -switching cpus -info: Entering event queue @ 671875023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 672875023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 673875023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 674875023000. Starting simulation... -switching cpus -info: Entering event queue @ 675781273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 676781273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 677781273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 678781273000. Starting simulation... -switching cpus -info: Entering event queue @ 679687523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 680687523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 681687523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 682687523000. Starting simulation... -switching cpus -info: Entering event queue @ 683593773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 684593773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 685593773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 686593773000. Starting simulation... -switching cpus -info: Entering event queue @ 687500023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 688500023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 689500023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 690500023000. Starting simulation... -switching cpus -info: Entering event queue @ 691406273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 692406273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 693406273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 694406273000. Starting simulation... -switching cpus -info: Entering event queue @ 695312523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 696312523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 697312523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 698312523000. Starting simulation... -switching cpus -info: Entering event queue @ 699218773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 700218773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 701218773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 702218773000. Starting simulation... -switching cpus -info: Entering event queue @ 703125023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 704125023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 705125023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 706125023000. Starting simulation... -switching cpus -info: Entering event queue @ 707031273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 708031273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 709031273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 710031273000. Starting simulation... -switching cpus -info: Entering event queue @ 710937523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 711937523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 712937523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 713937523000. Starting simulation... -switching cpus -info: Entering event queue @ 714843773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 715843773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 716843773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 717843773000. Starting simulation... -switching cpus -info: Entering event queue @ 718750023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 719750023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 720750023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 721750023000. Starting simulation... -switching cpus -info: Entering event queue @ 722656273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 723656273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 724656273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 725656273000. Starting simulation... -switching cpus -info: Entering event queue @ 726562523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 727562523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 728562523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 729562523000. Starting simulation... -switching cpus -info: Entering event queue @ 730468773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 731468773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 732468773000. Starting simulation... -switching cpus -info: Entering event queue @ 732468780500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 733468780500. Starting simulation... -switching cpus -info: Entering event queue @ 734375023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 735375023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 736375023000. Starting simulation... -switching cpus -info: Entering event queue @ 736375030500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 737375030500. Starting simulation... -switching cpus -info: Entering event queue @ 738281273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 739281273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 740281273000. Starting simulation... -switching cpus -info: Entering event queue @ 740281280500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 741281280500. Starting simulation... -switching cpus -info: Entering event queue @ 742187523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 743187523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 744187523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 745187523000. Starting simulation... -switching cpus -info: Entering event queue @ 746093773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 747093773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 748093773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 749093773000. Starting simulation... -switching cpus -info: Entering event queue @ 750000023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 751000023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 752000023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 753000023000. Starting simulation... -switching cpus -info: Entering event queue @ 753906273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 754906273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 755906273000. Starting simulation... -switching cpus -info: Entering event queue @ 755906280500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 756906280500. Starting simulation... -switching cpus -info: Entering event queue @ 757812523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 758812523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 759812523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 760812523000. Starting simulation... -switching cpus -info: Entering event queue @ 761718773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 762718773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 763718773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 764718773000. Starting simulation... -switching cpus -info: Entering event queue @ 765625023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 766625023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 767625023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 768625023000. Starting simulation... -switching cpus -info: Entering event queue @ 769531273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 770531273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 771531273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 772531273000. Starting simulation... -switching cpus -info: Entering event queue @ 773437523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 774437523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 775437523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 776437523000. Starting simulation... -switching cpus -info: Entering event queue @ 777343773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 778343773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 779343773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 780343773000. Starting simulation... -switching cpus -info: Entering event queue @ 781250023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 782250023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 783250023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 784250023000. Starting simulation... -switching cpus -info: Entering event queue @ 785156273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 786156273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 787156273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 788156273000. Starting simulation... -switching cpus -info: Entering event queue @ 789062523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 790062523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 791062523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 792062523000. Starting simulation... -switching cpus -info: Entering event queue @ 792968773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 793968773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 794968773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 795968773000. Starting simulation... -switching cpus -info: Entering event queue @ 796875023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 797875023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 798875023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 799875023000. Starting simulation... -switching cpus -info: Entering event queue @ 800781273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 801781273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 802781273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 803781273000. Starting simulation... -switching cpus -info: Entering event queue @ 804687523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 805687523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 806687523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 807687523000. Starting simulation... -switching cpus -info: Entering event queue @ 808593773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 809593773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 810593773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 811593773000. Starting simulation... -switching cpus -info: Entering event queue @ 812500023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 813500023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 814500023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 815500023000. Starting simulation... -switching cpus -info: Entering event queue @ 816406273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 817406273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 818406273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 819406273000. Starting simulation... -switching cpus -info: Entering event queue @ 820312523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 821312523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 822312523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 823312523000. Starting simulation... -switching cpus -info: Entering event queue @ 824218773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 825218773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 826218773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 827218773000. Starting simulation... -switching cpus -info: Entering event queue @ 828125023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 829125023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 830125023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 831125023000. Starting simulation... -switching cpus -info: Entering event queue @ 832031273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 833031273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 834031273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 835031273000. Starting simulation... -switching cpus -info: Entering event queue @ 835937523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 836937523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 837937523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 838937523000. Starting simulation... -switching cpus -info: Entering event queue @ 839843773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 840843773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 841843773000. Starting simulation... -switching cpus -info: Entering event queue @ 841843780500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 842843780500. Starting simulation... -switching cpus -info: Entering event queue @ 843750023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 844750023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 845750023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 846750023000. Starting simulation... -switching cpus -info: Entering event queue @ 847656273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 848656273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 849656273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 850656273000. Starting simulation... -switching cpus -info: Entering event queue @ 851562523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 852562523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 853562523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 854562523000. Starting simulation... -switching cpus -info: Entering event queue @ 855468773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 856468773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 857468773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 858468773000. Starting simulation... -switching cpus -info: Entering event queue @ 859375023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 860375023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 861375023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 862375023000. Starting simulation... -switching cpus -info: Entering event queue @ 863281273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 864281273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 865281273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 866281273000. Starting simulation... -switching cpus -info: Entering event queue @ 867187523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 868187523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 869187523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 870187523000. Starting simulation... -switching cpus -info: Entering event queue @ 871093773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 872093773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 873093773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 874093773000. Starting simulation... -switching cpus -info: Entering event queue @ 875000023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 876000023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 877000023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 878000023000. Starting simulation... -switching cpus -info: Entering event queue @ 878906273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 879906273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 880906273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 881906273000. Starting simulation... -switching cpus -info: Entering event queue @ 882812523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 883812523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 884812523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 885812523000. Starting simulation... -switching cpus -info: Entering event queue @ 886718773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 887718773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 888718773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 889718773000. Starting simulation... -switching cpus -info: Entering event queue @ 890625023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 891625023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 892625023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 893625023000. Starting simulation... -switching cpus -info: Entering event queue @ 894531273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 895531273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 896531273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 897531273000. Starting simulation... -switching cpus -info: Entering event queue @ 898437523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 899437523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 900437523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 901437523000. Starting simulation... -switching cpus -info: Entering event queue @ 902343773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 903343773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 904343773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 905343773000. Starting simulation... -switching cpus -info: Entering event queue @ 906250023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 907250023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 908250023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 909250023000. Starting simulation... -switching cpus -info: Entering event queue @ 910156273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 911156273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 912156273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 913156273000. Starting simulation... -switching cpus -info: Entering event queue @ 914062523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 915062523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 916062523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 917062523000. Starting simulation... -switching cpus -info: Entering event queue @ 917968773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 918968773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 919968773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 920968773000. Starting simulation... -switching cpus -info: Entering event queue @ 921875023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 922875023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 923875023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 924875023000. Starting simulation... -switching cpus -info: Entering event queue @ 925781273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 926781273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 927781273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 928781273000. Starting simulation... -switching cpus -info: Entering event queue @ 929687523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 930687523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 931687523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 932687523000. Starting simulation... -switching cpus -info: Entering event queue @ 933593773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 934593773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 935593773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 936593773000. Starting simulation... -switching cpus -info: Entering event queue @ 937500023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 938500023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 939500023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 940500023000. Starting simulation... -switching cpus -info: Entering event queue @ 941406273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 942406273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 943406273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 944406273000. Starting simulation... -switching cpus -info: Entering event queue @ 945312523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 946312523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 947312523000. Starting simulation... -switching cpus -info: Entering event queue @ 947312530500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 948312530500. Starting simulation... -switching cpus -info: Entering event queue @ 949218773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 950218773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 951218773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 952218773000. Starting simulation... -switching cpus -info: Entering event queue @ 953125023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 954125023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 955125023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 956125023000. Starting simulation... -switching cpus -info: Entering event queue @ 957031273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 958031273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 959031273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 960031273000. Starting simulation... -switching cpus -info: Entering event queue @ 960937523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 961937523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 962937523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 963937523000. Starting simulation... -switching cpus -info: Entering event queue @ 964843773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 965843773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 966843773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 967843773000. Starting simulation... -switching cpus -info: Entering event queue @ 968750023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 969750023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 970750023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 971750023000. Starting simulation... -switching cpus -info: Entering event queue @ 972656273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 973656273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 974656273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 975656273000. Starting simulation... -switching cpus -info: Entering event queue @ 976562523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 977562523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 978562523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 979562523000. Starting simulation... -switching cpus -info: Entering event queue @ 980468773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 981468773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 982468773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 983468773000. Starting simulation... -switching cpus -info: Entering event queue @ 984375023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 985375023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 986375023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 987375023000. Starting simulation... -switching cpus -info: Entering event queue @ 988281273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 989281273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 990281273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 991281273000. Starting simulation... -switching cpus -info: Entering event queue @ 992187523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 993187523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 994187523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 995187523000. Starting simulation... -switching cpus -info: Entering event queue @ 996093773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 997093773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 998093773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 999093773000. Starting simulation... -switching cpus -info: Entering event queue @ 1000000023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1001000023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1002000023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1003000023000. Starting simulation... -switching cpus -info: Entering event queue @ 1003906273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1004906273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1005906273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1006906273000. Starting simulation... -switching cpus -info: Entering event queue @ 1007812523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1008812523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1009812523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1010812523000. Starting simulation... -switching cpus -info: Entering event queue @ 1011718773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1012718773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1013718773000. Starting simulation... -switching cpus -info: Entering event queue @ 1013718780500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1014718780500. Starting simulation... -switching cpus -info: Entering event queue @ 1015625023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1016625023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1017625023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1018625023000. Starting simulation... -switching cpus -info: Entering event queue @ 1019531273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1020531273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1021531273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1022531273000. Starting simulation... -switching cpus -info: Entering event queue @ 1023437523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1024437523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1025437523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1026437523000. Starting simulation... -switching cpus -info: Entering event queue @ 1027343773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1028343773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1029343773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1030343773000. Starting simulation... -switching cpus -info: Entering event queue @ 1031250023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1032250023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1033250023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1034250023000. Starting simulation... -switching cpus -info: Entering event queue @ 1035156273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1036156273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1037156273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1038156273000. Starting simulation... -switching cpus -info: Entering event queue @ 1039062523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1040062523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1041062523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1042062523000. Starting simulation... -switching cpus -info: Entering event queue @ 1042968773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1043968773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1044968773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1045968773000. Starting simulation... -switching cpus -info: Entering event queue @ 1046875023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1047875023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1048875023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1049875023000. Starting simulation... -switching cpus -info: Entering event queue @ 1050781273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1051781273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1052781273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1053781273000. Starting simulation... -switching cpus -info: Entering event queue @ 1054687523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1055687523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1056687523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1057687523000. Starting simulation... -switching cpus -info: Entering event queue @ 1058593773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1059593773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1060593773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1061593773000. Starting simulation... -switching cpus -info: Entering event queue @ 1062500023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1063500023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1064500023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1065500023000. Starting simulation... -switching cpus -info: Entering event queue @ 1066406273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1067406273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1068406273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1069406273000. Starting simulation... -switching cpus -info: Entering event queue @ 1070312523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1071312523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1072312523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1073312523000. Starting simulation... -switching cpus -info: Entering event queue @ 1074218773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1075218773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1076218773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1077218773000. Starting simulation... -switching cpus -info: Entering event queue @ 1078125023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1079125023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1080125023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1081125023000. Starting simulation... -switching cpus -info: Entering event queue @ 1082031273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1083031273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1084031273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1085031273000. Starting simulation... -switching cpus -info: Entering event queue @ 1085937523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1086937523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1087937523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1088937523000. Starting simulation... -switching cpus -info: Entering event queue @ 1089843773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1090843773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1091843773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1092843773000. Starting simulation... -switching cpus -info: Entering event queue @ 1093750023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1094750023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1095750023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1096750023000. Starting simulation... -switching cpus -info: Entering event queue @ 1097656273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1098656273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1099656273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1100656273000. Starting simulation... -switching cpus -info: Entering event queue @ 1101562523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1102562523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1103562523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1104562523000. Starting simulation... -switching cpus -info: Entering event queue @ 1105468773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1106468773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1107468773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1108468773000. Starting simulation... -switching cpus -info: Entering event queue @ 1109375023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1110375023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1111375023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1112375023000. Starting simulation... -switching cpus -info: Entering event queue @ 1113281273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1114281273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1115281273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1116281273000. Starting simulation... -switching cpus -info: Entering event queue @ 1117187523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1118187523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1119187523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1120187523000. Starting simulation... -switching cpus -info: Entering event queue @ 1121093773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1122093773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1123093773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1124093773000. Starting simulation... -switching cpus -info: Entering event queue @ 1125000023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1126000023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1127000023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1128000023000. Starting simulation... -switching cpus -info: Entering event queue @ 1128906273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1129906273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1130906273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1131906273000. Starting simulation... -switching cpus -info: Entering event queue @ 1132812523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1133812523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1134812523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1135812523000. Starting simulation... -switching cpus -info: Entering event queue @ 1136718773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1137718773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1138718773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1139718773000. Starting simulation... -switching cpus -info: Entering event queue @ 1140625023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1141625023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1142625023000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1143625023000. Starting simulation... -switching cpus -info: Entering event queue @ 1144531273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1145531273000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1146531273000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1147531273000. Starting simulation... -switching cpus -info: Entering event queue @ 1148437523000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1149437523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1150437523000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1151437523000. Starting simulation... -switching cpus -info: Entering event queue @ 1152343773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1153343773000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1154343773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1155343773000. Starting simulation... -switching cpus -info: Entering event queue @ 1156250023000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1157250023000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1158250023000. Starting simulation... -switching cpus -info: Entering event queue @ 1158250030500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1159250030500. Starting simulation... -switching cpus -info: Entering event queue @ 1160338579500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1161338579500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1162338579500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1163338579500. Starting simulation... -switching cpus -info: Entering event queue @ 1163338582500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1164338582500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1165338582500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1166338582500. Starting simulation... -switching cpus -info: Entering event queue @ 1166338585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1167338585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1168338585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1169338585500. Starting simulation... -switching cpus -info: Entering event queue @ 1169921898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1170921898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1171921898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1172921898000. Starting simulation... -switching cpus -info: Entering event queue @ 1173828148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1174828148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1175828148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1176828148000. Starting simulation... -switching cpus -info: Entering event queue @ 1177734398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1178734398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1179734398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1180734398000. Starting simulation... -switching cpus -info: Entering event queue @ 1181640648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1182640648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1183640648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1184640648000. Starting simulation... -switching cpus -info: Entering event queue @ 1185546898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1186546898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1187546898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1188546898000. Starting simulation... -switching cpus -info: Entering event queue @ 1189453148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1190453148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1191453148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1192453148000. Starting simulation... -switching cpus -info: Entering event queue @ 1193359398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1194359398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1195359398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1196359398000. Starting simulation... -switching cpus -info: Entering event queue @ 1197265648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1198265648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1199265648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1200265648000. Starting simulation... -switching cpus -info: Entering event queue @ 1201171898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1202171898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1203171898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1204171898000. Starting simulation... -switching cpus -info: Entering event queue @ 1205078148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1206078148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1207078148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1208078148000. Starting simulation... -switching cpus -info: Entering event queue @ 1208984398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1209984398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1210984398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1211984398000. Starting simulation... -switching cpus -info: Entering event queue @ 1212890648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1213890648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1214890648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1215890648000. Starting simulation... -switching cpus -info: Entering event queue @ 1216796898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1217796898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1218796898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1219796898000. Starting simulation... -switching cpus -info: Entering event queue @ 1220703148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1221703148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1222703148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1223703148000. Starting simulation... -switching cpus -info: Entering event queue @ 1224609398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1225609398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1226609398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1227609398000. Starting simulation... -switching cpus -info: Entering event queue @ 1228515648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1229515648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1230515648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1231515648000. Starting simulation... -switching cpus -info: Entering event queue @ 1232421898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1233421898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1234421898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1235421898000. Starting simulation... -switching cpus -info: Entering event queue @ 1236328148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1237328148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1238328148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1239328148000. Starting simulation... -switching cpus -info: Entering event queue @ 1240234398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1241234398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1242234398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1243234398000. Starting simulation... -switching cpus -info: Entering event queue @ 1244140648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1245140648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1246140648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1247140648000. Starting simulation... -switching cpus -info: Entering event queue @ 1248046898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1249046898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1250046898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1251046898000. Starting simulation... -switching cpus -info: Entering event queue @ 1251953148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1252953148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1253953148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1254953148000. Starting simulation... -switching cpus -info: Entering event queue @ 1255859398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1256859398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1257859398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1258859398000. Starting simulation... -switching cpus -info: Entering event queue @ 1259765648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1260765648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1261765648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1262765648000. Starting simulation... -switching cpus -info: Entering event queue @ 1263671898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1264671898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1265671898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1266671898000. Starting simulation... -switching cpus -info: Entering event queue @ 1267578148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1268578148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1269578148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1270578148000. Starting simulation... -switching cpus -info: Entering event queue @ 1271484398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1272484398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1273484398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1274484398000. Starting simulation... -switching cpus -info: Entering event queue @ 1275390648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1276390648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1277390648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1278390648000. Starting simulation... -switching cpus -info: Entering event queue @ 1279296898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1280296898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1281296898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1282296898000. Starting simulation... -switching cpus -info: Entering event queue @ 1283203148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1284203148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1285203148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1286203148000. Starting simulation... -switching cpus -info: Entering event queue @ 1287109398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1288109398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1289109398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1290109398000. Starting simulation... -switching cpus -info: Entering event queue @ 1291015648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1292015648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1293015648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1294015648000. Starting simulation... -switching cpus -info: Entering event queue @ 1294921898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1295921898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1296921898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1297921898000. Starting simulation... -switching cpus -info: Entering event queue @ 1298828148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1299828148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1300828148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1301828148000. Starting simulation... -switching cpus -info: Entering event queue @ 1302734398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1303734398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1304734398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1305734398000. Starting simulation... -switching cpus -info: Entering event queue @ 1306640648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1307640648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1308640648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1309640648000. Starting simulation... -switching cpus -info: Entering event queue @ 1310546898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1311546898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1312546898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1313546898000. Starting simulation... -switching cpus -info: Entering event queue @ 1314453148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1315453148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1316453148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1317453148000. Starting simulation... -switching cpus -info: Entering event queue @ 1318359398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1319359398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1320359398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1321359398000. Starting simulation... -switching cpus -info: Entering event queue @ 1322265648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1323265648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1324265648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1325265648000. Starting simulation... -switching cpus -info: Entering event queue @ 1326171898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1327171898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1328171898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1329171898000. Starting simulation... -switching cpus -info: Entering event queue @ 1330078148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1331078148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1332078148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1333078148000. Starting simulation... -switching cpus -info: Entering event queue @ 1333984398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1334984398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1335984398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1336984398000. Starting simulation... -switching cpus -info: Entering event queue @ 1337890648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1338890648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1339890648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1340890648000. Starting simulation... -switching cpus -info: Entering event queue @ 1341796898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1342796898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1343796898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1344796898000. Starting simulation... -switching cpus -info: Entering event queue @ 1345703148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1346703148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1347703148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1348703148000. Starting simulation... -switching cpus -info: Entering event queue @ 1349609398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1350609398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1351609398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1352609398000. Starting simulation... -switching cpus -info: Entering event queue @ 1353515648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1354515648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1355515648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1356515648000. Starting simulation... -switching cpus -info: Entering event queue @ 1357421898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1358421898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1359421898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1360421898000. Starting simulation... -switching cpus -info: Entering event queue @ 1361328148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1362328148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1363328148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1364328148000. Starting simulation... -switching cpus -info: Entering event queue @ 1365234398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1366234398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1367234398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1368234398000. Starting simulation... -switching cpus -info: Entering event queue @ 1369140648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1370140648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1371140648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1372140648000. Starting simulation... -switching cpus -info: Entering event queue @ 1373046898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1374046898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1375046898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1376046898000. Starting simulation... -switching cpus -info: Entering event queue @ 1376953148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1377953148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1378953148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1379953148000. Starting simulation... -switching cpus -info: Entering event queue @ 1380859398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1381859398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1382859398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1383859398000. Starting simulation... -switching cpus -info: Entering event queue @ 1384765648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1385765648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1386765648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1387765648000. Starting simulation... -switching cpus -info: Entering event queue @ 1388671898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1389671898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1390671898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1391671898000. Starting simulation... -switching cpus -info: Entering event queue @ 1392578148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1393578148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1394578148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1395578148000. Starting simulation... -switching cpus -info: Entering event queue @ 1396484398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1397484398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1398484398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1399484398000. Starting simulation... -switching cpus -info: Entering event queue @ 1400390648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1401390648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1402390648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1403390648000. Starting simulation... -switching cpus -info: Entering event queue @ 1404296898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1405296898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1406296898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1407296898000. Starting simulation... -switching cpus -info: Entering event queue @ 1408203148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1409203148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1410203148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1411203148000. Starting simulation... -switching cpus -info: Entering event queue @ 1412109398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1413109398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1414109398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1415109398000. Starting simulation... -switching cpus -info: Entering event queue @ 1416015648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1417015648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1418015648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1419015648000. Starting simulation... -switching cpus -info: Entering event queue @ 1419921898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1420921898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1421921898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1422921898000. Starting simulation... -switching cpus -info: Entering event queue @ 1423828148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1424828148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1425828148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1426828148000. Starting simulation... -switching cpus -info: Entering event queue @ 1427734398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1428734398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1429734398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1430734398000. Starting simulation... -switching cpus -info: Entering event queue @ 1431640648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1432640648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1433640648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1434640648000. Starting simulation... -switching cpus -info: Entering event queue @ 1435546898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1436546898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1437546898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1438546898000. Starting simulation... -switching cpus -info: Entering event queue @ 1439453148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1440453148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1441453148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1442453148000. Starting simulation... -switching cpus -info: Entering event queue @ 1443359398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1444359398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1445359398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1446359398000. Starting simulation... -switching cpus -info: Entering event queue @ 1447265648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1448265648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1449265648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1450265648000. Starting simulation... -switching cpus -info: Entering event queue @ 1451171898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1452171898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1453171898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1454171898000. Starting simulation... -switching cpus -info: Entering event queue @ 1455078148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1456078148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1457078148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1458078148000. Starting simulation... -switching cpus -info: Entering event queue @ 1458984398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1459984398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1460984398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1461984398000. Starting simulation... -switching cpus -info: Entering event queue @ 1462890648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1463890648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1464890648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1465890648000. Starting simulation... -switching cpus -info: Entering event queue @ 1466796898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1467796898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1468796898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1469796898000. Starting simulation... -switching cpus -info: Entering event queue @ 1470703148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1471703148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1472703148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1473703148000. Starting simulation... -switching cpus -info: Entering event queue @ 1474609398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1475609398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1476609398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1477609398000. Starting simulation... -switching cpus -info: Entering event queue @ 1478515648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1479515648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1480515648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1481515648000. Starting simulation... -switching cpus -info: Entering event queue @ 1482421898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1483421898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1484421898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1485421898000. Starting simulation... -switching cpus -info: Entering event queue @ 1486328148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1487328148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1488328148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1489328148000. Starting simulation... -switching cpus -info: Entering event queue @ 1490234398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1491234398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1492234398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1493234398000. Starting simulation... -switching cpus -info: Entering event queue @ 1494140648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1495140648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1496140648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1497140648000. Starting simulation... -switching cpus -info: Entering event queue @ 1498046898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1499046898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1500046898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1501046898000. Starting simulation... -switching cpus -info: Entering event queue @ 1501953148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1502953148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1503953148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1504953148000. Starting simulation... -switching cpus -info: Entering event queue @ 1505859398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1506859398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1507859398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1508859398000. Starting simulation... -switching cpus -info: Entering event queue @ 1509765648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1510765648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1511765648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1512765648000. Starting simulation... -switching cpus -info: Entering event queue @ 1513671898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1514671898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1515671898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1516671898000. Starting simulation... -switching cpus -info: Entering event queue @ 1517578148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1518578148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1519578148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1520578148000. Starting simulation... -switching cpus -info: Entering event queue @ 1521484398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1522484398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1523484398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1524484398000. Starting simulation... -switching cpus -info: Entering event queue @ 1525390648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1526390648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1527390648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1528390648000. Starting simulation... -switching cpus -info: Entering event queue @ 1529296898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1530296898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1531296898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1532296898000. Starting simulation... -switching cpus -info: Entering event queue @ 1533203148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1534203148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1535203148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1536203148000. Starting simulation... -switching cpus -info: Entering event queue @ 1537109398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1538109398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1539109398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1540109398000. Starting simulation... -switching cpus -info: Entering event queue @ 1541015648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1542015648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1543015648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1544015648000. Starting simulation... -switching cpus -info: Entering event queue @ 1544921898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1545921898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1546921898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1547921898000. Starting simulation... -switching cpus -info: Entering event queue @ 1548828148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1549828148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1550828148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1551828148000. Starting simulation... -switching cpus -info: Entering event queue @ 1552734398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1553734398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1554734398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1555734398000. Starting simulation... -switching cpus -info: Entering event queue @ 1556640648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1557640648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1558640648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1559640648000. Starting simulation... -switching cpus -info: Entering event queue @ 1560546898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1561546898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1562546898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1563546898000. Starting simulation... -switching cpus -info: Entering event queue @ 1564453148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1565453148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1566453148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1567453148000. Starting simulation... -switching cpus -info: Entering event queue @ 1568359398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1569359398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1570359398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1571359398000. Starting simulation... -switching cpus -info: Entering event queue @ 1572265648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1573265648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1574265648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1575265648000. Starting simulation... -switching cpus -info: Entering event queue @ 1576171898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1577171898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1578171898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1579171898000. Starting simulation... -switching cpus -info: Entering event queue @ 1580078148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1581078148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1582078148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1583078148000. Starting simulation... -switching cpus -info: Entering event queue @ 1583984398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1584984398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1585984398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1586984398000. Starting simulation... -switching cpus -info: Entering event queue @ 1587890648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1588890648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1589890648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1590890648000. Starting simulation... -switching cpus -info: Entering event queue @ 1591796898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1592796898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1593796898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1594796898000. Starting simulation... -switching cpus -info: Entering event queue @ 1595703148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1596703148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1597703148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1598703148000. Starting simulation... -switching cpus -info: Entering event queue @ 1599609398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1600609398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1601609398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1602609398000. Starting simulation... -switching cpus -info: Entering event queue @ 1603515648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1604515648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1605515648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1606515648000. Starting simulation... -switching cpus -info: Entering event queue @ 1607421898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1608421898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1609421898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1610421898000. Starting simulation... -switching cpus -info: Entering event queue @ 1611328148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1612328148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1613328148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1614328148000. Starting simulation... -switching cpus -info: Entering event queue @ 1615234398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1616234398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1617234398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1618234398000. Starting simulation... -switching cpus -info: Entering event queue @ 1619140648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1620140648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1621140648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1622140648000. Starting simulation... -switching cpus -info: Entering event queue @ 1623046898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1624046898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1625046898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1626046898000. Starting simulation... -switching cpus -info: Entering event queue @ 1626953148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1627953148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1628953148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1629953148000. Starting simulation... -switching cpus -info: Entering event queue @ 1630859398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1631859398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1632859398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1633859398000. Starting simulation... -switching cpus -info: Entering event queue @ 1634765648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1635765648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1636765648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1637765648000. Starting simulation... -switching cpus -info: Entering event queue @ 1638671898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1639671898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1640671898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1641671898000. Starting simulation... -switching cpus -info: Entering event queue @ 1642578148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1643578148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1644578148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1645578148000. Starting simulation... -switching cpus -info: Entering event queue @ 1646484398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1647484398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1648484398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1649484398000. Starting simulation... -switching cpus -info: Entering event queue @ 1650390648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1651390648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1652390648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1653390648000. Starting simulation... -switching cpus -info: Entering event queue @ 1654296898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1655296898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1656296898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1657296898000. Starting simulation... -switching cpus -info: Entering event queue @ 1658203148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1659203148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1660203148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1661203148000. Starting simulation... -switching cpus -info: Entering event queue @ 1662109398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1663109398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1664109398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1665109398000. Starting simulation... -switching cpus -info: Entering event queue @ 1666015648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1667015648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1668015648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1669015648000. Starting simulation... -switching cpus -info: Entering event queue @ 1669921898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1670921898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1671921898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1672921898000. Starting simulation... -switching cpus -info: Entering event queue @ 1673828148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1674828148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1675828148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1676828148000. Starting simulation... -switching cpus -info: Entering event queue @ 1677734398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1678734398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1679734398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1680734398000. Starting simulation... -switching cpus -info: Entering event queue @ 1681640648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1682640648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1683640648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1684640648000. Starting simulation... -switching cpus -info: Entering event queue @ 1685546898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1686546898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1687546898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1688546898000. Starting simulation... -switching cpus -info: Entering event queue @ 1689453148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1690453148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1691453148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1692453148000. Starting simulation... -switching cpus -info: Entering event queue @ 1693359398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1694359398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1695359398000. Starting simulation... -switching cpus -info: Entering event queue @ 1695359405500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1696359405500. Starting simulation... -switching cpus -info: Entering event queue @ 1697265648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1698265648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1699265648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1700265648000. Starting simulation... -switching cpus -info: Entering event queue @ 1701171898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1702171898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1703171898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1704171898000. Starting simulation... -switching cpus -info: Entering event queue @ 1705078148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1706078148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1707078148000. Starting simulation... -switching cpus -info: Entering event queue @ 1707078155500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1708078155500. Starting simulation... -switching cpus -info: Entering event queue @ 1708984398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1709984398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1710984398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1711984398000. Starting simulation... -switching cpus -info: Entering event queue @ 1712890648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1713890648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1714890648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1715890648000. Starting simulation... -switching cpus -info: Entering event queue @ 1716796898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1717796898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1718796898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1719796898000. Starting simulation... -switching cpus -info: Entering event queue @ 1720703148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1721703148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1722703148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1723703148000. Starting simulation... -switching cpus -info: Entering event queue @ 1724609398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1725609398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1726609398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1727609398000. Starting simulation... -switching cpus -info: Entering event queue @ 1728515648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1729515648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1730515648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1731515648000. Starting simulation... -switching cpus -info: Entering event queue @ 1732421898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1733421898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1734421898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1735421898000. Starting simulation... -switching cpus -info: Entering event queue @ 1736328148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1737328148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1738328148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1739328148000. Starting simulation... -switching cpus -info: Entering event queue @ 1740234398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1741234398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1742234398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1743234398000. Starting simulation... -switching cpus -info: Entering event queue @ 1744140648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1745140648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1746140648000. Starting simulation... -switching cpus -info: Entering event queue @ 1746140655500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1747140655500. Starting simulation... -switching cpus -info: Entering event queue @ 1748046898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1749046898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1750046898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1751046898000. Starting simulation... -switching cpus -info: Entering event queue @ 1751953148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1752953148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1753953148000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1754953148000. Starting simulation... -switching cpus -info: Entering event queue @ 1755859398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1756859398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1757859398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1758859398000. Starting simulation... -switching cpus -info: Entering event queue @ 1759765648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1760765648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1761765648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1762765648000. Starting simulation... -switching cpus -info: Entering event queue @ 1763671898000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1764671898000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1765671898000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1766671898000. Starting simulation... -switching cpus -info: Entering event queue @ 1767578148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1768578148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1769578148000. Starting simulation... -switching cpus -info: Entering event queue @ 1769578155500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1770578155500. Starting simulation... -switching cpus -info: Entering event queue @ 1771484398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1772484398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1773484398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1774484398000. Starting simulation... -switching cpus -info: Entering event queue @ 1775390648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1776390648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1777390648000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1778390648000. Starting simulation... -switching cpus -info: Entering event queue @ 1778390871500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1779390871500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1780390871500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1781390871500. Starting simulation... -switching cpus -info: Entering event queue @ 1782226585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1783226585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1784226585500. Starting simulation... -switching cpus -info: Entering event queue @ 1784226593000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1785226593000. Starting simulation... -switching cpus -info: Entering event queue @ 1786132835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1787132835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1788132835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1789132835500. Starting simulation... -switching cpus -info: Entering event queue @ 1790039085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1791039085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1792039085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1793039085500. Starting simulation... -switching cpus -info: Entering event queue @ 1793945335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1794945335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1795945335500. Starting simulation... -switching cpus -info: Entering event queue @ 1795945343000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1796945343000. Starting simulation... -switching cpus -info: Entering event queue @ 1797851585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1798851585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1799851585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1800851585500. Starting simulation... -switching cpus -info: Entering event queue @ 1801757835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1802757835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1803757835500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1804757835500. Starting simulation... -switching cpus -info: Entering event queue @ 1805664085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1806664085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1807664085500. Starting simulation... -switching cpus -info: Entering event queue @ 1807664093000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1808664093000. Starting simulation... -switching cpus -info: Entering event queue @ 1809570335500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1810570335500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1811570335500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1812570335500. Starting simulation... -switching cpus -info: Entering event queue @ 1813476585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1814476585500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1815476585500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1816476585500. Starting simulation... -switching cpus -info: Entering event queue @ 1817382835500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1818382835500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1819382835500. Starting simulation... -switching cpus -info: Entering event queue @ 1819382844500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1820382844500. Starting simulation... -switching cpus -info: Entering event queue @ 1820383742000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1821383742000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1822383742000. Starting simulation... -switching cpus -info: Entering event queue @ 1822383749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1823383749500. Starting simulation... -info: Entering event queue @ 1823383883000. Starting simulation... -switching cpus -info: Entering event queue @ 1823383890500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1824383890500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1825383890500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1826383890500. Starting simulation... -switching cpus -info: Entering event queue @ 1827148460500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1828148460500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1829148460500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1830148460500. Starting simulation... -info: Entering event queue @ 1830148471500. Starting simulation... -info: Entering event queue @ 1830148476000. Starting simulation... -switching cpus -info: Entering event queue @ 1830148477000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1831148477000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1832148477000. Starting simulation... -info: Entering event queue @ 1832148513000. Starting simulation... -switching cpus -info: Entering event queue @ 1832148757750. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1833148757750. Starting simulation... -switching cpus -info: Entering event queue @ 1833984398000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1834984398000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1835984398000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1836984398000. Starting simulation... -switching cpus -info: Entering event queue @ 1837890648000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1838890648000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1839890648000. Starting simulation... -switching cpus -info: Entering event queue @ 1839890655500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1840890655500. Starting simulation... -info: Entering event queue @ 1840890668000. Starting simulation... -info: Entering event queue @ 1840890674500. Starting simulation... -switching cpus -info: Entering event queue @ 1840890679000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1841890679000. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index caa1e9081..3ead642aa 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.842697 # Nu sim_ticks 1842697218000 # Number of ticks simulated final_tick 1842697218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189301 # Simulator instruction rate (inst/s) -host_op_rate 189301 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4767309141 # Simulator tick rate (ticks/s) -host_mem_usage 353980 # Number of bytes of host memory used -host_seconds 386.53 # Real time elapsed on the host +host_inst_rate 281851 # Simulator instruction rate (inst/s) +host_op_rate 281851 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7098045398 # Simulator tick rate (ticks/s) +host_mem_usage 310872 # Number of bytes of host memory used +host_seconds 259.61 # Real time elapsed on the host sim_insts 73170192 # Number of instructions simulated sim_ops 73170192 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 489152 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 20102912 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2652352 # Number of bytes read from this memory @@ -375,6 +377,7 @@ system.membus.respLayer1.occupancy 764298954 # La system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 152995500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 337398 # number of replacements system.l2c.tags.tagsinuse 65420.701532 # Cycle average of tags in use system.l2c.tags.total_refs 2472173 # Total number of references to valid blocks. @@ -396,6 +399,15 @@ system.l2c.tags.occ_percent::cpu1.data 0.009495 # Av system.l2c.tags.occ_percent::cpu2.inst 0.032789 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.031610 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.998241 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 988 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5636 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2991 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55380 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26143118 # Number of tag accesses +system.l2c.tags.data_accesses 26143118 # Number of data accesses system.l2c.ReadReq_hits::cpu0.inst 520243 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 493553 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 124286 # number of ReadReq hits @@ -676,6 +688,11 @@ system.iocache.tags.warmup_cycle 1694870354000 # C system.iocache.tags.occ_blocks::tsunami.ide 1.254904 # Average occupied blocks per requestor system.iocache.tags.occ_percent::tsunami.ide 0.078431 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.078431 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -1026,6 +1043,13 @@ system.cpu0.icache.tags.occ_percent::cpu0.inst 0.490904 system.cpu0.icache.tags.occ_percent::cpu1.inst 0.194517 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu2.inst 0.312998 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.998419 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 45349405 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 45349405 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 33358489 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 7831408 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2239644 # number of ReadReq hits @@ -1156,6 +1180,13 @@ system.cpu0.dcache.tags.occ_percent::cpu0.data 0.487132 system.cpu0.dcache.tags.occ_percent::cpu1.data 0.257733 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu2.data 0.255131 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 63261634 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63261634 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 4082373 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 1085171 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 2396693 # number of ReadReq hits @@ -1763,7 +1794,7 @@ system.cpu2.int_regfile_reads 42582766 # nu system.cpu2.int_regfile_writes 22654603 # number of integer regfile writes system.cpu2.fp_regfile_reads 67639 # number of floating regfile reads system.cpu2.fp_regfile_writes 67817 # number of floating regfile writes -system.cpu2.misc_regfile_reads 5347337 # number of misc regfile reads +system.cpu2.misc_regfile_reads 5361637 # number of misc regfile reads system.cpu2.misc_regfile_writes 256988 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini index 25f2809e1..d2896598b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,7 +23,7 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -288,6 +288,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -304,6 +305,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] @@ -643,6 +645,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -659,6 +662,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] @@ -713,6 +717,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -729,6 +734,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] @@ -782,6 +788,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -798,6 +805,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr index 90faba56d..ccd250823 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr @@ -1,7 +1,6 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -11,22 +10,25 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented -warn: 6117297500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 -warn: 6125706500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 -warn: 6160975500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 -warn: 6176055500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 -warn: 6715294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 +warn: 6165886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748 +warn: 6172734500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708 +warn: 6181171500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8 +warn: 6216960500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608 +warn: 6232347500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8 +warn: 6775306000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8 warn: LCD dual screen mode not supported -warn: 51807478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 +warn: 51869237500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04 warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -warn: 2474714862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 -warn: 2488540668500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2489750451500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 -warn: 2510845218000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2511359133500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 -warn: 2517064152000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 -warn: 2517573704500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 -warn: 2518135055000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 -warn: 2518136146000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 -hack: be nice to actually delete the event here +warn: 2475417694000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0 +warn: 2489281853500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2490491047500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0 +warn: 2511643992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2512158375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0 +warn: 2516381302500: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0 +warn: 2516399186500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10 +warn: 2517881609000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0 +warn: 2518389750000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0 +warn: 2518949430500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0 +warn: 2518950618000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0 +warn: 2519498238000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout index 6df74fa42..a9e6de1f3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:31:27 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 23 2014 00:07:43 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2524309551500 because m5_exit instruction encountered +Exiting @ tick 2525131633500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index d7c49d42e..e81d47f63 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.525132 # Nu sim_ticks 2525131633500 # Number of ticks simulated final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 41051 # Simulator instruction rate (inst/s) -host_op_rate 52821 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1718892257 # Simulator tick rate (ticks/s) -host_mem_usage 447424 # Number of bytes of host memory used -host_seconds 1469.05 # Real time elapsed on the host +host_inst_rate 63748 # Simulator instruction rate (inst/s) +host_op_rate 82026 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2669254242 # Simulator tick rate (ticks/s) +host_mem_usage 403420 # Number of bytes of host memory used +host_seconds 946.01 # Real time elapsed on the host sim_insts 60305678 # Number of instructions simulated sim_ops 77596684 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory @@ -928,6 +930,7 @@ system.iobus.respLayer0.occupancy 2374785000 # La system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 14384927 # Number of BP lookups system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect @@ -958,8 +961,8 @@ system.cpu.checker.dtb.inst_accesses 0 # IT system.cpu.checker.dtb.hits 26214250 # DTB hits system.cpu.checker.dtb.misses 9498 # DTB misses system.cpu.checker.dtb.accesses 26223748 # DTB accesses -system.cpu.checker.itb.inst_hits 61479663 # ITB inst hits -system.cpu.checker.itb.inst_misses 4471 # ITB inst misses +system.cpu.checker.itb.inst_hits 61479661 # ITB inst hits +system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits @@ -968,7 +971,7 @@ system.cpu.checker.itb.flush_tlb 4 # Nu system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 4682 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_entries 4683 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions @@ -976,8 +979,8 @@ system.cpu.checker.itb.perms_faults 0 # Nu system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses system.cpu.checker.itb.inst_accesses 61484134 # ITB inst accesses -system.cpu.checker.itb.hits 61479663 # DTB hits -system.cpu.checker.itb.misses 4471 # DTB misses +system.cpu.checker.itb.hits 61479661 # DTB hits +system.cpu.checker.itb.misses 4473 # DTB misses system.cpu.checker.itb.accesses 61484134 # DTB accesses system.cpu.checker.numCycles 77882476 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started @@ -1332,6 +1335,14 @@ system.cpu.icache.tags.warmup_cycle 6918450250 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 12500309 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12500309 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits @@ -1432,6 +1443,19 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124721 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.095140 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.783737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6962 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54965 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18784884 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18784884 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52523 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10409 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 967861 # number of ReadReq hits @@ -1687,6 +1711,13 @@ system.cpu.dcache.tags.warmup_cycle 42430250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 101519243 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101519243 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits @@ -1846,6 +1877,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 98e6f2256..5b8c35474 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,7 +23,7 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -204,6 +204,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -220,6 +221,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -559,6 +561,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -575,6 +578,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -738,6 +742,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags @@ -754,6 +759,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.dtb] @@ -1093,6 +1099,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags @@ -1109,6 +1116,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu1.interrupts] @@ -1188,6 +1196,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -1204,6 +1213,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -1221,6 +1231,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -1237,6 +1248,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 4ccac5e7b..5a43c8b18 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -1,7 +1,6 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -15,4 +14,3 @@ warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented -hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 5def9d861..8a51f6391 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:18:35 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 23 2014 00:17:38 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1104038330000 because m5_exit instruction encountered +Exiting @ tick 1104766159000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index fbdae72ae..3b2b0bf59 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.104766 # Nu sim_ticks 1104766159000 # Number of ticks simulated final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49697 # Simulator instruction rate (inst/s) -host_op_rate 63978 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 891289209 # Simulator tick rate (ticks/s) -host_mem_usage 450492 # Number of bytes of host memory used -host_seconds 1239.51 # Real time elapsed on the host +host_inst_rate 77156 # Simulator instruction rate (inst/s) +host_op_rate 99328 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1383749494 # Simulator tick rate (ticks/s) +host_mem_usage 406496 # Number of bytes of host memory used +host_seconds 798.39 # Real time elapsed on the host sim_insts 61600257 # Number of instructions simulated sim_ops 79301805 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory @@ -799,6 +801,7 @@ system.membus.respLayer1.occupancy 4838543340 # La system.membus.respLayer1.utilization 0.4 # Layer utilization (%) system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 72740 # number of replacements system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks. @@ -822,6 +825,18 @@ system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000130 system.l2c.tags.occ_percent::cpu1.inst 0.056491 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.057637 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.821841 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65179 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 312 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3125 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8680 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53038 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994553 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18564692 # Number of tag accesses +system.l2c.tags.data_accesses 18564692 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 22002 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 4348 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 385872 # number of ReadReq hits @@ -1696,8 +1711,8 @@ system.cpu0.int_regfile_reads 171854579 # nu system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads system.cpu0.fp_regfile_writes 904 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13012931 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451079 # number of misc regfile writes +system.cpu0.misc_regfile_reads 13200315 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451289 # number of misc regfile writes system.cpu0.icache.tags.replacements 392190 # number of replacements system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks. @@ -1707,6 +1722,14 @@ system.cpu0.icache.tags.warmup_cycle 7054061250 # Cy system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 4608911 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 4608911 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits @@ -1799,6 +1822,13 @@ system.cpu0.dcache.tags.warmup_cycle 43491250 # Cy system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.475838 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897414 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.897414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 314 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 45150578 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 45150578 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 5781234 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 5781234 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 3158881 # number of WriteReq hits @@ -2267,8 +2297,8 @@ system.cpu1.int_regfile_reads 384897666 # nu system.cpu1.int_regfile_writes 55271640 # number of integer regfile writes system.cpu1.fp_regfile_reads 5031 # number of floating regfile reads system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18454230 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405462 # number of misc regfile writes +system.cpu1.misc_regfile_reads 18630847 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405526 # number of misc regfile writes system.cpu1.icache.tags.replacements 595825 # number of replacements system.cpu1.icache.tags.tagsinuse 480.685801 # Cycle average of tags in use system.cpu1.icache.tags.total_refs 6935518 # Total number of references to valid blocks. @@ -2278,6 +2308,12 @@ system.cpu1.icache.tags.warmup_cycle 74918873000 # Cy system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.685801 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938839 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.938839 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 8173146 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 8173146 # Number of data accesses system.cpu1.icache.ReadReq_hits::cpu1.inst 6935518 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 6935518 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 6935518 # number of demand (read+write) hits @@ -2370,6 +2406,11 @@ system.cpu1.dcache.tags.warmup_cycle 70967078000 # Cy system.cpu1.dcache.tags.occ_blocks::cpu1.data 473.291027 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.924397 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.924397 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 354 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 58866831 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 58866831 # Number of data accesses system.cpu1.dcache.ReadReq_hits::cpu1.data 8309635 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 8309635 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 4139080 # number of WriteReq hits @@ -2529,6 +2570,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index 49d73e9a8..276d3e895 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,7 +23,7 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -204,6 +204,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -220,6 +221,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] @@ -559,6 +561,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -575,6 +578,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] @@ -629,6 +633,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -645,6 +650,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] @@ -698,6 +704,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -714,6 +721,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index eda827fb8..41742298b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -1,7 +1,6 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -14,4 +13,3 @@ warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented -hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index 3406cd0de..d1ec33d4f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:15:54 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 23 2014 00:04:18 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2524309551500 because m5_exit instruction encountered +Exiting @ tick 2525131633500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 65955f345..6bfde3aab 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.525132 # Nu sim_ticks 2525131633500 # Number of ticks simulated final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49653 # Simulator instruction rate (inst/s) -host_op_rate 63890 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2079077169 # Simulator tick rate (ticks/s) -host_mem_usage 446400 # Number of bytes of host memory used -host_seconds 1214.54 # Real time elapsed on the host +host_inst_rate 76415 # Simulator instruction rate (inst/s) +host_op_rate 98325 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3199664494 # Simulator tick rate (ticks/s) +host_mem_usage 402400 # Number of bytes of host memory used +host_seconds 789.19 # Real time elapsed on the host sim_insts 60305678 # Number of instructions simulated sim_ops 77596684 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory @@ -928,6 +930,7 @@ system.iobus.respLayer0.occupancy 2374785000 # La system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 14384927 # Number of BP lookups system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect @@ -1287,6 +1290,14 @@ system.cpu.icache.tags.warmup_cycle 6918450250 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 511.579102 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999178 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999178 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 12500309 # Number of tag accesses +system.cpu.icache.tags.data_accesses 12500309 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits @@ -1387,6 +1398,19 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124721 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.095140 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.783737 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65375 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3055 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6962 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54965 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997543 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18784884 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18784884 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 52523 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10409 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 967861 # number of ReadReq hits @@ -1642,6 +1666,13 @@ system.cpu.dcache.tags.warmup_cycle 42430250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 101519243 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 101519243 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits @@ -1801,6 +1832,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 745161c28..bf231cd78 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,12 +23,12 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -137,6 +137,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -153,6 +154,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -185,6 +187,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -201,6 +204,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -819,6 +823,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -835,6 +840,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -852,6 +858,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -868,6 +875,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index b4a6065b7..d17b0e3b6 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -1,14 +1,12 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. warn: The ccsidr register isn't implemented and always reads as 0. warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented -hack: be nice to actually delete the event here warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented @@ -27,3 +25,5 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 7de6a94c3..05714643f 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,4144 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:10:22 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 23 2014 00:23:40 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 -info: Using bootloader at address 0x80000000 -info: Entering event queue @ 0. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1000000000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2000000000. Starting simulation... -switching cpus -info: Entering event queue @ 2000002000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3000002000. Starting simulation... -switching cpus -info: Entering event queue @ 3000005000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4000005000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5000005000. Starting simulation... -switching cpus -info: Entering event queue @ 5000005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 6000005500. Starting simulation... -switching cpus -info: Entering event queue @ 6000011500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 7000011500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 8000011500. Starting simulation... -switching cpus -info: Entering event queue @ 8000193000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 9000193000. Starting simulation... -switching cpus -info: Entering event queue @ 9000195500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 10000195500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 11000195500. Starting simulation... -switching cpus -info: Entering event queue @ 11000203000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 12000203000. Starting simulation... -switching cpus -info: Entering event queue @ 12000210500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 13000210500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 14000210500. Starting simulation... -switching cpus -info: Entering event queue @ 14000218000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 15000218000. Starting simulation... -switching cpus -info: Entering event queue @ 15000660500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 16000660500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 17000660500. Starting simulation... -switching cpus -info: Entering event queue @ 17000668000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 18000668000. Starting simulation... -info: Entering event queue @ 26061002500. Starting simulation... -info: Entering event queue @ 26061009000. Starting simulation... -switching cpus -info: Entering event queue @ 26061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 27061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 28061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 29061009500. Starting simulation... -info: Entering event queue @ 36061002500. Starting simulation... -info: Entering event queue @ 36061009000. Starting simulation... -switching cpus -info: Entering event queue @ 36061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 37061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 38061009500. Starting simulation... -switching cpus -info: Entering event queue @ 38061018500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 39061018500. Starting simulation... -info: Entering event queue @ 39061063500. Starting simulation... -switching cpus -info: Entering event queue @ 39061151000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 40061151000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 41061151000. Starting simulation... -switching cpus -info: Entering event queue @ 41061158500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 42061158500. Starting simulation... -info: Entering event queue @ 42061194500. Starting simulation... -switching cpus -info: Entering event queue @ 42061214750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 43061214750. Starting simulation... -switching cpus -info: Entering event queue @ 43061215000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 44061215000. Starting simulation... -switching cpus -info: Entering event queue @ 44061215500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 45061215500. Starting simulation... -info: Entering event queue @ 45061226000. Starting simulation... -switching cpus -info: Entering event queue @ 45061230500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 46061230500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 47061230500. Starting simulation... -switching cpus -info: Entering event queue @ 47061231000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 48061231000. Starting simulation... -info: Entering event queue @ 48061238500. Starting simulation... -info: Entering event queue @ 48061242500. Starting simulation... -switching cpus -info: Entering event queue @ 48061247000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 49061247000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 50061247000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 51061247000. Starting simulation... -info: Entering event queue @ 56061002500. Starting simulation... -info: Entering event queue @ 56061009500. Starting simulation... -switching cpus -info: Entering event queue @ 56061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 57061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 58061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 59061014000. Starting simulation... -info: Entering event queue @ 66061002500. Starting simulation... -info: Entering event queue @ 66061009000. Starting simulation... -switching cpus -info: Entering event queue @ 66061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 67061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 68061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 69061009500. Starting simulation... -info: Entering event queue @ 76061002500. Starting simulation... -info: Entering event queue @ 76061009500. Starting simulation... -switching cpus -info: Entering event queue @ 76061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 77061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 78061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 79061014000. Starting simulation... -info: Entering event queue @ 86061002500. Starting simulation... -info: Entering event queue @ 86061009000. Starting simulation... -switching cpus -info: Entering event queue @ 86061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 87061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 88061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 89061009500. Starting simulation... -info: Entering event queue @ 96061002500. Starting simulation... -info: Entering event queue @ 96061009000. Starting simulation... -switching cpus -info: Entering event queue @ 96061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 97061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 98061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 99061009500. Starting simulation... -info: Entering event queue @ 106061002500. Starting simulation... -info: Entering event queue @ 106061009000. Starting simulation... -switching cpus -info: Entering event queue @ 106061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 107061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 108061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 109061009500. Starting simulation... -info: Entering event queue @ 116061002500. Starting simulation... -info: Entering event queue @ 116061009000. Starting simulation... -switching cpus -info: Entering event queue @ 116061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 117061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 118061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 119061009500. Starting simulation... -info: Entering event queue @ 126061002500. Starting simulation... -info: Entering event queue @ 126061009500. Starting simulation... -switching cpus -info: Entering event queue @ 126061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 127061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 128061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 129061014000. Starting simulation... -info: Entering event queue @ 136061002500. Starting simulation... -info: Entering event queue @ 136206506250. Starting simulation... -switching cpus -info: Entering event queue @ 136206509000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 137206509000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 138206509000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 139206509000. Starting simulation... -info: Entering event queue @ 146061002500. Starting simulation... -info: Entering event queue @ 146061009500. Starting simulation... -switching cpus -info: Entering event queue @ 146061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 147061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 148061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 149061014000. Starting simulation... -info: Entering event queue @ 156061002500. Starting simulation... -info: Entering event queue @ 156061009000. Starting simulation... -switching cpus -info: Entering event queue @ 156061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 157061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 158061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 159061009500. Starting simulation... -info: Entering event queue @ 166061002500. Starting simulation... -info: Entering event queue @ 166061009000. Starting simulation... -switching cpus -info: Entering event queue @ 166061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 167061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 168061009500. Starting simulation... -info: Entering event queue @ 168904109250. Starting simulation... -switching cpus -info: Entering event queue @ 168904112000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 169904112000. Starting simulation... -info: Entering event queue @ 176061002500. Starting simulation... -info: Entering event queue @ 176061009000. Starting simulation... -switching cpus -info: Entering event queue @ 176061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 177061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 178061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 179061009500. Starting simulation... -info: Entering event queue @ 186061002500. Starting simulation... -info: Entering event queue @ 186061009500. Starting simulation... -switching cpus -info: Entering event queue @ 186061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 187061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 188061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 189061014000. Starting simulation... -info: Entering event queue @ 196061002500. Starting simulation... -info: Entering event queue @ 196061009500. Starting simulation... -switching cpus -info: Entering event queue @ 196061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 197061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 198061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 199061014000. Starting simulation... -info: Entering event queue @ 206061002500. Starting simulation... -info: Entering event queue @ 206061009000. Starting simulation... -switching cpus -info: Entering event queue @ 206061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 207061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 208061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 209061009500. Starting simulation... -info: Entering event queue @ 216061002500. Starting simulation... -info: Entering event queue @ 216061009500. Starting simulation... -switching cpus -info: Entering event queue @ 216061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 217061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 218061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 219061014000. Starting simulation... -info: Entering event queue @ 226061002500. Starting simulation... -info: Entering event queue @ 226061009000. Starting simulation... -switching cpus -info: Entering event queue @ 226061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 227061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 228061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 229061009500. Starting simulation... -info: Entering event queue @ 236061002500. Starting simulation... -info: Entering event queue @ 236061009500. Starting simulation... -switching cpus -info: Entering event queue @ 236061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 237061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 238061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 239061014000. Starting simulation... -info: Entering event queue @ 246061002500. Starting simulation... -info: Entering event queue @ 246061009000. Starting simulation... -switching cpus -info: Entering event queue @ 246061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 247061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 248061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 249061009500. Starting simulation... -info: Entering event queue @ 256061002500. Starting simulation... -info: Entering event queue @ 256061009000. Starting simulation... -switching cpus -info: Entering event queue @ 256061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 257061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 258061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 259061009500. Starting simulation... -info: Entering event queue @ 266061002500. Starting simulation... -info: Entering event queue @ 267151610250. Starting simulation... -switching cpus -info: Entering event queue @ 267151613000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 268151613000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 269151613000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 270151613000. Starting simulation... -info: Entering event queue @ 276061002500. Starting simulation... -info: Entering event queue @ 276061009000. Starting simulation... -switching cpus -info: Entering event queue @ 276061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 277061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 278061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 279061009500. Starting simulation... -info: Entering event queue @ 286061002500. Starting simulation... -info: Entering event queue @ 286061009500. Starting simulation... -switching cpus -info: Entering event queue @ 286061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 287061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 288061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 289061014000. Starting simulation... -info: Entering event queue @ 296061002500. Starting simulation... -info: Entering event queue @ 296061009500. Starting simulation... -switching cpus -info: Entering event queue @ 296061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 297061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 298061014000. Starting simulation... -info: Entering event queue @ 299887862250. Starting simulation... -switching cpus -info: Entering event queue @ 299887865000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 300887865000. Starting simulation... -info: Entering event queue @ 306061002500. Starting simulation... -info: Entering event queue @ 306061009500. Starting simulation... -switching cpus -info: Entering event queue @ 306061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 307061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 308061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 309061014000. Starting simulation... -info: Entering event queue @ 316061002500. Starting simulation... -info: Entering event queue @ 316061009000. Starting simulation... -switching cpus -info: Entering event queue @ 316061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 317061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 318061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 319061009500. Starting simulation... -info: Entering event queue @ 326061002500. Starting simulation... -info: Entering event queue @ 326061009000. Starting simulation... -switching cpus -info: Entering event queue @ 326061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 327061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 328061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 329061009500. Starting simulation... -info: Entering event queue @ 336061002500. Starting simulation... -info: Entering event queue @ 336061009000. Starting simulation... -switching cpus -info: Entering event queue @ 336061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 337061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 338061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 339061009500. Starting simulation... -info: Entering event queue @ 346061002500. Starting simulation... -info: Entering event queue @ 346061009500. Starting simulation... -switching cpus -info: Entering event queue @ 346061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 347061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 348061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 349061014000. Starting simulation... -info: Entering event queue @ 356061002500. Starting simulation... -info: Entering event queue @ 356061009500. Starting simulation... -switching cpus -info: Entering event queue @ 356061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 357061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 358061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 359061014000. Starting simulation... -info: Entering event queue @ 366061002500. Starting simulation... -info: Entering event queue @ 366061009000. Starting simulation... -switching cpus -info: Entering event queue @ 366061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 367061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 368061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 369061009500. Starting simulation... -info: Entering event queue @ 376061002500. Starting simulation... -info: Entering event queue @ 376061009500. Starting simulation... -switching cpus -info: Entering event queue @ 376061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 377061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 378061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 379061014000. Starting simulation... -info: Entering event queue @ 386061002500. Starting simulation... -info: Entering event queue @ 386061009000. Starting simulation... -switching cpus -info: Entering event queue @ 386061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 387061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 388061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 389061009500. Starting simulation... -info: Entering event queue @ 396061003500. Starting simulation... -info: Entering event queue @ 396061011000. Starting simulation... -switching cpus -info: Entering event queue @ 396061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 397061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 398061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 399061015500. Starting simulation... -info: Entering event queue @ 406061002500. Starting simulation... -info: Entering event queue @ 406061009000. Starting simulation... -switching cpus -info: Entering event queue @ 406061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 407061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 408061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 409061009500. Starting simulation... -info: Entering event queue @ 416061002500. Starting simulation... -info: Entering event queue @ 416061009000. Starting simulation... -switching cpus -info: Entering event queue @ 416061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 417061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 418061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 419061009500. Starting simulation... -info: Entering event queue @ 426061002500. Starting simulation... -info: Entering event queue @ 426061009000. Starting simulation... -switching cpus -info: Entering event queue @ 426061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 427061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 428061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 429061009500. Starting simulation... -info: Entering event queue @ 436061002500. Starting simulation... -info: Entering event queue @ 436061009000. Starting simulation... -switching cpus -info: Entering event queue @ 436061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 437061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 438061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 439061009500. Starting simulation... -info: Entering event queue @ 446061002500. Starting simulation... -info: Entering event queue @ 446061009500. Starting simulation... -switching cpus -info: Entering event queue @ 446061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 447061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 448061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 449061014000. Starting simulation... -info: Entering event queue @ 456061003500. Starting simulation... -info: Entering event queue @ 456061012000. Starting simulation... -switching cpus -info: Entering event queue @ 456061016500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 457061016500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 458061016500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 459061016500. Starting simulation... -info: Entering event queue @ 466061003500. Starting simulation... -info: Entering event queue @ 466061011000. Starting simulation... -switching cpus -info: Entering event queue @ 466061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 467061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 468061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 469061015500. Starting simulation... -info: Entering event queue @ 476061002500. Starting simulation... -info: Entering event queue @ 476061009000. Starting simulation... -switching cpus -info: Entering event queue @ 476061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 477061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 478061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 479061009500. Starting simulation... -info: Entering event queue @ 486061002500. Starting simulation... -info: Entering event queue @ 486061009000. Starting simulation... -switching cpus -info: Entering event queue @ 486061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 487061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 488061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 489061009500. Starting simulation... -info: Entering event queue @ 496061002500. Starting simulation... -info: Entering event queue @ 496305189250. Starting simulation... -switching cpus -info: Entering event queue @ 496305192000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 497305192000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 498305192000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 499305192000. Starting simulation... -info: Entering event queue @ 506061002500. Starting simulation... -info: Entering event queue @ 506061009500. Starting simulation... -switching cpus -info: Entering event queue @ 506061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 507061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 508061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 509061014000. Starting simulation... -info: Entering event queue @ 516061002500. Starting simulation... -info: Entering event queue @ 516061009500. Starting simulation... -switching cpus -info: Entering event queue @ 516061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 517061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 518061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 519061014000. Starting simulation... -info: Entering event queue @ 526061002500. Starting simulation... -info: Entering event queue @ 526061009000. Starting simulation... -switching cpus -info: Entering event queue @ 526061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 527061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 528061009500. Starting simulation... -info: Entering event queue @ 529041477250. Starting simulation... -switching cpus -info: Entering event queue @ 529041480000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 530041480000. Starting simulation... -info: Entering event queue @ 536061002500. Starting simulation... -info: Entering event queue @ 536061009500. Starting simulation... -switching cpus -info: Entering event queue @ 536061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 537061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 538061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 539061014000. Starting simulation... -info: Entering event queue @ 546061002500. Starting simulation... -info: Entering event queue @ 546061009000. Starting simulation... -switching cpus -info: Entering event queue @ 546061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 547061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 548061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 549061009500. Starting simulation... -info: Entering event queue @ 556061002500. Starting simulation... -info: Entering event queue @ 556061009500. Starting simulation... -switching cpus -info: Entering event queue @ 556061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 557061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 558061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 559061014000. Starting simulation... -info: Entering event queue @ 566061002500. Starting simulation... -info: Entering event queue @ 566061009000. Starting simulation... -switching cpus -info: Entering event queue @ 566061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 567061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 568061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 569061009500. Starting simulation... -info: Entering event queue @ 576061002500. Starting simulation... -info: Entering event queue @ 576061009000. Starting simulation... -switching cpus -info: Entering event queue @ 576061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 577061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 578061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 579061009500. Starting simulation... -info: Entering event queue @ 586061002500. Starting simulation... -info: Entering event queue @ 586061009000. Starting simulation... -switching cpus -info: Entering event queue @ 586061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 587061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 588061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 589061009500. Starting simulation... -info: Entering event queue @ 596061002500. Starting simulation... -info: Entering event queue @ 596061009000. Starting simulation... -switching cpus -info: Entering event queue @ 596061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 597061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 598061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 599061009500. Starting simulation... -info: Entering event queue @ 606061002500. Starting simulation... -info: Entering event queue @ 606061009500. Starting simulation... -switching cpus -info: Entering event queue @ 606061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 607061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 608061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 609061014000. Starting simulation... -info: Entering event queue @ 616061003500. Starting simulation... -info: Entering event queue @ 616061010500. Starting simulation... -switching cpus -info: Entering event queue @ 616061015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 617061015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 618061015000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 619061015000. Starting simulation... -info: Entering event queue @ 626061003500. Starting simulation... -info: Entering event queue @ 627250298250. Starting simulation... -switching cpus -info: Entering event queue @ 627250301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 628250301000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 629250301000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 630250301000. Starting simulation... -info: Entering event queue @ 636061002500. Starting simulation... -info: Entering event queue @ 636061009000. Starting simulation... -switching cpus -info: Entering event queue @ 636061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 637061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 638061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 639061009500. Starting simulation... -info: Entering event queue @ 646061002500. Starting simulation... -info: Entering event queue @ 646061009000. Starting simulation... -switching cpus -info: Entering event queue @ 646061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 647061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 648061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 649061009500. Starting simulation... -info: Entering event queue @ 656061002500. Starting simulation... -info: Entering event queue @ 656061009000. Starting simulation... -switching cpus -info: Entering event queue @ 656061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 657061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 658061009500. Starting simulation... -info: Entering event queue @ 659986582250. Starting simulation... -switching cpus -info: Entering event queue @ 659986585000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 660986585000. Starting simulation... -info: Entering event queue @ 666061002500. Starting simulation... -info: Entering event queue @ 666061009500. Starting simulation... -switching cpus -info: Entering event queue @ 666061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 667061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 668061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 669061014000. Starting simulation... -info: Entering event queue @ 676061002500. Starting simulation... -info: Entering event queue @ 676061009500. Starting simulation... -switching cpus -info: Entering event queue @ 676061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 677061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 678061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 679061014000. Starting simulation... -info: Entering event queue @ 686061002500. Starting simulation... -info: Entering event queue @ 686061009000. Starting simulation... -switching cpus -info: Entering event queue @ 686061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 687061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 688061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 689061009500. Starting simulation... -info: Entering event queue @ 696061002500. Starting simulation... -info: Entering event queue @ 696061009500. Starting simulation... -switching cpus -info: Entering event queue @ 696061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 697061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 698061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 699061014000. Starting simulation... -info: Entering event queue @ 706061002500. Starting simulation... -info: Entering event queue @ 706061009000. Starting simulation... -switching cpus -info: Entering event queue @ 706061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 707061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 708061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 709061009500. Starting simulation... -info: Entering event queue @ 716061002500. Starting simulation... -info: Entering event queue @ 716061009500. Starting simulation... -switching cpus -info: Entering event queue @ 716061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 717061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 718061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 719061014000. Starting simulation... -info: Entering event queue @ 726061002500. Starting simulation... -info: Entering event queue @ 726061009000. Starting simulation... -switching cpus -info: Entering event queue @ 726061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 727061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 728061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 729061009500. Starting simulation... -info: Entering event queue @ 736061002500. Starting simulation... -info: Entering event queue @ 736061009000. Starting simulation... -switching cpus -info: Entering event queue @ 736061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 737061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 738061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 739061009500. Starting simulation... -info: Entering event queue @ 746061002500. Starting simulation... -info: Entering event queue @ 746061009000. Starting simulation... -switching cpus -info: Entering event queue @ 746061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 747061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 748061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 749061009500. Starting simulation... -info: Entering event queue @ 756061002500. Starting simulation... -info: Entering event queue @ 756061009000. Starting simulation... -switching cpus -info: Entering event queue @ 756061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 757061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 758061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 759061009500. Starting simulation... -info: Entering event queue @ 766061002500. Starting simulation... -info: Entering event queue @ 766061009500. Starting simulation... -switching cpus -info: Entering event queue @ 766061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 767061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 768061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 769061014000. Starting simulation... -info: Entering event queue @ 776061002500. Starting simulation... -info: Entering event queue @ 776061009500. Starting simulation... -switching cpus -info: Entering event queue @ 776061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 777061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 778061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 779061014000. Starting simulation... -info: Entering event queue @ 786061002500. Starting simulation... -info: Entering event queue @ 786061009500. Starting simulation... -switching cpus -info: Entering event queue @ 786061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 787061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 788061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 789061014000. Starting simulation... -info: Entering event queue @ 796061002500. Starting simulation... -info: Entering event queue @ 796061009000. Starting simulation... -switching cpus -info: Entering event queue @ 796061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 797061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 798061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 799061009500. Starting simulation... -info: Entering event queue @ 806061002500. Starting simulation... -info: Entering event queue @ 806061009000. Starting simulation... -switching cpus -info: Entering event queue @ 806061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 807061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 808061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 809061009500. Starting simulation... -info: Entering event queue @ 816061002500. Starting simulation... -info: Entering event queue @ 816061009000. Starting simulation... -switching cpus -info: Entering event queue @ 816061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 817061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 818061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 819061009500. Starting simulation... -info: Entering event queue @ 826061002500. Starting simulation... -info: Entering event queue @ 826061009500. Starting simulation... -switching cpus -info: Entering event queue @ 826061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 827061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 828061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 829061014000. Starting simulation... -info: Entering event queue @ 836061002500. Starting simulation... -info: Entering event queue @ 836061009500. Starting simulation... -switching cpus -info: Entering event queue @ 836061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 837061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 838061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 839061014000. Starting simulation... -info: Entering event queue @ 846061002500. Starting simulation... -info: Entering event queue @ 846061009000. Starting simulation... -switching cpus -info: Entering event queue @ 846061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 847061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 848061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 849061009500. Starting simulation... -info: Entering event queue @ 856061002500. Starting simulation... -info: Entering event queue @ 856404222250. Starting simulation... -switching cpus -info: Entering event queue @ 856404225000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 857404225000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 858404225000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 859404225000. Starting simulation... -info: Entering event queue @ 866061002500. Starting simulation... -info: Entering event queue @ 866061009000. Starting simulation... -switching cpus -info: Entering event queue @ 866061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 867061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 868061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 869061009500. Starting simulation... -info: Entering event queue @ 876061002500. Starting simulation... -info: Entering event queue @ 876061009500. Starting simulation... -switching cpus -info: Entering event queue @ 876061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 877061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 878061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 879061014000. Starting simulation... -info: Entering event queue @ 886061002500. Starting simulation... -info: Entering event queue @ 886061009000. Starting simulation... -switching cpus -info: Entering event queue @ 886061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 887061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 888061009500. Starting simulation... -info: Entering event queue @ 889140509250. Starting simulation... -switching cpus -info: Entering event queue @ 889140512000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 890140512000. Starting simulation... -info: Entering event queue @ 896061002500. Starting simulation... -info: Entering event queue @ 896061009000. Starting simulation... -switching cpus -info: Entering event queue @ 896061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 897061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 898061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 899061009500. Starting simulation... -info: Entering event queue @ 906061002500. Starting simulation... -info: Entering event queue @ 906061009000. Starting simulation... -switching cpus -info: Entering event queue @ 906061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 907061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 908061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 909061009500. Starting simulation... -info: Entering event queue @ 916061002500. Starting simulation... -info: Entering event queue @ 916061009000. Starting simulation... -switching cpus -info: Entering event queue @ 916061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 917061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 918061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 919061009500. Starting simulation... -info: Entering event queue @ 926061002500. Starting simulation... -info: Entering event queue @ 926061009500. Starting simulation... -switching cpus -info: Entering event queue @ 926061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 927061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 928061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 929061014000. Starting simulation... -info: Entering event queue @ 936061003500. Starting simulation... -info: Entering event queue @ 936061010500. Starting simulation... -switching cpus -info: Entering event queue @ 936061015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 937061015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 938061015000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 939061015000. Starting simulation... -info: Entering event queue @ 946061003500. Starting simulation... -info: Entering event queue @ 946061011000. Starting simulation... -switching cpus -info: Entering event queue @ 946061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 947061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 948061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 949061015500. Starting simulation... -info: Entering event queue @ 956061002500. Starting simulation... -info: Entering event queue @ 956061009000. Starting simulation... -switching cpus -info: Entering event queue @ 956061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 957061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 958061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 959061009500. Starting simulation... -info: Entering event queue @ 966061002500. Starting simulation... -info: Entering event queue @ 966061009000. Starting simulation... -switching cpus -info: Entering event queue @ 966061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 967061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 968061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 969061009500. Starting simulation... -info: Entering event queue @ 976061002500. Starting simulation... -info: Entering event queue @ 976061009000. Starting simulation... -switching cpus -info: Entering event queue @ 976061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 977061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 978061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 979061009500. Starting simulation... -info: Entering event queue @ 986061003500. Starting simulation... -info: Entering event queue @ 987349326250. Starting simulation... -switching cpus -info: Entering event queue @ 987349329000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 988349329000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 989349329000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 990349329000. Starting simulation... -info: Entering event queue @ 996061002500. Starting simulation... -info: Entering event queue @ 996061009500. Starting simulation... -switching cpus -info: Entering event queue @ 996061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 997061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 998061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 999061014000. Starting simulation... -info: Entering event queue @ 1006061002500. Starting simulation... -info: Entering event queue @ 1006061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1006061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1007061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1008061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1009061009500. Starting simulation... -info: Entering event queue @ 1016061002500. Starting simulation... -info: Entering event queue @ 1016061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1016061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1017061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1018061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1019061014000. Starting simulation... -info: Entering event queue @ 1026061002500. Starting simulation... -info: Entering event queue @ 1026061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1026061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1027061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1028061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1029061009500. Starting simulation... -info: Entering event queue @ 1036061002500. Starting simulation... -info: Entering event queue @ 1036061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1036061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1037061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1038061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1039061014000. Starting simulation... -info: Entering event queue @ 1046061002500. Starting simulation... -info: Entering event queue @ 1046061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1046061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1047061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1048061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1049061009500. Starting simulation... -info: Entering event queue @ 1056061002500. Starting simulation... -info: Entering event queue @ 1056061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1056061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1057061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1058061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1059061009500. Starting simulation... -info: Entering event queue @ 1066061002500. Starting simulation... -info: Entering event queue @ 1066061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1066061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1067061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1068061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1069061009500. Starting simulation... -info: Entering event queue @ 1076061002500. Starting simulation... -info: Entering event queue @ 1076061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1076061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1077061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1078061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1079061009500. Starting simulation... -info: Entering event queue @ 1086061002500. Starting simulation... -info: Entering event queue @ 1086061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1086061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1087061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1088061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1089061014000. Starting simulation... -info: Entering event queue @ 1096061003500. Starting simulation... -info: Entering event queue @ 1096061010500. Starting simulation... -switching cpus -info: Entering event queue @ 1096061015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1097061015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1098061015000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1099061015000. Starting simulation... -info: Entering event queue @ 1106061003500. Starting simulation... -info: Entering event queue @ 1106061011000. Starting simulation... -switching cpus -info: Entering event queue @ 1106061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1107061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1108061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1109061015500. Starting simulation... -info: Entering event queue @ 1116061002500. Starting simulation... -info: Entering event queue @ 1116061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1116061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1117061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1118061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1119061009500. Starting simulation... -info: Entering event queue @ 1126061002500. Starting simulation... -info: Entering event queue @ 1126061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1126061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1127061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1128061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1129061009500. Starting simulation... -info: Entering event queue @ 1136061002500. Starting simulation... -info: Entering event queue @ 1136061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1136061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1137061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1138061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1139061009500. Starting simulation... -info: Entering event queue @ 1146061002500. Starting simulation... -info: Entering event queue @ 1146061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1146061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1147061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1148061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1149061014000. Starting simulation... -info: Entering event queue @ 1156061002500. Starting simulation... -info: Entering event queue @ 1156061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1156061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1157061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1158061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1159061014000. Starting simulation... -info: Entering event queue @ 1166061002500. Starting simulation... -info: Entering event queue @ 1166061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1166061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1167061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1168061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1169061009500. Starting simulation... -info: Entering event queue @ 1176061002500. Starting simulation... -info: Entering event queue @ 1176061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1176061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1177061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1178061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1179061014000. Starting simulation... -info: Entering event queue @ 1186061002500. Starting simulation... -info: Entering event queue @ 1186061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1186061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1187061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1188061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1189061009500. Starting simulation... -info: Entering event queue @ 1196061003500. Starting simulation... -info: Entering event queue @ 1196061011000. Starting simulation... -switching cpus -info: Entering event queue @ 1196061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1197061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1198061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1199061015500. Starting simulation... -info: Entering event queue @ 1206061002500. Starting simulation... -info: Entering event queue @ 1206061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1206061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1207061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1208061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1209061009500. Starting simulation... -info: Entering event queue @ 1216061002500. Starting simulation... -info: Entering event queue @ 1216502945250. Starting simulation... -switching cpus -info: Entering event queue @ 1216502948000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1217502948000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1218502948000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1219502948000. Starting simulation... -info: Entering event queue @ 1226061002500. Starting simulation... -info: Entering event queue @ 1226061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1226061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1227061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1228061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1229061009500. Starting simulation... -info: Entering event queue @ 1236061002500. Starting simulation... -info: Entering event queue @ 1236061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1236061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1237061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1238061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1239061009500. Starting simulation... -info: Entering event queue @ 1246061002500. Starting simulation... -info: Entering event queue @ 1246061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1246061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1247061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1248061014000. Starting simulation... -info: Entering event queue @ 1249239189250. Starting simulation... -switching cpus -info: Entering event queue @ 1249239192000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1250239192000. Starting simulation... -info: Entering event queue @ 1256061003500. Starting simulation... -info: Entering event queue @ 1256061010500. Starting simulation... -switching cpus -info: Entering event queue @ 1256061015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1257061015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1258061015000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1259061015000. Starting simulation... -info: Entering event queue @ 1266061003500. Starting simulation... -info: Entering event queue @ 1266061011000. Starting simulation... -switching cpus -info: Entering event queue @ 1266061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1267061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1268061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1269061015500. Starting simulation... -info: Entering event queue @ 1276061002500. Starting simulation... -info: Entering event queue @ 1276061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1276061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1277061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1278061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1279061009500. Starting simulation... -info: Entering event queue @ 1286061002500. Starting simulation... -info: Entering event queue @ 1286061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1286061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1287061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1288061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1289061009500. Starting simulation... -info: Entering event queue @ 1296061002500. Starting simulation... -info: Entering event queue @ 1296061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1296061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1297061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1298061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1299061009500. Starting simulation... -info: Entering event queue @ 1306061002500. Starting simulation... -info: Entering event queue @ 1306061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1306061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1307061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1308061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1309061014000. Starting simulation... -info: Entering event queue @ 1316061002500. Starting simulation... -info: Entering event queue @ 1316061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1316061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1317061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1318061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1319061014000. Starting simulation... -info: Entering event queue @ 1326061002500. Starting simulation... -info: Entering event queue @ 1326061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1326061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1327061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1328061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1329061009500. Starting simulation... -info: Entering event queue @ 1336061002500. Starting simulation... -info: Entering event queue @ 1336061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1336061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1337061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1338061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1339061014000. Starting simulation... -info: Entering event queue @ 1346061002500. Starting simulation... -info: Entering event queue @ 1347448013250. Starting simulation... -switching cpus -info: Entering event queue @ 1347448016000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1348448016000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1349448016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1350448016000. Starting simulation... -info: Entering event queue @ 1356061002500. Starting simulation... -info: Entering event queue @ 1356061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1356061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1357061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1358061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1359061014000. Starting simulation... -info: Entering event queue @ 1366061002500. Starting simulation... -info: Entering event queue @ 1366061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1366061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1367061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1368061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1369061009500. Starting simulation... -info: Entering event queue @ 1376061002500. Starting simulation... -info: Entering event queue @ 1376061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1376061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1377061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1378061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1379061009500. Starting simulation... -info: Entering event queue @ 1386061002500. Starting simulation... -info: Entering event queue @ 1386061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1386061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1387061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1388061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1389061009500. Starting simulation... -info: Entering event queue @ 1396061002500. Starting simulation... -info: Entering event queue @ 1396061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1396061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1397061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1398061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1399061009500. Starting simulation... -info: Entering event queue @ 1406061002500. Starting simulation... -info: Entering event queue @ 1406061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1406061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1407061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1408061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1409061014000. Starting simulation... -info: Entering event queue @ 1416061003500. Starting simulation... -info: Entering event queue @ 1416061010500. Starting simulation... -switching cpus -info: Entering event queue @ 1416061015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1417061015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1418061015000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1419061015000. Starting simulation... -info: Entering event queue @ 1426061003500. Starting simulation... -info: Entering event queue @ 1426061011000. Starting simulation... -switching cpus -info: Entering event queue @ 1426061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1427061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1428061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1429061015500. Starting simulation... -info: Entering event queue @ 1436061002500. Starting simulation... -info: Entering event queue @ 1436061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1436061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1437061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1438061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1439061009500. Starting simulation... -info: Entering event queue @ 1446061002500. Starting simulation... -info: Entering event queue @ 1446061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1446061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1447061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1448061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1449061009500. Starting simulation... -info: Entering event queue @ 1456061002500. Starting simulation... -info: Entering event queue @ 1456061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1456061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1457061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1458061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1459061009500. Starting simulation... -info: Entering event queue @ 1466061002500. Starting simulation... -info: Entering event queue @ 1466061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1466061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1467061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1468061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1469061014000. Starting simulation... -info: Entering event queue @ 1476061002500. Starting simulation... -info: Entering event queue @ 1476061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1476061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1477061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1478061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1479061014000. Starting simulation... -info: Entering event queue @ 1486061002500. Starting simulation... -info: Entering event queue @ 1486061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1486061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1487061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1488061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1489061009500. Starting simulation... -info: Entering event queue @ 1496061002500. Starting simulation... -info: Entering event queue @ 1496061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1496061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1497061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1498061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1499061014000. Starting simulation... -info: Entering event queue @ 1506061002500. Starting simulation... -info: Entering event queue @ 1506061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1506061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1507061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1508061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1509061009500. Starting simulation... -info: Entering event queue @ 1516061002500. Starting simulation... -info: Entering event queue @ 1516061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1516061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1517061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1518061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1519061014000. Starting simulation... -info: Entering event queue @ 1526061002500. Starting simulation... -info: Entering event queue @ 1526061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1526061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1527061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1528061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1529061009500. Starting simulation... -info: Entering event queue @ 1536061002500. Starting simulation... -info: Entering event queue @ 1536061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1536061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1537061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1538061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1539061009500. Starting simulation... -info: Entering event queue @ 1546061002500. Starting simulation... -info: Entering event queue @ 1546061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1546061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1547061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1548061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1549061009500. Starting simulation... -info: Entering event queue @ 1556061002500. Starting simulation... -info: Entering event queue @ 1556061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1556061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1557061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1558061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1559061009500. Starting simulation... -info: Entering event queue @ 1566061002500. Starting simulation... -info: Entering event queue @ 1566061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1566061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1567061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1568061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1569061014000. Starting simulation... -info: Entering event queue @ 1576061003500. Starting simulation... -info: Entering event queue @ 1576601934250. Starting simulation... -switching cpus -info: Entering event queue @ 1576601937000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1577601937000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1578601937000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1579601937000. Starting simulation... -info: Entering event queue @ 1586061003500. Starting simulation... -info: Entering event queue @ 1586061011000. Starting simulation... -switching cpus -info: Entering event queue @ 1586061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1587061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1588061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1589061015500. Starting simulation... -info: Entering event queue @ 1596061002500. Starting simulation... -info: Entering event queue @ 1596061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1596061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1597061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1598061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1599061009500. Starting simulation... -info: Entering event queue @ 1606061002500. Starting simulation... -info: Entering event queue @ 1606061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1606061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1607061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1608061009500. Starting simulation... -info: Entering event queue @ 1609338221250. Starting simulation... -switching cpus -info: Entering event queue @ 1609338224000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1610338224000. Starting simulation... -info: Entering event queue @ 1616061002500. Starting simulation... -info: Entering event queue @ 1616061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1616061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1617061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1618061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1619061009500. Starting simulation... -info: Entering event queue @ 1626061002500. Starting simulation... -info: Entering event queue @ 1626061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1626061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1627061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1628061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1629061014000. Starting simulation... -info: Entering event queue @ 1636061002500. Starting simulation... -info: Entering event queue @ 1636061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1636061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1637061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1638061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1639061014000. Starting simulation... -info: Entering event queue @ 1646061002500. Starting simulation... -info: Entering event queue @ 1646061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1646061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1647061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1648061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1649061009500. Starting simulation... -info: Entering event queue @ 1656061002500. Starting simulation... -info: Entering event queue @ 1656061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1656061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1657061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1658061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1659061014000. Starting simulation... -info: Entering event queue @ 1666061002500. Starting simulation... -info: Entering event queue @ 1666061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1666061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1667061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1668061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1669061009500. Starting simulation... -info: Entering event queue @ 1676061002500. Starting simulation... -info: Entering event queue @ 1676061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1676061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1677061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1678061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1679061014000. Starting simulation... -info: Entering event queue @ 1686061002500. Starting simulation... -info: Entering event queue @ 1686061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1686061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1687061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1688061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1689061009500. Starting simulation... -info: Entering event queue @ 1696061002500. Starting simulation... -info: Entering event queue @ 1696061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1696061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1697061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1698061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1699061009500. Starting simulation... -info: Entering event queue @ 1706061002500. Starting simulation... -info: Entering event queue @ 1707547042250. Starting simulation... -switching cpus -info: Entering event queue @ 1707547045000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1708547045000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1709547045000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1710547045000. Starting simulation... -info: Entering event queue @ 1716061002500. Starting simulation... -info: Entering event queue @ 1716061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1716061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1717061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1718061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1719061009500. Starting simulation... -info: Entering event queue @ 1726061002500. Starting simulation... -info: Entering event queue @ 1726061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1726061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1727061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1728061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1729061014000. Starting simulation... -info: Entering event queue @ 1736061003500. Starting simulation... -info: Entering event queue @ 1736061010500. Starting simulation... -switching cpus -info: Entering event queue @ 1736061015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1737061015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1738061015000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1739061015000. Starting simulation... -info: Entering event queue @ 1746061003500. Starting simulation... -info: Entering event queue @ 1746061011000. Starting simulation... -switching cpus -info: Entering event queue @ 1746061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1747061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1748061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1749061015500. Starting simulation... -info: Entering event queue @ 1756061002500. Starting simulation... -info: Entering event queue @ 1756061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1756061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1757061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1758061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1759061009500. Starting simulation... -info: Entering event queue @ 1766061002500. Starting simulation... -info: Entering event queue @ 1766061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1766061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1767061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1768061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1769061009500. Starting simulation... -info: Entering event queue @ 1776061002500. Starting simulation... -info: Entering event queue @ 1776061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1776061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1777061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1778061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1779061009500. Starting simulation... -info: Entering event queue @ 1786061003500. Starting simulation... -info: Entering event queue @ 1786061011500. Starting simulation... -switching cpus -info: Entering event queue @ 1786061016000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1787061016000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1788061016000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1789061016000. Starting simulation... -info: Entering event queue @ 1796061002500. Starting simulation... -info: Entering event queue @ 1796061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1796061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1797061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1798061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1799061014000. Starting simulation... -info: Entering event queue @ 1806061002500. Starting simulation... -info: Entering event queue @ 1806061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1806061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1807061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1808061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1809061009500. Starting simulation... -info: Entering event queue @ 1816061002500. Starting simulation... -info: Entering event queue @ 1816061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1816061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1817061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1818061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1819061014000. Starting simulation... -info: Entering event queue @ 1826061002500. Starting simulation... -info: Entering event queue @ 1826061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1826061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1827061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1828061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1829061009500. Starting simulation... -info: Entering event queue @ 1836061002500. Starting simulation... -info: Entering event queue @ 1836061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1836061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1837061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1838061014000. Starting simulation... -info: Entering event queue @ 1838124570250. Starting simulation... -switching cpus -info: Entering event queue @ 1838124573000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1839124573000. Starting simulation... -info: Entering event queue @ 1846061002500. Starting simulation... -info: Entering event queue @ 1846061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1846061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1847061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1848061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1849061009500. Starting simulation... -info: Entering event queue @ 1856061002500. Starting simulation... -info: Entering event queue @ 1856061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1856061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1857061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1858061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1859061009500. Starting simulation... -info: Entering event queue @ 1866061002500. Starting simulation... -info: Entering event queue @ 1866061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1866061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1867061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1868061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1869061009500. Starting simulation... -info: Entering event queue @ 1876061002500. Starting simulation... -info: Entering event queue @ 1876061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1876061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1877061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1878061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1879061009500. Starting simulation... -info: Entering event queue @ 1886061002500. Starting simulation... -info: Entering event queue @ 1886061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1886061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1887061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1888061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1889061014000. Starting simulation... -info: Entering event queue @ 1896061003500. Starting simulation... -info: Entering event queue @ 1896061010500. Starting simulation... -switching cpus -info: Entering event queue @ 1896061015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1897061015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1898061015000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1899061015000. Starting simulation... -info: Entering event queue @ 1906061003500. Starting simulation... -info: Entering event queue @ 1906061011000. Starting simulation... -switching cpus -info: Entering event queue @ 1906061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1907061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1908061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1909061015500. Starting simulation... -info: Entering event queue @ 1916061002500. Starting simulation... -info: Entering event queue @ 1916061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1916061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1917061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1918061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1919061009500. Starting simulation... -info: Entering event queue @ 1926061002500. Starting simulation... -info: Entering event queue @ 1926061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1926061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1927061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1928061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1929061009500. Starting simulation... -info: Entering event queue @ 1936061002500. Starting simulation... -info: Entering event queue @ 1936700970250. Starting simulation... -switching cpus -info: Entering event queue @ 1936700973000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1937700973000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1938700973000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1939700973000. Starting simulation... -info: Entering event queue @ 1946061002500. Starting simulation... -info: Entering event queue @ 1946061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1946061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1947061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1948061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1949061014000. Starting simulation... -info: Entering event queue @ 1956061002500. Starting simulation... -info: Entering event queue @ 1956061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1956061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1957061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1958061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1959061014000. Starting simulation... -info: Entering event queue @ 1966061002500. Starting simulation... -info: Entering event queue @ 1966061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1966061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1967061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1968061009500. Starting simulation... -info: Entering event queue @ 1969436945250. Starting simulation... -switching cpus -info: Entering event queue @ 1969436948000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1970436948000. Starting simulation... -info: Entering event queue @ 1976061002500. Starting simulation... -info: Entering event queue @ 1976061009500. Starting simulation... -switching cpus -info: Entering event queue @ 1976061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1977061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1978061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1979061014000. Starting simulation... -info: Entering event queue @ 1986061002500. Starting simulation... -info: Entering event queue @ 1986061009000. Starting simulation... -switching cpus -info: Entering event queue @ 1986061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1987061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1988061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1989061009500. Starting simulation... -info: Entering event queue @ 1996061003500. Starting simulation... -info: Entering event queue @ 1996061011000. Starting simulation... -switching cpus -info: Entering event queue @ 1996061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1997061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1998061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1999061015500. Starting simulation... -info: Entering event queue @ 2006061002500. Starting simulation... -info: Entering event queue @ 2006061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2006061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2007061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2008061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2009061009500. Starting simulation... -info: Entering event queue @ 2016061002500. Starting simulation... -info: Entering event queue @ 2016061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2016061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2017061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2018061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2019061009500. Starting simulation... -info: Entering event queue @ 2026061002500. Starting simulation... -info: Entering event queue @ 2026061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2026061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2027061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2028061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2029061009500. Starting simulation... -info: Entering event queue @ 2036061002500. Starting simulation... -info: Entering event queue @ 2036061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2036061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2037061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2038061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2039061009500. Starting simulation... -info: Entering event queue @ 2046061002500. Starting simulation... -info: Entering event queue @ 2046061009500. Starting simulation... -switching cpus -info: Entering event queue @ 2046061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2047061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2048061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2049061014000. Starting simulation... -info: Entering event queue @ 2056061003500. Starting simulation... -info: Entering event queue @ 2056061010500. Starting simulation... -switching cpus -info: Entering event queue @ 2056061015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2057061015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2058061015000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2059061015000. Starting simulation... -info: Entering event queue @ 2066061003500. Starting simulation... -info: Entering event queue @ 2067645765250. Starting simulation... -switching cpus -info: Entering event queue @ 2067645768000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2068645768000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2069645768000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2070645768000. Starting simulation... -info: Entering event queue @ 2076061002500. Starting simulation... -info: Entering event queue @ 2076061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2076061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2077061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2078061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2079061009500. Starting simulation... -info: Entering event queue @ 2086061002500. Starting simulation... -info: Entering event queue @ 2086061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2086061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2087061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2088061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2089061009500. Starting simulation... -info: Entering event queue @ 2096061002500. Starting simulation... -info: Entering event queue @ 2096061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2096061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2097061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2098061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2099061009500. Starting simulation... -info: Entering event queue @ 2106061002500. Starting simulation... -info: Entering event queue @ 2106061009500. Starting simulation... -switching cpus -info: Entering event queue @ 2106061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2107061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2108061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2109061014000. Starting simulation... -info: Entering event queue @ 2116061002500. Starting simulation... -info: Entering event queue @ 2116061009500. Starting simulation... -switching cpus -info: Entering event queue @ 2116061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2117061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2118061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2119061014000. Starting simulation... -info: Entering event queue @ 2126061002500. Starting simulation... -info: Entering event queue @ 2126061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2126061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2127061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2128061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2129061009500. Starting simulation... -info: Entering event queue @ 2136061002500. Starting simulation... -info: Entering event queue @ 2136061009500. Starting simulation... -switching cpus -info: Entering event queue @ 2136061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2137061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2138061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2139061014000. Starting simulation... -info: Entering event queue @ 2146061002500. Starting simulation... -info: Entering event queue @ 2146061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2146061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2147061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2148061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2149061009500. Starting simulation... -info: Entering event queue @ 2156061002500. Starting simulation... -info: Entering event queue @ 2156061009500. Starting simulation... -switching cpus -info: Entering event queue @ 2156061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2157061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2158061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2159061014000. Starting simulation... -info: Entering event queue @ 2166061002500. Starting simulation... -info: Entering event queue @ 2166061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2166061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2167061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2168061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2169061009500. Starting simulation... -info: Entering event queue @ 2176061002500. Starting simulation... -info: Entering event queue @ 2176061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2176061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2177061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2178061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2179061009500. Starting simulation... -info: Entering event queue @ 2186061002500. Starting simulation... -info: Entering event queue @ 2186061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2186061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2187061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2188061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2189061009500. Starting simulation... -info: Entering event queue @ 2196061002500. Starting simulation... -info: Entering event queue @ 2196061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2196061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2197061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2198061009500. Starting simulation... -info: Entering event queue @ 2198295410250. Starting simulation... -switching cpus -info: Entering event queue @ 2198295413000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2199295413000. Starting simulation... -info: Entering event queue @ 2206061002500. Starting simulation... -info: Entering event queue @ 2206061009500. Starting simulation... -switching cpus -info: Entering event queue @ 2206061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2207061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2208061014000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2209061014000. Starting simulation... -info: Entering event queue @ 2216061003500. Starting simulation... -info: Entering event queue @ 2216061010500. Starting simulation... -switching cpus -info: Entering event queue @ 2216061015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2217061015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2218061015000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2219061015000. Starting simulation... -info: Entering event queue @ 2226061003500. Starting simulation... -info: Entering event queue @ 2226061011000. Starting simulation... -switching cpus -info: Entering event queue @ 2226061015500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2227061015500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2228061015500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2229061015500. Starting simulation... -info: Entering event queue @ 2236061002500. Starting simulation... -info: Entering event queue @ 2236061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2236061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2237061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2238061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2239061009500. Starting simulation... -info: Entering event queue @ 2246061002500. Starting simulation... -info: Entering event queue @ 2246061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2246061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2247061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2248061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2249061009500. Starting simulation... -info: Entering event queue @ 2256061002500. Starting simulation... -info: Entering event queue @ 2256061009000. Starting simulation... -switching cpus -info: Entering event queue @ 2256061009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2257061009500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2258061009500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2259061009500. Starting simulation... -info: Entering event queue @ 2266061002500. Starting simulation... -info: Entering event queue @ 2266061009500. Starting simulation... -switching cpus -info: Entering event queue @ 2266061014000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2267061014000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2268061014000. Starting simulation... -switching cpus -info: Entering event queue @ 2268061021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2269061021500. Starting simulation... -switching cpus -info: Entering event queue @ 2269061148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2270061148000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2271061148000. Starting simulation... -switching cpus -info: Entering event queue @ 2271061155500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2272061155500. Starting simulation... -switching cpus -info: Entering event queue @ 2272061191000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2273061191000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2274061191000. Starting simulation... -switching cpus -info: Entering event queue @ 2274061278000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2275061278000. Starting simulation... -switching cpus -info: Entering event queue @ 2275061305000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2276061305000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2277061305000. Starting simulation... -switching cpus -info: Entering event queue @ 2277061449000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2278061449000. Starting simulation... -switching cpus -info: Entering event queue @ 2278061476000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2279061476000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2280061476000. Starting simulation... -switching cpus -info: Entering event queue @ 2280061529000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2281061529000. Starting simulation... -switching cpus -info: Entering event queue @ 2281070598000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2282070598000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2283070598000. Starting simulation... -info: Entering event queue @ 2283070605500. Starting simulation... -switching cpus -info: Entering event queue @ 2283070607500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2284070607500. Starting simulation... -switching cpus -info: Entering event queue @ 2284072321000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2285072321000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2286072321000. Starting simulation... -switching cpus -info: Entering event queue @ 2286072412000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2287072412000. Starting simulation... -switching cpus -info: Entering event queue @ 2287072517000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2288072517000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2289072517000. Starting simulation... -switching cpus -info: Entering event queue @ 2289072627000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2290072627000. Starting simulation... -switching cpus -info: Entering event queue @ 2290072768000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2291072768000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2292072768000. Starting simulation... -switching cpus -info: Entering event queue @ 2292072780000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2293072780000. Starting simulation... -switching cpus -info: Entering event queue @ 2293072888000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2294072888000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2295072888000. Starting simulation... -info: Entering event queue @ 2296800002250. Starting simulation... -switching cpus -info: Entering event queue @ 2296800005000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2297800005000. Starting simulation... -switching cpus -info: Entering event queue @ 2297800079000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2298800079000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2299800079000. Starting simulation... -switching cpus -info: Entering event queue @ 2299800134000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2300800134000. Starting simulation... -switching cpus -info: Entering event queue @ 2300800209000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2301800209000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2302800209000. Starting simulation... -switching cpus -info: Entering event queue @ 2302800293000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2303800293000. Starting simulation... -switching cpus -info: Entering event queue @ 2303800354000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2304800354000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2305800354000. Starting simulation... -switching cpus -info: Entering event queue @ 2305800437000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2306800437000. Starting simulation... -switching cpus -info: Entering event queue @ 2306800538000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2307800538000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2308800538000. Starting simulation... -switching cpus -info: Entering event queue @ 2308800680000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2309800680000. Starting simulation... -switching cpus -info: Entering event queue @ 2309800703000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2310800703000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2311800703000. Starting simulation... -switching cpus -info: Entering event queue @ 2311800722000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2312800722000. Starting simulation... -switching cpus -info: Entering event queue @ 2312800881000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2313800881000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2314800881000. Starting simulation... -switching cpus -info: Entering event queue @ 2314800888500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2315800888500. Starting simulation... -switching cpus -info: Entering event queue @ 2315801041000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2316801041000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2317801041000. Starting simulation... -switching cpus -info: Entering event queue @ 2317801187000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2318801187000. Starting simulation... -switching cpus -info: Entering event queue @ 2318801316000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2319801316000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2320801316000. Starting simulation... -switching cpus -info: Entering event queue @ 2320801362000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2321801362000. Starting simulation... -switching cpus -info: Entering event queue @ 2321801451000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2322801451000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2323801451000. Starting simulation... -switching cpus -info: Entering event queue @ 2323801593000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2324801593000. Starting simulation... -switching cpus -info: Entering event queue @ 2324801757000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2325801757000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2326801757000. Starting simulation... -switching cpus -info: Entering event queue @ 2326801907000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2327801907000. Starting simulation... -info: Entering event queue @ 2329536286250. Starting simulation... -switching cpus -info: Entering event queue @ 2329536289000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2330536289000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2331536289000. Starting simulation... -switching cpus -info: Entering event queue @ 2331536409000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2332536409000. Starting simulation... -switching cpus -info: Entering event queue @ 2332536496000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2333536496000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2334536496000. Starting simulation... -switching cpus -info: Entering event queue @ 2334536578000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2335536578000. Starting simulation... -switching cpus -info: Entering event queue @ 2335536696000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2336536696000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2337536696000. Starting simulation... -switching cpus -info: Entering event queue @ 2337536812000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2338536812000. Starting simulation... -switching cpus -info: Entering event queue @ 2338536969000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2339536969000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2340536969000. Starting simulation... -switching cpus -info: Entering event queue @ 2340536997000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2341536997000. Starting simulation... -switching cpus -info: Entering event queue @ 2341537098500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2342537098500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2343537098500. Starting simulation... -switching cpus -info: Entering event queue @ 2343537168000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2344537168000. Starting simulation... -switching cpus -info: Entering event queue @ 2344537177500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2345537177500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2346537177500. Starting simulation... -switching cpus -info: Entering event queue @ 2346537288000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2347537288000. Starting simulation... -switching cpus -info: Entering event queue @ 2347537394000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2348537394000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2349537394000. Starting simulation... -switching cpus -info: Entering event queue @ 2349537514000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2350537514000. Starting simulation... -switching cpus -info: Entering event queue @ 2350537663000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2351537663000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2352537663000. Starting simulation... -switching cpus -info: Entering event queue @ 2352537779000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2353537779000. Starting simulation... -switching cpus -info: Entering event queue @ 2353537905000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2354537905000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2355537905000. Starting simulation... -switching cpus -info: Entering event queue @ 2355538017000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2356538017000. Starting simulation... -switching cpus -info: Entering event queue @ 2356538152000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2357538152000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2358538152000. Starting simulation... -switching cpus -info: Entering event queue @ 2358538294000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2359538294000. Starting simulation... -switching cpus -info: Entering event queue @ 2359542534000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2360542534000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2361542534000. Starting simulation... -info: Entering event queue @ 2362129237250. Starting simulation... -switching cpus -info: Entering event queue @ 2362129240000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2363129240000. Starting simulation... -switching cpus -info: Entering event queue @ 2363133658000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2364133658000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2365133658000. Starting simulation... -switching cpus -info: Entering event queue @ 2365133769000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2366133769000. Starting simulation... -switching cpus -info: Entering event queue @ 2366133837000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2367133837000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2368133837000. Starting simulation... -info: Entering event queue @ 2368133844500. Starting simulation... -switching cpus -info: Entering event queue @ 2368133845000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2369133845000. Starting simulation... -switching cpus -info: Entering event queue @ 2369133852500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2370133852500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2371133852500. Starting simulation... -switching cpus -info: Entering event queue @ 2371134001000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2372134001000. Starting simulation... -switching cpus -info: Entering event queue @ 2372143233000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2373143233000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2374143233000. Starting simulation... -switching cpus -info: Entering event queue @ 2374143240500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2375143240500. Starting simulation... -switching cpus -info: Entering event queue @ 2375145136500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2376145136500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2377145136500. Starting simulation... -switching cpus -info: Entering event queue @ 2377145199000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2378145199000. Starting simulation... -switching cpus -info: Entering event queue @ 2378149152000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2379149152000. Starting simulation... -switching cpus -info: Entering event queue @ 2379149152500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2380149152500. Starting simulation... -switching cpus -info: Entering event queue @ 2380149276000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2381149276000. Starting simulation... -switching cpus -info: Entering event queue @ 2381149328000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2382149328000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2383149328000. Starting simulation... -switching cpus -info: Entering event queue @ 2383149380000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2384149380000. Starting simulation... -switching cpus -info: Entering event queue @ 2384149451500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2385149451500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2386149451500. Starting simulation... -switching cpus -info: Entering event queue @ 2386149459000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2387149459000. Starting simulation... -switching cpus -info: Entering event queue @ 2387152521500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2388152521500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2389152521500. Starting simulation... -switching cpus -info: Entering event queue @ 2389152529000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2390152529000. Starting simulation... -switching cpus -info: Entering event queue @ 2390152536500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2391152536500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2392152536500. Starting simulation... -switching cpus -info: Entering event queue @ 2392152544000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2393152544000. Starting simulation... -info: Entering event queue @ 2395010782250. Starting simulation... -switching cpus -info: Entering event queue @ 2395010785000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2396010785000. Starting simulation... -switching cpus -info: Entering event queue @ 2396010785500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2397010785500. Starting simulation... -switching cpus -info: Entering event queue @ 2397010793000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2398010793000. Starting simulation... -switching cpus -info: Entering event queue @ 2398010844000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2399010844000. Starting simulation... -switching cpus -info: Entering event queue @ 2399010844500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2400010844500. Starting simulation... -switching cpus -info: Entering event queue @ 2400010852000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2401010852000. Starting simulation... -switching cpus -info: Entering event queue @ 2401010917000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2402010917000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2403010917000. Starting simulation... -switching cpus -info: Entering event queue @ 2403010924500. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 3eab7d5a6..f17311f85 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -4,25 +4,15 @@ sim_seconds 2.403659 # Nu sim_ticks 2403658742000 # Number of ticks simulated final_tick 2403658742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 141358 # Simulator instruction rate (inst/s) -host_op_rate 181555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5632122143 # Simulator tick rate (ticks/s) -host_mem_usage 447420 # Number of bytes of host memory used -host_seconds 426.78 # Real time elapsed on the host +host_inst_rate 228698 # Simulator instruction rate (inst/s) +host_op_rate 293732 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9112018126 # Simulator tick rate (ticks/s) +host_mem_usage 403420 # Number of bytes of host memory used +host_seconds 263.79 # Real time elapsed on the host sim_insts 60328128 # Number of instructions simulated sim_ops 77483556 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory @@ -530,6 +520,18 @@ system.physmem.writeRowHitRate 88.14 # Ro system.physmem.avgGap 172554.83 # Average gap between requests system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 0.75 # Percentage of time for which DRAM has all the banks in precharge state +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 55672581 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 13813538 # Transaction distribution system.membus.trans_dist::ReadResp 13813538 # Transaction distribution @@ -566,6 +568,7 @@ system.membus.respLayer1.occupancy 1598779620 # La system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.membus.respLayer2.occupancy 30355600750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 63253 # number of replacements system.l2c.tags.tagsinuse 50392.264505 # Cycle average of tags in use system.l2c.tags.total_refs 1749443 # Total number of references to valid blocks. @@ -597,6 +600,18 @@ system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 system.l2c.tags.occ_percent::cpu2.inst 0.025666 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.024115 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.768925 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65394 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2645 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6480 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55890 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997833 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17683343 # Number of tag accesses +system.l2c.tags.data_accesses 17683343 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 8706 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3165 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 467858 # number of ReadReq hits @@ -1235,6 +1250,14 @@ system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964278 system.cpu0.icache.tags.occ_percent::cpu1.inst 0.015011 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019937 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999226 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 158 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 45450915 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 45450915 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 31849634 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 8050768 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 3742157 # number of ReadReq hits @@ -1365,6 +1388,13 @@ system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970753 system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015892 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013350 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 98826136 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 98826136 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 6861592 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 1819766 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 4641843 # number of ReadReq hits @@ -1988,6 +2018,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini index bd21d2c8f..3aa171235 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,7 +23,7 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -204,6 +204,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -220,6 +221,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -559,6 +561,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -575,6 +578,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -1114,6 +1118,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -1130,6 +1135,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -1147,6 +1153,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -1163,6 +1170,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr index c194b7193..1059ef88b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr @@ -1,14 +1,12 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. warn: The ccsidr register isn't implemented and always reads as 0. warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented -hack: be nice to actually delete the event here warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented @@ -17,9 +15,3 @@ warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: User mode does not have SPSR warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout index e9eaa0c70..74e20af0b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout @@ -1,2622 +1,8 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:34:20 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 23 2014 00:28:14 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 -info: Using bootloader at address 0x80000000 -info: Entering event queue @ 0. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1000000000. Starting simulation... -switching cpus -info: Entering event queue @ 1000007500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2000007500. Starting simulation... -switching cpus -info: Entering event queue @ 2000060000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 3000060000. Starting simulation... -switching cpus -info: Entering event queue @ 3000063500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 4000063500. Starting simulation... -switching cpus -info: Entering event queue @ 4000079500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5000079500. Starting simulation... -switching cpus -info: Entering event queue @ 5000082000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 6000082000. Starting simulation... -switching cpus -info: Entering event queue @ 6000085000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 7000085000. Starting simulation... -info: Entering event queue @ 7000092500. Starting simulation... -switching cpus -info: Entering event queue @ 7000096500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 8000096500. Starting simulation... -switching cpus -info: Entering event queue @ 8000104000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 9000104000. Starting simulation... -info: Entering event queue @ 9000125000. Starting simulation... -info: Entering event queue @ 9000130000. Starting simulation... -switching cpus -info: Entering event queue @ 9000134500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 10000134500. Starting simulation... -switching cpus -info: Entering event queue @ 10000250000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 11000250000. Starting simulation... -switching cpus -info: Entering event queue @ 11000557000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 12000557000. Starting simulation... -switching cpus -info: Entering event queue @ 12000567000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 13000567000. Starting simulation... -info: Entering event queue @ 13000584000. Starting simulation... -info: Entering event queue @ 13000589000. Starting simulation... -switching cpus -info: Entering event queue @ 13000593500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 14000593500. Starting simulation... -switching cpus -info: Entering event queue @ 14000684000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 15000684000. Starting simulation... -info: Entering event queue @ 15000698000. Starting simulation... -info: Entering event queue @ 15000703000. Starting simulation... -switching cpus -info: Entering event queue @ 15000707500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 16000707500. Starting simulation... -switching cpus -info: Entering event queue @ 16000715000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 17000715000. Starting simulation... -info: Entering event queue @ 17000770000. Starting simulation... -switching cpus -info: Entering event queue @ 17000896000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 18000896000. Starting simulation... -switching cpus -info: Entering event queue @ 26407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 27407630000. Starting simulation... -switching cpus -info: Entering event queue @ 36407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 37407630000. Starting simulation... -switching cpus -info: Entering event queue @ 46407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 47407630000. Starting simulation... -info: Entering event queue @ 48415862250. Starting simulation... -switching cpus -info: Entering event queue @ 48415869750. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 49415869750. Starting simulation... -info: Entering event queue @ 49415893500. Starting simulation... -switching cpus -info: Entering event queue @ 49415994500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 50415994500. Starting simulation... -info: Entering event queue @ 50416030500. Starting simulation... -switching cpus -info: Entering event queue @ 50416112000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 51416112000. Starting simulation... -info: Entering event queue @ 51416127500. Starting simulation... -info: Entering event queue @ 51416132000. Starting simulation... -switching cpus -info: Entering event queue @ 51416136500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 52416136500. Starting simulation... -info: Entering event queue @ 52416144500. Starting simulation... -switching cpus -info: Entering event queue @ 52416149000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 53416149000. Starting simulation... -switching cpus -info: Entering event queue @ 53416152000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 54416152000. Starting simulation... -switching cpus -info: Entering event queue @ 54416158000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 55416158000. Starting simulation... -switching cpus -info: Entering event queue @ 55416494500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 56416494500. Starting simulation... -info: Entering event queue @ 56416502000. Starting simulation... -info: Entering event queue @ 56416506500. Starting simulation... -switching cpus -info: Entering event queue @ 56416511000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 57416511000. Starting simulation... -switching cpus -info: Entering event queue @ 66407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 67407630000. Starting simulation... -switching cpus -info: Entering event queue @ 76407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 77407630000. Starting simulation... -switching cpus -info: Entering event queue @ 86407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 87407630000. Starting simulation... -switching cpus -info: Entering event queue @ 96407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 97407630000. Starting simulation... -switching cpus -info: Entering event queue @ 106407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 107407630000. Starting simulation... -switching cpus -info: Entering event queue @ 116407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 117407630000. Starting simulation... -switching cpus -info: Entering event queue @ 126407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 127407630000. Starting simulation... -switching cpus -info: Entering event queue @ 136407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 137407630000. Starting simulation... -info: Entering event queue @ 146407630000. Starting simulation... -info: Entering event queue @ 146556126250. Starting simulation... -switching cpus -info: Entering event queue @ 146556129000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 147556129000. Starting simulation... -switching cpus -info: Entering event queue @ 156407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 157407630000. Starting simulation... -switching cpus -info: Entering event queue @ 166407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 167407630000. Starting simulation... -switching cpus -info: Entering event queue @ 176407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 177407630000. Starting simulation... -switching cpus -info: Entering event queue @ 186407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 187407630000. Starting simulation... -switching cpus -info: Entering event queue @ 196407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 197407630000. Starting simulation... -switching cpus -info: Entering event queue @ 206407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 207407630000. Starting simulation... -switching cpus -info: Entering event queue @ 207407637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 208407637500. Starting simulation... -switching cpus -info: Entering event queue @ 216407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 217407630000. Starting simulation... -switching cpus -info: Entering event queue @ 226407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 227407630000. Starting simulation... -switching cpus -info: Entering event queue @ 236407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 237407630000. Starting simulation... -switching cpus -info: Entering event queue @ 246407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 247407630000. Starting simulation... -switching cpus -info: Entering event queue @ 256407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 257407630000. Starting simulation... -switching cpus -info: Entering event queue @ 266407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 267407630000. Starting simulation... -info: Entering event queue @ 276407630000. Starting simulation... -info: Entering event queue @ 277500885250. Starting simulation... -switching cpus -info: Entering event queue @ 277500888000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 278500888000. Starting simulation... -switching cpus -info: Entering event queue @ 286407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 287407630000. Starting simulation... -switching cpus -info: Entering event queue @ 296407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 297407630000. Starting simulation... -switching cpus -info: Entering event queue @ 306407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 307407630000. Starting simulation... -switching cpus -info: Entering event queue @ 316407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 317407630000. Starting simulation... -switching cpus -info: Entering event queue @ 326407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 327407630000. Starting simulation... -switching cpus -info: Entering event queue @ 336407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 337407630000. Starting simulation... -switching cpus -info: Entering event queue @ 346407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 347407630000. Starting simulation... -switching cpus -info: Entering event queue @ 356407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 357407630000. Starting simulation... -switching cpus -info: Entering event queue @ 366407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 367407630000. Starting simulation... -switching cpus -info: Entering event queue @ 376407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 377407630000. Starting simulation... -switching cpus -info: Entering event queue @ 386407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 387407630000. Starting simulation... -switching cpus -info: Entering event queue @ 396407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 397407630000. Starting simulation... -switching cpus -info: Entering event queue @ 406407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 407407630000. Starting simulation... -switching cpus -info: Entering event queue @ 416407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 417407630000. Starting simulation... -switching cpus -info: Entering event queue @ 426407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 427407630000. Starting simulation... -switching cpus -info: Entering event queue @ 436407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 437407630000. Starting simulation... -switching cpus -info: Entering event queue @ 446407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 447407630000. Starting simulation... -switching cpus -info: Entering event queue @ 456407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 457407630000. Starting simulation... -switching cpus -info: Entering event queue @ 466407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 467407630000. Starting simulation... -switching cpus -info: Entering event queue @ 476407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 477407630000. Starting simulation... -switching cpus -info: Entering event queue @ 486407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 487407630000. Starting simulation... -switching cpus -info: Entering event queue @ 496407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 497407630000. Starting simulation... -info: Entering event queue @ 506407630000. Starting simulation... -info: Entering event queue @ 506654813250. Starting simulation... -switching cpus -info: Entering event queue @ 506654816000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 507654816000. Starting simulation... -switching cpus -info: Entering event queue @ 516407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 517407630000. Starting simulation... -switching cpus -info: Entering event queue @ 526407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 527407630000. Starting simulation... -switching cpus -info: Entering event queue @ 536407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 537407630000. Starting simulation... -switching cpus -info: Entering event queue @ 546407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 547407630000. Starting simulation... -switching cpus -info: Entering event queue @ 556407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 557407630000. Starting simulation... -switching cpus -info: Entering event queue @ 566407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 567407630000. Starting simulation... -switching cpus -info: Entering event queue @ 576407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 577407630000. Starting simulation... -switching cpus -info: Entering event queue @ 586407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 587407630000. Starting simulation... -switching cpus -info: Entering event queue @ 596407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 597407630000. Starting simulation... -switching cpus -info: Entering event queue @ 606407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 607407630000. Starting simulation... -switching cpus -info: Entering event queue @ 616407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 617407630000. Starting simulation... -switching cpus -info: Entering event queue @ 626407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 627407630000. Starting simulation... -info: Entering event queue @ 636407630000. Starting simulation... -info: Entering event queue @ 637599918250. Starting simulation... -switching cpus -info: Entering event queue @ 637599921000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 638599921000. Starting simulation... -switching cpus -info: Entering event queue @ 646407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 647407630000. Starting simulation... -switching cpus -info: Entering event queue @ 656407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 657407630000. Starting simulation... -switching cpus -info: Entering event queue @ 666407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 667407630000. Starting simulation... -switching cpus -info: Entering event queue @ 676407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 677407630000. Starting simulation... -switching cpus -info: Entering event queue @ 686407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 687407630000. Starting simulation... -switching cpus -info: Entering event queue @ 696407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 697407630000. Starting simulation... -switching cpus -info: Entering event queue @ 706407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 707407630000. Starting simulation... -switching cpus -info: Entering event queue @ 716407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 717407630000. Starting simulation... -switching cpus -info: Entering event queue @ 726407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 727407630000. Starting simulation... -switching cpus -info: Entering event queue @ 736407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 737407630000. Starting simulation... -switching cpus -info: Entering event queue @ 746407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 747407630000. Starting simulation... -switching cpus -info: Entering event queue @ 756407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 757407630000. Starting simulation... -switching cpus -info: Entering event queue @ 766407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 767407630000. Starting simulation... -switching cpus -info: Entering event queue @ 776407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 777407630000. Starting simulation... -switching cpus -info: Entering event queue @ 786407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 787407630000. Starting simulation... -switching cpus -info: Entering event queue @ 796407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 797407630000. Starting simulation... -switching cpus -info: Entering event queue @ 806407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 807407630000. Starting simulation... -switching cpus -info: Entering event queue @ 816407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 817407630000. Starting simulation... -switching cpus -info: Entering event queue @ 826407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 827407630000. Starting simulation... -switching cpus -info: Entering event queue @ 836407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 837407630000. Starting simulation... -switching cpus -info: Entering event queue @ 846407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 847407630000. Starting simulation... -switching cpus -info: Entering event queue @ 856407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 857407630000. Starting simulation... -info: Entering event queue @ 866407630000. Starting simulation... -info: Entering event queue @ 866753842250. Starting simulation... -switching cpus -info: Entering event queue @ 866753845000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 867753845000. Starting simulation... -switching cpus -info: Entering event queue @ 876407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 877407630000. Starting simulation... -switching cpus -info: Entering event queue @ 886407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 887407630000. Starting simulation... -switching cpus -info: Entering event queue @ 896407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 897407630000. Starting simulation... -switching cpus -info: Entering event queue @ 906407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 907407630000. Starting simulation... -switching cpus -info: Entering event queue @ 916407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 917407630000. Starting simulation... -switching cpus -info: Entering event queue @ 926407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 927407630000. Starting simulation... -switching cpus -info: Entering event queue @ 936407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 937407630000. Starting simulation... -switching cpus -info: Entering event queue @ 946407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 947407630000. Starting simulation... -switching cpus -info: Entering event queue @ 956407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 957407630000. Starting simulation... -switching cpus -info: Entering event queue @ 966407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 967407630000. Starting simulation... -switching cpus -info: Entering event queue @ 976407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 977407630000. Starting simulation... -switching cpus -info: Entering event queue @ 986407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 987407630000. Starting simulation... -info: Entering event queue @ 996407630000. Starting simulation... -info: Entering event queue @ 997698950250. Starting simulation... -switching cpus -info: Entering event queue @ 997698953000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 998698953000. Starting simulation... -switching cpus -info: Entering event queue @ 1006407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1007407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1016407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1017407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1026407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1027407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1036407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1037407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1046407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1047407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1056407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1057407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1066407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1067407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1076407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1077407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1086407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1087407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1096407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1097407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1106407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1107407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1116407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1117407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1126407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1127407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1136407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1137407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1146407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1147407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1156407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1157407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1166407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1167407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1176407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1177407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1186407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1187407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1196407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1197407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1206407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1207407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1216407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1217407630000. Starting simulation... -info: Entering event queue @ 1226407630000. Starting simulation... -info: Entering event queue @ 1226852565250. Starting simulation... -switching cpus -info: Entering event queue @ 1226852568000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1227852568000. Starting simulation... -switching cpus -info: Entering event queue @ 1236407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1237407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1246407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1247407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1256407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1257407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1266407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1267407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1276407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1277407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1286407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1287407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1296407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1297407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1306407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1307407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1316407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1317407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1326407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1327407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1336407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1337407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1346407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1347407630000. Starting simulation... -info: Entering event queue @ 1356407630000. Starting simulation... -info: Entering event queue @ 1357797666250. Starting simulation... -switching cpus -info: Entering event queue @ 1357797669000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1358797669000. Starting simulation... -switching cpus -info: Entering event queue @ 1366407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1367407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1376407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1377407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1386407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1387407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1396407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1397407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1406407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1407407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1416407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1417407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1426407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1427407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1436407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1437407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1446407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1447407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1456407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1457407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1466407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1467407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1476407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1477407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1486407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1487407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1496407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1497407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1506407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1507407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1516407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1517407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1526407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1527407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1536407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1537407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1546407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1547407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1556407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1557407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1566407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1567407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1576407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1577407630000. Starting simulation... -info: Entering event queue @ 1586407630000. Starting simulation... -info: Entering event queue @ 1586951590250. Starting simulation... -switching cpus -info: Entering event queue @ 1586951593000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1587951593000. Starting simulation... -switching cpus -info: Entering event queue @ 1596407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1597407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1606407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1607407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1616407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1617407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1626407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1627407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1636407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1637407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1646407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1647407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1656407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1657407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1666407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1667407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1676407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1677407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1686407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1687407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1696407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1697407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1706407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1707407630000. Starting simulation... -info: Entering event queue @ 1716407630000. Starting simulation... -info: Entering event queue @ 1717896662250. Starting simulation... -switching cpus -info: Entering event queue @ 1717896665000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1718896665000. Starting simulation... -switching cpus -info: Entering event queue @ 1726407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1727407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1736407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1737407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1746407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1747407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1756407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1757407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1766407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1767407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1776407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1777407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1786407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1787407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1796407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1797407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1806407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1807407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1816407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1817407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1826407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1827407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1836407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1837407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1846407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1847407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1856407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1857407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1866407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1867407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1876407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1877407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1886407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1887407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1896407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1897407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1906407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1907407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1916407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1917407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1926407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1927407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1936407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1937407630000. Starting simulation... -info: Entering event queue @ 1946407630000. Starting simulation... -info: Entering event queue @ 1947050277250. Starting simulation... -switching cpus -info: Entering event queue @ 1947050280000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1948050280000. Starting simulation... -switching cpus -info: Entering event queue @ 1956407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1957407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1966407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1967407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1976407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1977407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1986407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1987407630000. Starting simulation... -switching cpus -info: Entering event queue @ 1996407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1997407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2006407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2007407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2016407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2017407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2026407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2027407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2036407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2037407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2046407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2047407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2056407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2057407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2066407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2067407630000. Starting simulation... -info: Entering event queue @ 2076407630000. Starting simulation... -info: Entering event queue @ 2077995385250. Starting simulation... -switching cpus -info: Entering event queue @ 2077995388000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2078995388000. Starting simulation... -switching cpus -info: Entering event queue @ 2086407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2087407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2096407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2097407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2106407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2107407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2116407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2117407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2126407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2127407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2136407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2137407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2146407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2147407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2156407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2157407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2166407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2167407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2176407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2177407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2186407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2187407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2196407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2197407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2206407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2207407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2216407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2217407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2226407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2227407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2236407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2237407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2246407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2247407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2256407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2257407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2266407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2267407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2276407630000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2277407630000. Starting simulation... -switching cpus -info: Entering event queue @ 2277409537500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2278409537500. Starting simulation... -switching cpus -info: Entering event queue @ 2278414867500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2279414867500. Starting simulation... -switching cpus -info: Entering event queue @ 2279419426000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2280419426000. Starting simulation... -switching cpus -info: Entering event queue @ 2280419476000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2281419476000. Starting simulation... -switching cpus -info: Entering event queue @ 2281429116500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2282429116500. Starting simulation... -switching cpus -info: Entering event queue @ 2282429246000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2283429246000. Starting simulation... -info: Entering event queue @ 2283429488500. Starting simulation... -info: Entering event queue @ 2283429494500. Starting simulation... -switching cpus -info: Entering event queue @ 2283429499000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2284429499000. Starting simulation... -switching cpus -info: Entering event queue @ 2284429592000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2285429592000. Starting simulation... -switching cpus -info: Entering event queue @ 2285429739000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2286429739000. Starting simulation... -switching cpus -info: Entering event queue @ 2286429753500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2287429753500. Starting simulation... -switching cpus -info: Entering event queue @ 2287429870500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2288429870500. Starting simulation... -switching cpus -info: Entering event queue @ 2288429988500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2289429988500. Starting simulation... -switching cpus -info: Entering event queue @ 2289430124000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2290430124000. Starting simulation... -switching cpus -info: Entering event queue @ 2290430180500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2291430180500. Starting simulation... -switching cpus -info: Entering event queue @ 2291430236000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2292430236000. Starting simulation... -switching cpus -info: Entering event queue @ 2292430259000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2293430259000. Starting simulation... -switching cpus -info: Entering event queue @ 2293433076000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2294433076000. Starting simulation... -switching cpus -info: Entering event queue @ 2294433155000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2295433155000. Starting simulation... -switching cpus -info: Entering event queue @ 2295433172000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2296433172000. Starting simulation... -info: Entering event queue @ 2296433181500. Starting simulation... -info: Entering event queue @ 2296433186000. Starting simulation... -switching cpus -info: Entering event queue @ 2296433190500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2297433190500. Starting simulation... -switching cpus -info: Entering event queue @ 2297433312000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2298433312000. Starting simulation... -switching cpus -info: Entering event queue @ 2298433344000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2299433344000. Starting simulation... -switching cpus -info: Entering event queue @ 2299433455000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2300433455000. Starting simulation... -switching cpus -info: Entering event queue @ 2300433479000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2301433479000. Starting simulation... -switching cpus -info: Entering event queue @ 2301433503000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2302433503000. Starting simulation... -switching cpus -info: Entering event queue @ 2302440698000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2303440698000. Starting simulation... -switching cpus -info: Entering event queue @ 2303440805000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2304440805000. Starting simulation... -switching cpus -info: Entering event queue @ 2304440909000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2305440909000. Starting simulation... -info: Entering event queue @ 2307149622250. Starting simulation... -switching cpus -info: Entering event queue @ 2307149625000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2308149625000. Starting simulation... -switching cpus -info: Entering event queue @ 2308149782000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2309149782000. Starting simulation... -info: Entering event queue @ 2309152871000. Starting simulation... -info: Entering event queue @ 2309152877000. Starting simulation... -switching cpus -info: Entering event queue @ 2309152881500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2310152881500. Starting simulation... -switching cpus -info: Entering event queue @ 2310153091000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2311153091000. Starting simulation... -switching cpus -info: Entering event queue @ 2311153129000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2312153129000. Starting simulation... -switching cpus -info: Entering event queue @ 2312162803000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2313162803000. Starting simulation... -switching cpus -info: Entering event queue @ 2313162841000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2314162841000. Starting simulation... -switching cpus -info: Entering event queue @ 2314162969000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2315162969000. Starting simulation... -switching cpus -info: Entering event queue @ 2315169643000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2316169643000. Starting simulation... -switching cpus -info: Entering event queue @ 2316169714000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2317169714000. Starting simulation... -switching cpus -info: Entering event queue @ 2317169776000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2318169776000. Starting simulation... -switching cpus -info: Entering event queue @ 2318175119000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2319175119000. Starting simulation... -switching cpus -info: Entering event queue @ 2319175239000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2320175239000. Starting simulation... -info: Entering event queue @ 2320175450500. Starting simulation... -switching cpus -info: Entering event queue @ 2320175458000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2321175458000. Starting simulation... -switching cpus -info: Entering event queue @ 2321175591500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2322175591500. Starting simulation... -switching cpus -info: Entering event queue @ 2322175626000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2323175626000. Starting simulation... -switching cpus -info: Entering event queue @ 2323175647000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2324175647000. Starting simulation... -switching cpus -info: Entering event queue @ 2324175714000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2325175714000. Starting simulation... -switching cpus -info: Entering event queue @ 2325175854000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2326175854000. Starting simulation... -switching cpus -info: Entering event queue @ 2326180829000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2327180829000. Starting simulation... -switching cpus -info: Entering event queue @ 2327180923000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2328180923000. Starting simulation... -switching cpus -info: Entering event queue @ 2328180942000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2329180942000. Starting simulation... -switching cpus -info: Entering event queue @ 2329181056000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2330181056000. Starting simulation... -switching cpus -info: Entering event queue @ 2330181099000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2331181099000. Starting simulation... -switching cpus -info: Entering event queue @ 2331181224000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2332181224000. Starting simulation... -switching cpus -info: Entering event queue @ 2332181371000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2333181371000. Starting simulation... -switching cpus -info: Entering event queue @ 2333183918000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2334183918000. Starting simulation... -switching cpus -info: Entering event queue @ 2334184003000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2335184003000. Starting simulation... -switching cpus -info: Entering event queue @ 2335184065500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2336184065500. Starting simulation... -switching cpus -info: Entering event queue @ 2336184220000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2337184220000. Starting simulation... -switching cpus -info: Entering event queue @ 2337184247000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2338184247000. Starting simulation... -info: Entering event queue @ 2339885909250. Starting simulation... -switching cpus -info: Entering event queue @ 2339885912000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2340885912000. Starting simulation... -switching cpus -info: Entering event queue @ 2340885975000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2341885975000. Starting simulation... -switching cpus -info: Entering event queue @ 2341885983000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2342885983000. Starting simulation... -switching cpus -info: Entering event queue @ 2342893450000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2343893450000. Starting simulation... -switching cpus -info: Entering event queue @ 2343893492000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2344893492000. Starting simulation... -switching cpus -info: Entering event queue @ 2344893590000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2345893590000. Starting simulation... -switching cpus -info: Entering event queue @ 2345900652000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2346900652000. Starting simulation... -switching cpus -info: Entering event queue @ 2346900696000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2347900696000. Starting simulation... -switching cpus -info: Entering event queue @ 2347900767000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2348900767000. Starting simulation... -switching cpus -info: Entering event queue @ 2348900774500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2349900774500. Starting simulation... -switching cpus -info: Entering event queue @ 2349900793000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2350900793000. Starting simulation... -switching cpus -info: Entering event queue @ 2350900953500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2351900953500. Starting simulation... -switching cpus -info: Entering event queue @ 2351901376000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2352901376000. Starting simulation... -switching cpus -info: Entering event queue @ 2352901383500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2353901383500. Starting simulation... -switching cpus -info: Entering event queue @ 2353901423000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2354901423000. Starting simulation... -switching cpus -info: Entering event queue @ 2354908569000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2355908569000. Starting simulation... -switching cpus -info: Entering event queue @ 2355908584000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2356908584000. Starting simulation... -switching cpus -info: Entering event queue @ 2356908737000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2357908737000. Starting simulation... -switching cpus -info: Entering event queue @ 2357915083000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2358915083000. Starting simulation... -switching cpus -info: Entering event queue @ 2358915112000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2359915112000. Starting simulation... -switching cpus -info: Entering event queue @ 2359915187000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2360915187000. Starting simulation... -switching cpus -info: Entering event queue @ 2360922523000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2361922523000. Starting simulation... -switching cpus -info: Entering event queue @ 2361922658000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2362922658000. Starting simulation... -switching cpus -info: Entering event queue @ 2362922750500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2363922750500. Starting simulation... -switching cpus -info: Entering event queue @ 2363922762000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2364922762000. Starting simulation... -switching cpus -info: Entering event queue @ 2364922771000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2365922771000. Starting simulation... -switching cpus -info: Entering event queue @ 2365927824000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2366927824000. Starting simulation... -switching cpus -info: Entering event queue @ 2366927896000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2367927896000. Starting simulation... -switching cpus -info: Entering event queue @ 2367927978000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2368927978000. Starting simulation... -switching cpus -info: Entering event queue @ 2368928076000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2369928076000. Starting simulation... -switching cpus -info: Entering event queue @ 2369928159000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2370928159000. Starting simulation... -info: Entering event queue @ 2372622506250. Starting simulation... -switching cpus -info: Entering event queue @ 2372622509000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2373622509000. Starting simulation... -switching cpus -info: Entering event queue @ 2373622667000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2374622667000. Starting simulation... -switching cpus -info: Entering event queue @ 2374625947000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2375625947000. Starting simulation... -switching cpus -info: Entering event queue @ 2375625991000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2376625991000. Starting simulation... -switching cpus -info: Entering event queue @ 2376626046000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2377626046000. Starting simulation... -switching cpus -info: Entering event queue @ 2377626053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2378626053500. Starting simulation... -switching cpus -info: Entering event queue @ 2378626119000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2379626119000. Starting simulation... -switching cpus -info: Entering event queue @ 2379633260000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2380633260000. Starting simulation... -switching cpus -info: Entering event queue @ 2380633388000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2381633388000. Starting simulation... -switching cpus -info: Entering event queue @ 2381633484000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2382633484000. Starting simulation... -switching cpus -info: Entering event queue @ 2382639954000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2383639954000. Starting simulation... -switching cpus -info: Entering event queue @ 2383640101000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2384640101000. Starting simulation... -switching cpus -info: Entering event queue @ 2384640241000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2385640241000. Starting simulation... -switching cpus -info: Entering event queue @ 2385646694000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2386646694000. Starting simulation... -switching cpus -info: Entering event queue @ 2386646793000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2387646793000. Starting simulation... -switching cpus -info: Entering event queue @ 2387646908500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2388646908500. Starting simulation... -switching cpus -info: Entering event queue @ 2388646947500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2389646947500. Starting simulation... -switching cpus -info: Entering event queue @ 2389647000500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2390647000500. Starting simulation... -switching cpus -info: Entering event queue @ 2390647107000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2391647107000. Starting simulation... -switching cpus -info: Entering event queue @ 2391647193000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2392647193000. Starting simulation... -switching cpus -info: Entering event queue @ 2392647232000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2393647232000. Starting simulation... -switching cpus -info: Entering event queue @ 2393655582000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2394655582000. Starting simulation... -switching cpus -info: Entering event queue @ 2394655705000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2395655705000. Starting simulation... -switching cpus -info: Entering event queue @ 2395655800000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2396655800000. Starting simulation... -switching cpus -info: Entering event queue @ 2396655896000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2397655896000. Starting simulation... -switching cpus -info: Entering event queue @ 2397656000000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2398656000000. Starting simulation... -switching cpus -info: Entering event queue @ 2398656109000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2399656109000. Starting simulation... -switching cpus -info: Entering event queue @ 2399656252000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2400656252000. Starting simulation... -switching cpus -info: Entering event queue @ 2400658939000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2401658939000. Starting simulation... -switching cpus -info: Entering event queue @ 2401659076000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2402659076000. Starting simulation... -switching cpus -info: Entering event queue @ 2402659185500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2403659185500. Starting simulation... -info: Entering event queue @ 2405358441250. Starting simulation... -switching cpus -info: Entering event queue @ 2405358444000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2406358444000. Starting simulation... -switching cpus -info: Entering event queue @ 2406358469000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2407358469000. Starting simulation... -switching cpus -info: Entering event queue @ 2407367356000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2408367356000. Starting simulation... -switching cpus -info: Entering event queue @ 2408367376000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2409367376000. Starting simulation... -switching cpus -info: Entering event queue @ 2409367470000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2410367470000. Starting simulation... -switching cpus -info: Entering event queue @ 2410374541000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2411374541000. Starting simulation... -switching cpus -info: Entering event queue @ 2411374671000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2412374671000. Starting simulation... -switching cpus -info: Entering event queue @ 2412374731500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2413374731500. Starting simulation... -switching cpus -info: Entering event queue @ 2413381673000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2414381673000. Starting simulation... -switching cpus -info: Entering event queue @ 2414381740000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2415381740000. Starting simulation... -switching cpus -info: Entering event queue @ 2415381765000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2416381765000. Starting simulation... -switching cpus -info: Entering event queue @ 2416388872000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2417388872000. Starting simulation... -switching cpus -info: Entering event queue @ 2417388890000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2418388890000. Starting simulation... -switching cpus -info: Entering event queue @ 2418388899500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2419388899500. Starting simulation... -switching cpus -info: Entering event queue @ 2419388941000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2420388941000. Starting simulation... -switching cpus -info: Entering event queue @ 2420389055000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2421389055000. Starting simulation... -switching cpus -info: Entering event queue @ 2421389132000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2422389132000. Starting simulation... -switching cpus -info: Entering event queue @ 2422389169500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2423389169500. Starting simulation... -switching cpus -info: Entering event queue @ 2423389212000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2424389212000. Starting simulation... -switching cpus -info: Entering event queue @ 2424392828000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2425392828000. Starting simulation... -switching cpus -info: Entering event queue @ 2425392965000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2426392965000. Starting simulation... -switching cpus -info: Entering event queue @ 2426393102000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2427393102000. Starting simulation... -switching cpus -info: Entering event queue @ 2427396556000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2428396556000. Starting simulation... -switching cpus -info: Entering event queue @ 2428396645000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2429396645000. Starting simulation... -switching cpus -info: Entering event queue @ 2429396754000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2430396754000. Starting simulation... -switching cpus -info: Entering event queue @ 2430403859000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2431403859000. Starting simulation... -switching cpus -info: Entering event queue @ 2431403964000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2432403964000. Starting simulation... -switching cpus -info: Entering event queue @ 2432404100500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2433404100500. Starting simulation... -switching cpus -info: Entering event queue @ 2433404250000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2434404250000. Starting simulation... -switching cpus -info: Entering event queue @ 2434410611000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2435410611000. Starting simulation... -switching cpus -info: Entering event queue @ 2435410707000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2436410707000. Starting simulation... -info: Entering event queue @ 2438094729250. Starting simulation... -switching cpus -info: Entering event queue @ 2438094732000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2439094732000. Starting simulation... -switching cpus -info: Entering event queue @ 2439094850000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2440094850000. Starting simulation... -switching cpus -info: Entering event queue @ 2440094895000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2441094895000. Starting simulation... -switching cpus -info: Entering event queue @ 2441099330000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2442099330000. Starting simulation... -switching cpus -info: Entering event queue @ 2442099486000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2443099486000. Starting simulation... -switching cpus -info: Entering event queue @ 2443099600500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2444099600500. Starting simulation... -switching cpus -info: Entering event queue @ 2444106551000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2445106551000. Starting simulation... -switching cpus -info: Entering event queue @ 2445106624000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2446106624000. Starting simulation... -switching cpus -info: Entering event queue @ 2446106663000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2447106663000. Starting simulation... -switching cpus -info: Entering event queue @ 2447106677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2448106677500. Starting simulation... -switching cpus -info: Entering event queue @ 2448106732000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2449106732000. Starting simulation... -switching cpus -info: Entering event queue @ 2449106788500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2450106788500. Starting simulation... -switching cpus -info: Entering event queue @ 2450106864000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2451106864000. Starting simulation... -switching cpus -info: Entering event queue @ 2451106954500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2452106954500. Starting simulation... -switching cpus -info: Entering event queue @ 2452107027000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2453107027000. Starting simulation... -switching cpus -info: Entering event queue @ 2453107165000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2454107165000. Starting simulation... -switching cpus -info: Entering event queue @ 2454112628000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2455112628000. Starting simulation... -switching cpus -info: Entering event queue @ 2455112711000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2456112711000. Starting simulation... -switching cpus -info: Entering event queue @ 2456112857000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2457112857000. Starting simulation... -switching cpus -info: Entering event queue @ 2457112869000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2458112869000. Starting simulation... -switching cpus -info: Entering event queue @ 2458113021000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2459113021000. Starting simulation... -switching cpus -info: Entering event queue @ 2459113070000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2460113070000. Starting simulation... -switching cpus -info: Entering event queue @ 2460113176000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2461113176000. Starting simulation... -switching cpus -info: Entering event queue @ 2461114992000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2462114992000. Starting simulation... -switching cpus -info: Entering event queue @ 2462115142000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2463115142000. Starting simulation... -switching cpus -info: Entering event queue @ 2463115302000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2464115302000. Starting simulation... -switching cpus -info: Entering event queue @ 2464122382000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2465122382000. Starting simulation... -switching cpus -info: Entering event queue @ 2465122453000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2466122453000. Starting simulation... -switching cpus -info: Entering event queue @ 2466122567000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2467122567000. Starting simulation... -switching cpus -info: Entering event queue @ 2467122667000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2468122667000. Starting simulation... -switching cpus -info: Entering event queue @ 2468122726000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2469122726000. Starting simulation... -info: Entering event queue @ 2470831329250. Starting simulation... -switching cpus -info: Entering event queue @ 2470831332000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2471831332000. Starting simulation... -switching cpus -info: Entering event queue @ 2471831399000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2472831399000. Starting simulation... -switching cpus -info: Entering event queue @ 2472831434000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2473831434000. Starting simulation... -switching cpus -info: Entering event queue @ 2473831443000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2474831443000. Starting simulation... -switching cpus -info: Entering event queue @ 2474831496500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2475831496500. Starting simulation... -switching cpus -info: Entering event queue @ 2475831610000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2476831610000. Starting simulation... -switching cpus -info: Entering event queue @ 2476831728000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2477831728000. Starting simulation... -switching cpus -info: Entering event queue @ 2477831824000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2478831824000. Starting simulation... -switching cpus -info: Entering event queue @ 2478833712000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2479833712000. Starting simulation... -switching cpus -info: Entering event queue @ 2479833747000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2480833747000. Starting simulation... -switching cpus -info: Entering event queue @ 2480833839000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2481833839000. Starting simulation... -info: Entering event queue @ 2481835884000. Starting simulation... -info: Entering event queue @ 2481835889000. Starting simulation... -switching cpus -info: Entering event queue @ 2481835893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2482835893500. Starting simulation... -switching cpus -info: Entering event queue @ 2482837674000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2483837674000. Starting simulation... -switching cpus -info: Entering event queue @ 2483837738000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2484837738000. Starting simulation... -switching cpus -info: Entering event queue @ 2484841149000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2485841149000. Starting simulation... -switching cpus -info: Entering event queue @ 2485841199000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2486841199000. Starting simulation... -switching cpus -info: Entering event queue @ 2486841323500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2487841323500. Starting simulation... -switching cpus -info: Entering event queue @ 2487841419000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2488841419000. Starting simulation... -switching cpus -info: Entering event queue @ 2488841557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2489841557500. Starting simulation... -switching cpus -info: Entering event queue @ 2489841714000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2490841714000. Starting simulation... -switching cpus -info: Entering event queue @ 2490841815000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2491841815000. Starting simulation... -switching cpus -info: Entering event queue @ 2491846012000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2492846012000. Starting simulation... -switching cpus -info: Entering event queue @ 2492846092000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2493846092000. Starting simulation... -switching cpus -info: Entering event queue @ 2493846192000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2494846192000. Starting simulation... -switching cpus -info: Entering event queue @ 2494846274000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2495846274000. Starting simulation... -switching cpus -info: Entering event queue @ 2495846428000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2496846428000. Starting simulation... -switching cpus -info: Entering event queue @ 2496846578500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2497846578500. Starting simulation... -switching cpus -info: Entering event queue @ 2497846655000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2498846655000. Starting simulation... -switching cpus -info: Entering event queue @ 2498846726000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2499846726000. Starting simulation... -switching cpus -info: Entering event queue @ 2499846861000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2500846861000. Starting simulation... -switching cpus -info: Entering event queue @ 2500851435000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2501851435000. Starting simulation... -info: Entering event queue @ 2503567610250. Starting simulation... -switching cpus -info: Entering event queue @ 2503567613000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2504567613000. Starting simulation... -switching cpus -info: Entering event queue @ 2504567726000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2505567726000. Starting simulation... -switching cpus -info: Entering event queue @ 2505574981000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2506574981000. Starting simulation... -switching cpus -info: Entering event queue @ 2506575012000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2507575012000. Starting simulation... -switching cpus -info: Entering event queue @ 2507575052000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2508575052000. Starting simulation... -switching cpus -info: Entering event queue @ 2508575160000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2509575160000. Starting simulation... -switching cpus -info: Entering event queue @ 2509575287000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2510575287000. Starting simulation... -switching cpus -info: Entering event queue @ 2510575294500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2511575294500. Starting simulation... -switching cpus -info: Entering event queue @ 2511575312000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2512575312000. Starting simulation... -switching cpus -info: Entering event queue @ 2512575405000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2513575405000. Starting simulation... -switching cpus -info: Entering event queue @ 2513575444000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2514575444000. Starting simulation... -switching cpus -info: Entering event queue @ 2514575602000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2515575602000. Starting simulation... -switching cpus -info: Entering event queue @ 2515575628500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2516575628500. Starting simulation... -switching cpus -info: Entering event queue @ 2516575659000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2517575659000. Starting simulation... -switching cpus -info: Entering event queue @ 2517575698000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2518575698000. Starting simulation... -switching cpus -info: Entering event queue @ 2518577085000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2519577085000. Starting simulation... -switching cpus -info: Entering event queue @ 2519577132000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2520577132000. Starting simulation... -switching cpus -info: Entering event queue @ 2520577256500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2521577256500. Starting simulation... -switching cpus -info: Entering event queue @ 2521584198000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2522584198000. Starting simulation... -switching cpus -info: Entering event queue @ 2522584259000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2523584259000. Starting simulation... -switching cpus -info: Entering event queue @ 2523584372000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2524584372000. Starting simulation... -switching cpus -info: Entering event queue @ 2524584455500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2525584455500. Starting simulation... -switching cpus -info: Entering event queue @ 2525591164000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2526591164000. Starting simulation... -switching cpus -info: Entering event queue @ 2526591230000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2527591230000. Starting simulation... -switching cpus -info: Entering event queue @ 2527591238000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2528591238000. Starting simulation... -switching cpus -info: Entering event queue @ 2528597259000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2529597259000. Starting simulation... -switching cpus -info: Entering event queue @ 2529597411000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2530597411000. Starting simulation... -switching cpus -info: Entering event queue @ 2530597561500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2531597561500. Starting simulation... -switching cpus -info: Entering event queue @ 2531597646000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2532597646000. Starting simulation... -switching cpus -info: Entering event queue @ 2532597765000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2533597765000. Starting simulation... -info: Entering event queue @ 2533597774500. Starting simulation... -info: Entering event queue @ 2533597779000. Starting simulation... -switching cpus -info: Entering event queue @ 2533597780000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2534597780000. Starting simulation... -info: Entering event queue @ 2536303549250. Starting simulation... -switching cpus -info: Entering event queue @ 2536303552000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2537303552000. Starting simulation... -info: Entering event queue @ 2537303556000. Starting simulation... -switching cpus -info: Entering event queue @ 2537303560500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2538303560500. Starting simulation... -info: Entering event queue @ 2538303568500. Starting simulation... -switching cpus -info: Entering event queue @ 2538303573000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2539303573000. Starting simulation... -switching cpus -info: Entering event queue @ 2539303580500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2540303580500. Starting simulation... -switching cpus -info: Entering event queue @ 2540303606000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2541303606000. Starting simulation... -switching cpus -info: Entering event queue @ 2541303613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2542303613500. Starting simulation... -switching cpus -info: Entering event queue @ 2542303621000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2543303621000. Starting simulation... -switching cpus -info: Entering event queue @ 2543303628500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2544303628500. Starting simulation... -switching cpus -info: Entering event queue @ 2544303636000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2545303636000. Starting simulation... -switching cpus -info: Entering event queue @ 2545303749000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2546303749000. Starting simulation... -switching cpus -info: Entering event queue @ 2546303779000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2547303779000. Starting simulation... -switching cpus -info: Entering event queue @ 2547303786500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2548303786500. Starting simulation... -switching cpus -info: Entering event queue @ 2548303794000. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 5fef90c5a..5e74bf3fb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.549345 # Nu sim_ticks 2549345168000 # Number of ticks simulated final_tick 2549345168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48945 # Simulator instruction rate (inst/s) -host_op_rate 62980 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2068782078 # Simulator tick rate (ticks/s) -host_mem_usage 448444 # Number of bytes of host memory used -host_seconds 1232.29 # Real time elapsed on the host +host_inst_rate 76720 # Simulator instruction rate (inst/s) +host_op_rate 98719 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3242754050 # Simulator tick rate (ticks/s) +host_mem_usage 404480 # Number of bytes of host memory used +host_seconds 786.17 # Real time elapsed on the host sim_insts 60314699 # Number of instructions simulated sim_ops 77609228 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 1856 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory @@ -639,6 +641,7 @@ system.membus.respLayer1.occupancy 4736419263 # La system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 34186627978 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 64357 # number of replacements system.l2c.tags.tagsinuse 51453.251473 # Cycle average of tags in use system.l2c.tags.total_refs 1905423 # Total number of references to valid blocks. @@ -662,6 +665,18 @@ system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000207 system.l2c.tags.occ_percent::cpu1.inst 0.051046 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.044272 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.785114 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65363 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 24 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3051 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6862 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55068 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997360 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 18937227 # Number of tag accesses +system.l2c.tags.data_accesses 18937227 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 32950 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 7107 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 506567 # number of ReadReq hits @@ -1517,6 +1532,13 @@ system.cpu0.icache.tags.occ_blocks::cpu1.inst 191.745915 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.624663 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.374504 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999166 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 167 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 12566622 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 12566622 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 5233615 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 5282125 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 10515740 # number of ReadReq hits @@ -1644,6 +1666,13 @@ system.cpu0.dcache.tags.occ_blocks::cpu1.data 257.286930 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497473 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.502514 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 101674783 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 101674783 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 6830201 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6949651 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13779852 # number of ReadReq hits @@ -2200,6 +2229,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini index 927b487de..6f15742b0 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini @@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain @@ -23,12 +23,12 @@ eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 panic_on_oops=true @@ -75,7 +75,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/dist/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -130,6 +130,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -146,6 +147,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -178,6 +180,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -194,6 +197,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -352,6 +356,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -368,6 +373,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -385,6 +391,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -401,6 +408,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr index e2fadf975..4dfb66c84 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr @@ -1,12 +1,10 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections -warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. warn: The ccsidr register isn't implemented and always reads as 0. -hack: be nice to actually delete the event here warn: instruction 'mcr bpiallis' unimplemented warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr dccimvac' unimplemented @@ -33,3 +31,13 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout index 6d8b9163b..25848b995 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout @@ -1,10536 +1,8 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:46:41 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 23 2014 00:31:08 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 -info: Using bootloader at address 0x80000000 -info: Entering event queue @ 0. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1000000000. Starting simulation... -switching cpus -info: Entering event queue @ 1000007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2000007500. Starting simulation... -switching cpus -info: Entering event queue @ 2000015000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 3000015000. Starting simulation... -switching cpus -info: Entering event queue @ 3000081000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 4000081000. Starting simulation... -switching cpus -info: Entering event queue @ 4000151000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 5000151000. Starting simulation... -switching cpus -info: Entering event queue @ 5000197000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 6000197000. Starting simulation... -switching cpus -info: Entering event queue @ 6000198000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 7000198000. Starting simulation... -switching cpus -info: Entering event queue @ 7000198500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 8000198500. Starting simulation... -switching cpus -info: Entering event queue @ 8000199000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 9000199000. Starting simulation... -switching cpus -info: Entering event queue @ 9000200000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 10000200000. Starting simulation... -switching cpus -info: Entering event queue @ 10000269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 11000269500. Starting simulation... -switching cpus -info: Entering event queue @ 11000272000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 12000272000. Starting simulation... -switching cpus -info: Entering event queue @ 12000273000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 13000273000. Starting simulation... -switching cpus -info: Entering event queue @ 13000274000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 14000274000. Starting simulation... -switching cpus -info: Entering event queue @ 14000275000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 15000275000. Starting simulation... -info: Entering event queue @ 15000288500. Starting simulation... -switching cpus -info: Entering event queue @ 15000290000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 16000290000. Starting simulation... -info: Entering event queue @ 16000302500. Starting simulation... -switching cpus -info: Entering event queue @ 16000306000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 17000306000. Starting simulation... -switching cpus -info: Entering event queue @ 17000313500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 18000313500. Starting simulation... -switching cpus -info: Entering event queue @ 18000314500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 19000314500. Starting simulation... -switching cpus -info: Entering event queue @ 19000322000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 20000322000. Starting simulation... -switching cpus -info: Entering event queue @ 20000329500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 21000329500. Starting simulation... -switching cpus -info: Entering event queue @ 21000337000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 22000337000. Starting simulation... -switching cpus -info: Entering event queue @ 22000344500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 23000344500. Starting simulation... -switching cpus -info: Entering event queue @ 23000395000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 24000395000. Starting simulation... -switching cpus -info: Entering event queue @ 24000402500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 25000402500. Starting simulation... -switching cpus -info: Entering event queue @ 25000410000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 26000410000. Starting simulation... -switching cpus -info: Entering event queue @ 26000417500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 27000417500. Starting simulation... -switching cpus -info: Entering event queue @ 27000425000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 28000425000. Starting simulation... -switching cpus -info: Entering event queue @ 28000432500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 29000432500. Starting simulation... -switching cpus -info: Entering event queue @ 29000440000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 30000440000. Starting simulation... -switching cpus -info: Entering event queue @ 30000447500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 31000447500. Starting simulation... -switching cpus -info: Entering event queue @ 31000455000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 32000455000. Starting simulation... -switching cpus -info: Entering event queue @ 32000462500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 33000462500. Starting simulation... -switching cpus -info: Entering event queue @ 33000470000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 34000470000. Starting simulation... -switching cpus -info: Entering event queue @ 34000694000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 35000694000. Starting simulation... -switching cpus -info: Entering event queue @ 35000701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 36000701500. Starting simulation... -switching cpus -info: Entering event queue @ 36000709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 37000709000. Starting simulation... -switching cpus -info: Entering event queue @ 37000716500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 38000716500. Starting simulation... -info: Entering event queue @ 38000736000. Starting simulation... -switching cpus -info: Entering event queue @ 38000832750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 39000832750. Starting simulation... -switching cpus -info: Entering event queue @ 39000840250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 40000840250. Starting simulation... -switching cpus -info: Entering event queue @ 40000847750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 41000847750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 42000847750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 43000847750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 44000847750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 45000847750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 46000847750. Starting simulation... -switching cpus -info: Entering event queue @ 46000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 47000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 48000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 49000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 50000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 51000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 52000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 53000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 54000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 55000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 56000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 57000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 58000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 59000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 60000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 61000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 62000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 63000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 64000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 65000855250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 66000855250. Starting simulation... -info: Entering event queue @ 67631497250. Starting simulation... -switching cpus -info: Entering event queue @ 67631500000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 68631500000. Starting simulation... -switching cpus -info: Entering event queue @ 68631519500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 69631519500. Starting simulation... -switching cpus -info: Entering event queue @ 69631527000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 70631527000. Starting simulation... -switching cpus -info: Entering event queue @ 70631534500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 71631534500. Starting simulation... -switching cpus -info: Entering event queue @ 71631554500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 72631554500. Starting simulation... -switching cpus -info: Entering event queue @ 72631563500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 73631563500. Starting simulation... -info: Entering event queue @ 73631597500. Starting simulation... -switching cpus -info: Entering event queue @ 73631689750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 74631689750. Starting simulation... -switching cpus -info: Entering event queue @ 74631697250. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 75631697250. Starting simulation... -switching cpus -info: Entering event queue @ 75631727500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 76631727500. Starting simulation... -switching cpus -info: Entering event queue @ 76631736500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 77631736500. Starting simulation... -switching cpus -info: Entering event queue @ 77631744000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 78631744000. Starting simulation... -switching cpus -info: Entering event queue @ 78631751500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 79631751500. Starting simulation... -switching cpus -info: Entering event queue @ 79631773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 80631773500. Starting simulation... -switching cpus -info: Entering event queue @ 80631802500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 81631802500. Starting simulation... -switching cpus -info: Entering event queue @ 81631810000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 82631810000. Starting simulation... -switching cpus -info: Entering event queue @ 82631817500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 83631817500. Starting simulation... -switching cpus -info: Entering event queue @ 83631834500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 84631834500. Starting simulation... -switching cpus -info: Entering event queue @ 84631842000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 85631842000. Starting simulation... -switching cpus -info: Entering event queue @ 85631849500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 86631849500. Starting simulation... -switching cpus -info: Entering event queue @ 86631857000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 87631857000. Starting simulation... -switching cpus -info: Entering event queue @ 87631864500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 88631864500. Starting simulation... -switching cpus -info: Entering event queue @ 88631872000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 89631872000. Starting simulation... -switching cpus -info: Entering event queue @ 89631879500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 90631879500. Starting simulation... -info: Entering event queue @ 90631913500. Starting simulation... -switching cpus -info: Entering event queue @ 90631921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 91631921000. Starting simulation... -switching cpus -info: Entering event queue @ 91631938500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 92631938500. Starting simulation... -switching cpus -info: Entering event queue @ 92631957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 93631957500. Starting simulation... -switching cpus -info: Entering event queue @ 93631965000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 94631965000. Starting simulation... -switching cpus -info: Entering event queue @ 94631983500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 95631983500. Starting simulation... -switching cpus -info: Entering event queue @ 95632005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 96632005500. Starting simulation... -switching cpus -info: Entering event queue @ 96632013000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 97632013000. Starting simulation... -switching cpus -info: Entering event queue @ 97632020500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 98632020500. Starting simulation... -info: Entering event queue @ 100364210250. Starting simulation... -switching cpus -info: Entering event queue @ 100364213000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 101364213000. Starting simulation... -switching cpus -info: Entering event queue @ 101364220500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 102364220500. Starting simulation... -switching cpus -info: Entering event queue @ 102364228000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 103364228000. Starting simulation... -switching cpus -info: Entering event queue @ 103364235500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 104364235500. Starting simulation... -switching cpus -info: Entering event queue @ 104364260500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 105364260500. Starting simulation... -switching cpus -info: Entering event queue @ 105364274500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 106364274500. Starting simulation... -switching cpus -info: Entering event queue @ 106364300500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 107364300500. Starting simulation... -switching cpus -info: Entering event queue @ 107364308000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 108364308000. Starting simulation... -info: Entering event queue @ 108364322500. Starting simulation... -switching cpus -info: Entering event queue @ 108364326000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 109364326000. Starting simulation... -switching cpus -info: Entering event queue @ 109364326500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 110364326500. Starting simulation... -info: Entering event queue @ 110364339000. Starting simulation... -switching cpus -info: Entering event queue @ 110364342500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 111364342500. Starting simulation... -info: Entering event queue @ 111364349500. Starting simulation... -switching cpus -info: Entering event queue @ 111364351000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 112364351000. Starting simulation... -switching cpus -info: Entering event queue @ 112364355500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 113364355500. Starting simulation... -switching cpus -info: Entering event queue @ 113364357000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 114364357000. Starting simulation... -switching cpus -info: Entering event queue @ 114364358000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 115364358000. Starting simulation... -switching cpus -info: Entering event queue @ 115364361500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 116364361500. Starting simulation... -switching cpus -info: Entering event queue @ 116364363000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 117364363000. Starting simulation... -switching cpus -info: Entering event queue @ 117364363500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 118364363500. Starting simulation... -switching cpus -info: Entering event queue @ 118364371000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 119364371000. Starting simulation... -switching cpus -info: Entering event queue @ 119364374000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 120364374000. Starting simulation... -switching cpus -info: Entering event queue @ 120364381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 121364381500. Starting simulation... -switching cpus -info: Entering event queue @ 121364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 122364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 123364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 124364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 125364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 126364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 127364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 128364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 129364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 130364389000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 131364389000. Starting simulation... -info: Entering event queue @ 133099170250. Starting simulation... -switching cpus -info: Entering event queue @ 133099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 134099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 135099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 136099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 137099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 138099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 139099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 140099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 141099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 142099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 143099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 144099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 145099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 146099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 147099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 148099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 149099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 150099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 151099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 152099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 153099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 154099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 155099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 156099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 157099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 158099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 159099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 160099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 161099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 162099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 163099173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 164099173000. Starting simulation... -info: Entering event queue @ 165835457250. Starting simulation... -switching cpus -info: Entering event queue @ 165835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 166835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 167835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 168835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 169835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 170835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 171835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 172835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 173835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 174835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 175835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 176835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 177835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 178835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 179835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 180835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 181835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 182835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 183835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 184835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 185835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 186835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 187835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 188835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 189835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 190835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 191835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 192835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 193835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 194835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 195835460000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 196835460000. Starting simulation... -info: Entering event queue @ 198571738250. Starting simulation... -switching cpus -info: Entering event queue @ 198571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 199571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 200571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 201571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 202571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 203571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 204571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 205571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 206571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 207571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 208571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 209571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 210571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 211571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 212571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 213571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 214571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 215571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 216571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 217571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 218571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 219571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 220571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 221571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 222571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 223571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 224571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 225571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 226571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 227571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 228571741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 229571741000. Starting simulation... -info: Entering event queue @ 231307990250. Starting simulation... -switching cpus -info: Entering event queue @ 231307993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 232307993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 233307993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 234307993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 235307993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 236307993000. Starting simulation... -switching cpus -info: Entering event queue @ 236308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 237308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 238308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 239308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 240308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 241308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 242308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 243308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 244308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 245308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 246308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 247308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 248308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 249308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 250308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 251308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 252308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 253308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 254308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 255308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 256308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 257308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 258308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 259308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 260308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 261308000500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 262308000500. Starting simulation... -info: Entering event queue @ 264044274250. Starting simulation... -switching cpus -info: Entering event queue @ 264044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 265044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 266044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 267044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 268044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 269044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 270044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 271044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 272044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 273044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 274044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 275044277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 276044277000. Starting simulation... -switching cpus -info: Entering event queue @ 276044278500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 277044278500. Starting simulation... -switching cpus -info: Entering event queue @ 277044286000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 278044286000. Starting simulation... -switching cpus -info: Entering event queue @ 278044293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 279044293500. Starting simulation... -switching cpus -info: Entering event queue @ 279044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 280044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 281044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 282044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 283044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 284044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 285044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 286044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 287044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 288044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 289044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 290044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 291044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 292044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 293044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 294044301000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 295044301000. Starting simulation... -info: Entering event queue @ 296780565250. Starting simulation... -switching cpus -info: Entering event queue @ 296780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 297780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 298780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 299780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 300780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 301780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 302780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 303780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 304780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 305780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 306780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 307780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 308780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 309780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 310780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 311780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 312780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 313780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 314780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 315780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 316780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 317780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 318780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 319780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 320780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 321780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 322780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 323780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 324780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 325780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 326780568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 327780568000. Starting simulation... -info: Entering event queue @ 329516810250. Starting simulation... -switching cpus -info: Entering event queue @ 329516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 330516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 331516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 332516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 333516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 334516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 335516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 336516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 337516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 338516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 339516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 340516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 341516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 342516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 343516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 344516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 345516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 346516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 347516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 348516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 349516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 350516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 351516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 352516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 353516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 354516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 355516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 356516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 357516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 358516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 359516813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 360516813000. Starting simulation... -info: Entering event queue @ 362253097250. Starting simulation... -switching cpus -info: Entering event queue @ 362253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 363253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 364253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 365253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 366253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 367253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 368253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 369253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 370253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 371253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 372253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 373253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 374253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 375253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 376253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 377253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 378253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 379253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 380253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 381253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 382253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 383253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 384253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 385253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 386253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 387253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 388253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 389253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 390253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 391253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 392253100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 393253100000. Starting simulation... -info: Entering event queue @ 394989382250. Starting simulation... -switching cpus -info: Entering event queue @ 394989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 395989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 396989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 397989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 398989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 399989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 400989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 401989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 402989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 403989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 404989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 405989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 406989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 407989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 408989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 409989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 410989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 411989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 412989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 413989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 414989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 415989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 416989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 417989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 418989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 419989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 420989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 421989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 422989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 423989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 424989385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 425989385000. Starting simulation... -info: Entering event queue @ 427725666250. Starting simulation... -switching cpus -info: Entering event queue @ 427725669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 428725669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 429725669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 430725669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 431725669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 432725669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 433725669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 434725669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 435725669000. Starting simulation... -switching cpus -info: Entering event queue @ 435725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 436725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 437725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 438725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 439725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 440725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 441725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 442725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 443725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 444725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 445725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 446725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 447725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 448725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 449725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 450725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 451725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 452725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 453725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 454725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 455725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 456725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 457725676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 458725676500. Starting simulation... -info: Entering event queue @ 460461918250. Starting simulation... -switching cpus -info: Entering event queue @ 460461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 461461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 462461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 463461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 464461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 465461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 466461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 467461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 468461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 469461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 470461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 471461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 472461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 473461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 474461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 475461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 476461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 477461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 478461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 479461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 480461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 481461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 482461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 483461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 484461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 485461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 486461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 487461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 488461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 489461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 490461921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 491461921000. Starting simulation... -info: Entering event queue @ 493198202250. Starting simulation... -switching cpus -info: Entering event queue @ 493198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 494198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 495198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 496198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 497198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 498198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 499198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 500198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 501198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 502198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 503198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 504198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 505198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 506198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 507198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 508198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 509198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 510198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 511198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 512198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 513198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 514198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 515198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 516198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 517198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 518198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 519198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 520198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 521198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 522198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 523198205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 524198205000. Starting simulation... -info: Entering event queue @ 525934134250. Starting simulation... -switching cpus -info: Entering event queue @ 525934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 526934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 527934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 528934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 529934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 530934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 531934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 532934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 533934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 534934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 535934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 536934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 537934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 538934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 539934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 540934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 541934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 542934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 543934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 544934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 545934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 546934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 547934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 548934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 549934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 550934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 551934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 552934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 553934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 554934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 555934137000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 556934137000. Starting simulation... -info: Entering event queue @ 558670734250. Starting simulation... -switching cpus -info: Entering event queue @ 558670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 559670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 560670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 561670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 562670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 563670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 564670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 565670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 566670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 567670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 568670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 569670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 570670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 571670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 572670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 573670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 574670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 575670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 576670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 577670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 578670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 579670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 580670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 581670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 582670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 583670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 584670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 585670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 586670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 587670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 588670737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 589670737000. Starting simulation... -info: Entering event queue @ 591406706250. Starting simulation... -switching cpus -info: Entering event queue @ 591406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 592406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 593406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 594406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 595406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 596406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 597406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 598406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 599406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 600406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 601406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 602406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 603406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 604406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 605406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 606406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 607406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 608406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 609406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 610406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 611406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 612406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 613406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 614406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 615406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 616406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 617406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 618406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 619406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 620406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 621406709000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 622406709000. Starting simulation... -info: Entering event queue @ 624142997250. Starting simulation... -switching cpus -info: Entering event queue @ 624143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 625143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 626143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 627143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 628143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 629143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 630143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 631143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 632143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 633143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 634143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 635143000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 636143000000. Starting simulation... -switching cpus -info: Entering event queue @ 636143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 637143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 638143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 639143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 640143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 641143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 642143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 643143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 644143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 645143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 646143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 647143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 648143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 649143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 650143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 651143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 652143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 653143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 654143007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 655143007500. Starting simulation... -info: Entering event queue @ 656879241250. Starting simulation... -switching cpus -info: Entering event queue @ 656879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 657879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 658879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 659879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 660879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 661879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 662879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 663879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 664879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 665879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 666879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 667879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 668879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 669879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 670879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 671879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 672879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 673879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 674879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 675879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 676879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 677879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 678879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 679879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 680879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 681879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 682879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 683879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 684879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 685879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 686879244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 687879244000. Starting simulation... -info: Entering event queue @ 689615526250. Starting simulation... -switching cpus -info: Entering event queue @ 689615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 690615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 691615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 692615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 693615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 694615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 695615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 696615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 697615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 698615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 699615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 700615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 701615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 702615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 703615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 704615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 705615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 706615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 707615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 708615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 709615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 710615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 711615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 712615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 713615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 714615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 715615529000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 716615529000. Starting simulation... -switching cpus -info: Entering event queue @ 716615536500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 717615536500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 718615536500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 719615536500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 720615536500. Starting simulation... -info: Entering event queue @ 722351817250. Starting simulation... -switching cpus -info: Entering event queue @ 722351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 723351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 724351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 725351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 726351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 727351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 728351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 729351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 730351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 731351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 732351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 733351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 734351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 735351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 736351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 737351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 738351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 739351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 740351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 741351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 742351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 743351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 744351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 745351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 746351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 747351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 748351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 749351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 750351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 751351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 752351820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 753351820000. Starting simulation... -info: Entering event queue @ 755088065250. Starting simulation... -switching cpus -info: Entering event queue @ 755088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 756088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 757088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 758088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 759088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 760088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 761088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 762088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 763088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 764088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 765088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 766088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 767088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 768088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 769088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 770088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 771088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 772088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 773088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 774088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 775088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 776088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 777088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 778088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 779088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 780088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 781088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 782088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 783088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 784088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 785088068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 786088068000. Starting simulation... -info: Entering event queue @ 787824349250. Starting simulation... -switching cpus -info: Entering event queue @ 787824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 788824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 789824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 790824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 791824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 792824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 793824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 794824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 795824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 796824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 797824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 798824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 799824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 800824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 801824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 802824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 803824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 804824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 805824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 806824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 807824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 808824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 809824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 810824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 811824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 812824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 813824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 814824352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 815824352000. Starting simulation... -switching cpus -info: Entering event queue @ 815824359500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 816824359500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 817824359500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 818824359500. Starting simulation... -info: Entering event queue @ 820560634250. Starting simulation... -switching cpus -info: Entering event queue @ 820560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 821560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 822560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 823560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 824560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 825560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 826560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 827560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 828560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 829560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 830560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 831560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 832560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 833560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 834560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 835560637000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 836560637000. Starting simulation... -switching cpus -info: Entering event queue @ 836560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 837560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 838560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 839560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 840560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 841560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 842560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 843560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 844560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 845560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 846560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 847560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 848560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 849560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 850560644500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 851560644500. Starting simulation... -info: Entering event queue @ 853296882250. Starting simulation... -switching cpus -info: Entering event queue @ 853296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 854296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 855296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 856296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 857296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 858296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 859296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 860296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 861296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 862296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 863296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 864296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 865296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 866296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 867296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 868296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 869296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 870296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 871296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 872296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 873296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 874296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 875296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 876296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 877296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 878296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 879296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 880296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 881296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 882296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 883296885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 884296885000. Starting simulation... -info: Entering event queue @ 886033170250. Starting simulation... -switching cpus -info: Entering event queue @ 886033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 887033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 888033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 889033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 890033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 891033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 892033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 893033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 894033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 895033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 896033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 897033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 898033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 899033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 900033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 901033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 902033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 903033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 904033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 905033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 906033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 907033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 908033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 909033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 910033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 911033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 912033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 913033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 914033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 915033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 916033173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 917033173000. Starting simulation... -info: Entering event queue @ 918769454250. Starting simulation... -switching cpus -info: Entering event queue @ 918769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 919769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 920769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 921769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 922769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 923769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 924769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 925769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 926769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 927769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 928769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 929769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 930769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 931769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 932769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 933769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 934769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 935769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 936769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 937769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 938769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 939769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 940769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 941769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 942769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 943769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 944769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 945769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 946769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 947769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 948769457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 949769457000. Starting simulation... -info: Entering event queue @ 951505745250. Starting simulation... -switching cpus -info: Entering event queue @ 951505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 952505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 953505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 954505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 955505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 956505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 957505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 958505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 959505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 960505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 961505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 962505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 963505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 964505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 965505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 966505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 967505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 968505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 969505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 970505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 971505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 972505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 973505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 974505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 975505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 976505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 977505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 978505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 979505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 980505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 981505748000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 982505748000. Starting simulation... -info: Entering event queue @ 984241990250. Starting simulation... -switching cpus -info: Entering event queue @ 984241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 985241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 986241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 987241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 988241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 989241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 990241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 991241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 992241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 993241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 994241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 995241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 996241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 997241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 998241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 999241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1000241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1001241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1002241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1003241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1004241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1005241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1006241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1007241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1008241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1009241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1010241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1011241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1012241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1013241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1014241993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1015241993000. Starting simulation... -info: Entering event queue @ 1016978277250. Starting simulation... -switching cpus -info: Entering event queue @ 1016978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1017978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1018978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1019978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1020978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1021978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1022978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1023978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1024978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1025978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1026978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1027978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1028978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1029978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1030978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1031978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1032978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1033978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1034978280000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1035978280000. Starting simulation... -switching cpus -info: Entering event queue @ 1035978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1036978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1037978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1038978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1039978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1040978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1041978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1042978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1043978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1044978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1045978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1046978287500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1047978287500. Starting simulation... -info: Entering event queue @ 1049714558250. Starting simulation... -switching cpus -info: Entering event queue @ 1049714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1050714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1051714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1052714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1053714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1054714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1055714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1056714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1057714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1058714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1059714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1060714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1061714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1062714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1063714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1064714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1065714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1066714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1067714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1068714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1069714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1070714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1071714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1072714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1073714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1074714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1075714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1076714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1077714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1078714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1079714561000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1080714561000. Starting simulation... -info: Entering event queue @ 1082450813250. Starting simulation... -switching cpus -info: Entering event queue @ 1082450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1083450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1084450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1085450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1086450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1087450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1088450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1089450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1090450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1091450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1092450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1093450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1094450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1095450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1096450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1097450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1098450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1099450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1100450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1101450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1102450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1103450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1104450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1105450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1106450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1107450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1108450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1109450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1110450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1111450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1112450816000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1113450816000. Starting simulation... -info: Entering event queue @ 1115187098250. Starting simulation... -switching cpus -info: Entering event queue @ 1115187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1116187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1117187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1118187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1119187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1120187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1121187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1122187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1123187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1124187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1125187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1126187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1127187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1128187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1129187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1130187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1131187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1132187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1133187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1134187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1135187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1136187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1137187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1138187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1139187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1140187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1141187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1142187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1143187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1144187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1145187101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1146187101000. Starting simulation... -info: Entering event queue @ 1147923385250. Starting simulation... -switching cpus -info: Entering event queue @ 1147923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1148923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1149923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1150923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1151923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1152923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1153923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1154923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1155923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1156923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1157923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1158923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1159923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1160923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1161923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1162923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1163923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1164923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1165923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1166923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1167923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1168923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1169923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1170923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1171923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1172923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1173923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1174923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1175923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1176923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1177923388000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1178923388000. Starting simulation... -info: Entering event queue @ 1180659666250. Starting simulation... -switching cpus -info: Entering event queue @ 1180659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1181659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1182659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1183659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1184659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1185659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1186659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1187659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1188659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1189659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1190659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1191659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1192659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1193659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1194659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1195659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1196659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1197659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1198659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1199659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1200659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1201659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1202659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1203659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1204659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1205659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1206659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1207659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1208659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1209659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1210659669000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1211659669000. Starting simulation... -info: Entering event queue @ 1213395918250. Starting simulation... -switching cpus -info: Entering event queue @ 1213395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1214395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1215395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1216395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1217395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1218395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1219395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1220395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1221395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1222395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1223395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1224395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1225395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1226395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1227395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1228395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1229395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1230395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1231395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1232395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1233395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1234395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1235395921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1236395921000. Starting simulation... -switching cpus -info: Entering event queue @ 1236395928500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1237395928500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1238395928500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1239395928500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1240395928500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1241395928500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1242395928500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1243395928500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1244395928500. Starting simulation... -info: Entering event queue @ 1246132202250. Starting simulation... -switching cpus -info: Entering event queue @ 1246132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1247132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1248132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1249132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1250132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1251132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1252132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1253132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1254132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1255132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1256132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1257132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1258132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1259132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1260132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1261132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1262132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1263132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1264132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1265132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1266132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1267132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1268132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1269132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1270132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1271132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1272132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1273132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1274132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1275132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1276132205000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1277132205000. Starting simulation... -info: Entering event queue @ 1278868486250. Starting simulation... -switching cpus -info: Entering event queue @ 1278868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1279868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1280868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1281868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1282868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1283868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1284868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1285868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1286868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1287868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1288868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1289868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1290868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1291868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1292868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1293868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1294868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1295868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1296868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1297868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1298868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1299868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1300868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1301868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1302868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1303868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1304868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1305868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1306868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1307868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1308868489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1309868489000. Starting simulation... -info: Entering event queue @ 1311604734250. Starting simulation... -switching cpus -info: Entering event queue @ 1311604737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1312604737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1313604737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1314604737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1315604737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1316604737000. Starting simulation... -switching cpus -info: Entering event queue @ 1316604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1317604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1318604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1319604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1320604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1321604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1322604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1323604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1324604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1325604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1326604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1327604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1328604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1329604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1330604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1331604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1332604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1333604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1334604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1335604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1336604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1337604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1338604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1339604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1340604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1341604744500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1342604744500. Starting simulation... -info: Entering event queue @ 1344341022250. Starting simulation... -switching cpus -info: Entering event queue @ 1344341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1345341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1346341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1347341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1348341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1349341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1350341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1351341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1352341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1353341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1354341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1355341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1356341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1357341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1358341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1359341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1360341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1361341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1362341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1363341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1364341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1365341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1366341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1367341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1368341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1369341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1370341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1371341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1372341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1373341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1374341025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1375341025000. Starting simulation... -info: Entering event queue @ 1377076990250. Starting simulation... -switching cpus -info: Entering event queue @ 1377076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1378076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1379076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1380076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1381076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1382076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1383076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1384076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1385076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1386076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1387076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1388076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1389076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1390076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1391076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1392076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1393076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1394076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1395076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1396076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1397076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1398076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1399076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1400076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1401076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1402076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1403076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1404076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1405076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1406076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1407076993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1408076993000. Starting simulation... -info: Entering event queue @ 1409813242250. Starting simulation... -switching cpus -info: Entering event queue @ 1409813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1410813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1411813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1412813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1413813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1414813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1415813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1416813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1417813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1418813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1419813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1420813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1421813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1422813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1423813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1424813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1425813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1426813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1427813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1428813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1429813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1430813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1431813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1432813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1433813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1434813245000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1435813245000. Starting simulation... -switching cpus -info: Entering event queue @ 1435813252500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1436813252500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1437813252500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1438813252500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1439813252500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1440813252500. Starting simulation... -info: Entering event queue @ 1442549529250. Starting simulation... -switching cpus -info: Entering event queue @ 1442549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1443549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1444549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1445549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1446549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1447549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1448549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1449549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1450549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1451549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1452549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1453549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1454549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1455549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1456549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1457549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1458549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1459549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1460549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1461549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1462549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1463549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1464549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1465549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1466549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1467549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1468549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1469549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1470549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1471549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1472549532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1473549532000. Starting simulation... -info: Entering event queue @ 1475285817250. Starting simulation... -switching cpus -info: Entering event queue @ 1475285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1476285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1477285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1478285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1479285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1480285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1481285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1482285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1483285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1484285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1485285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1486285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1487285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1488285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1489285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1490285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1491285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1492285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1493285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1494285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1495285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1496285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1497285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1498285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1499285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1500285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1501285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1502285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1503285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1504285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1505285820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1506285820000. Starting simulation... -info: Entering event queue @ 1508022065250. Starting simulation... -switching cpus -info: Entering event queue @ 1508022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1509022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1510022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1511022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1512022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1513022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1514022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1515022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1516022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1517022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1518022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1519022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1520022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1521022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1522022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1523022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1524022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1525022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1526022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1527022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1528022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1529022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1530022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1531022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1532022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1533022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1534022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1535022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1536022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1537022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1538022068000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1539022068000. Starting simulation... -info: Entering event queue @ 1540758349250. Starting simulation... -switching cpus -info: Entering event queue @ 1540758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1541758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1542758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1543758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1544758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1545758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1546758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1547758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1548758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1549758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1550758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1551758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1552758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1553758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1554758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1555758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1556758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1557758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1558758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1559758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1560758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1561758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1562758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1563758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1564758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1565758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1566758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1567758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1568758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1569758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1570758352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1571758352000. Starting simulation... -info: Entering event queue @ 1573494637250. Starting simulation... -switching cpus -info: Entering event queue @ 1573494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1574494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1575494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1576494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1577494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1578494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1579494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1580494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1581494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1582494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1583494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1584494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1585494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1586494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1587494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1588494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1589494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1590494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1591494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1592494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1593494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1594494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1595494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1596494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1597494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1598494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1599494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1600494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1601494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1602494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1603494640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1604494640000. Starting simulation... -info: Entering event queue @ 1606230882250. Starting simulation... -switching cpus -info: Entering event queue @ 1606230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1607230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1608230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1609230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1610230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1611230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1612230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1613230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1614230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1615230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1616230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1617230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1618230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1619230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1620230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1621230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1622230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1623230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1624230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1625230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1626230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1627230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1628230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1629230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1630230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1631230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1632230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1633230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1634230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1635230885000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1636230885000. Starting simulation... -switching cpus -info: Entering event queue @ 1636230892500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1637230892500. Starting simulation... -info: Entering event queue @ 1638967170250. Starting simulation... -switching cpus -info: Entering event queue @ 1638967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1639967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1640967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1641967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1642967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1643967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1644967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1645967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1646967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1647967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1648967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1649967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1650967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1651967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1652967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1653967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1654967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1655967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1656967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1657967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1658967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1659967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1660967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1661967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1662967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1663967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1664967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1665967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1666967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1667967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1668967173000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1669967173000. Starting simulation... -info: Entering event queue @ 1671703454250. Starting simulation... -switching cpus -info: Entering event queue @ 1671703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1672703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1673703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1674703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1675703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1676703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1677703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1678703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1679703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1680703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1681703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1682703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1683703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1684703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1685703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1686703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1687703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1688703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1689703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1690703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1691703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1692703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1693703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1694703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1695703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1696703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1697703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1698703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1699703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1700703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1701703457000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1702703457000. Starting simulation... -info: Entering event queue @ 1704439738250. Starting simulation... -switching cpus -info: Entering event queue @ 1704439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1705439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1706439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1707439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1708439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1709439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1710439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1711439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1712439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1713439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1714439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1715439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1716439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1717439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1718439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1719439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1720439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1721439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1722439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1723439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1724439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1725439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1726439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1727439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1728439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1729439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1730439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1731439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1732439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1733439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1734439741000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1735439741000. Starting simulation... -info: Entering event queue @ 1737175990250. Starting simulation... -switching cpus -info: Entering event queue @ 1737175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1738175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1739175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1740175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1741175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1742175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1743175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1744175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1745175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1746175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1747175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1748175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1749175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1750175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1751175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1752175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1753175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1754175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1755175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1756175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1757175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1758175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1759175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1760175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1761175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1762175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1763175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1764175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1765175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1766175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1767175993000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1768175993000. Starting simulation... -info: Entering event queue @ 1769912274250. Starting simulation... -switching cpus -info: Entering event queue @ 1769912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1770912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1771912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1772912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1773912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1774912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1775912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1776912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1777912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1778912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1779912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1780912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1781912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1782912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1783912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1784912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1785912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1786912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1787912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1788912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1789912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1790912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1791912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1792912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1793912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1794912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1795912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1796912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1797912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1798912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1799912277000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1800912277000. Starting simulation... -info: Entering event queue @ 1802648565250. Starting simulation... -switching cpus -info: Entering event queue @ 1802648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1803648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1804648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1805648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1806648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1807648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1808648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1809648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1810648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1811648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1812648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1813648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1814648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1815648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1816648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1817648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1818648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1819648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1820648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1821648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1822648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1823648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1824648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1825648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1826648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1827648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1828648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1829648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1830648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1831648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1832648568000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1833648568000. Starting simulation... -info: Entering event queue @ 1835384810250. Starting simulation... -switching cpus -info: Entering event queue @ 1835384813000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1836384813000. Starting simulation... -switching cpus -info: Entering event queue @ 1836384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1837384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1838384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1839384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1840384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1841384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1842384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1843384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1844384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1845384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1846384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1847384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1848384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1849384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1850384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1851384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1852384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1853384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1854384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1855384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1856384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1857384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1858384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1859384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1860384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1861384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1862384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1863384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1864384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1865384820500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1866384820500. Starting simulation... -info: Entering event queue @ 1868121097250. Starting simulation... -switching cpus -info: Entering event queue @ 1868121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1869121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1870121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1871121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1872121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1873121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1874121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1875121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1876121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1877121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1878121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1879121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1880121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1881121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1882121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1883121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1884121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1885121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1886121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1887121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1888121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1889121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1890121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1891121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1892121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1893121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1894121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1895121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1896121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1897121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1898121100000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1899121100000. Starting simulation... -info: Entering event queue @ 1900857382250. Starting simulation... -switching cpus -info: Entering event queue @ 1900857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1901857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1902857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1903857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1904857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1905857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1906857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1907857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1908857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1909857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1910857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1911857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1912857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1913857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1914857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1915857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1916857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1917857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1918857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1919857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1920857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1921857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1922857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1923857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1924857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1925857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1926857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1927857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1928857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1929857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1930857385000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1931857385000. Starting simulation... -info: Entering event queue @ 1933593673250. Starting simulation... -switching cpus -info: Entering event queue @ 1933593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1934593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1935593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1936593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1937593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1938593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1939593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1940593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1941593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1942593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1943593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1944593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1945593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1946593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1947593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1948593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1949593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1950593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1951593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1952593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1953593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1954593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1955593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1956593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1957593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1958593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1959593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1960593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1961593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1962593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1963593676000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1964593676000. Starting simulation... -info: Entering event queue @ 1966329918250. Starting simulation... -switching cpus -info: Entering event queue @ 1966329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1967329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1968329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1969329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1970329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1971329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1972329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1973329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1974329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1975329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1976329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1977329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1978329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1979329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1980329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1981329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1982329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1983329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1984329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1985329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1986329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1987329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1988329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1989329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1990329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1991329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1992329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1993329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1994329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1995329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1996329921000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 1997329921000. Starting simulation... -info: Entering event queue @ 1999066205250. Starting simulation... -switching cpus -info: Entering event queue @ 1999066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2000066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2001066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2002066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2003066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2004066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2005066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2006066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2007066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2008066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2009066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2010066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2011066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2012066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2013066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2014066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2015066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2016066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2017066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2018066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2019066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2020066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2021066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2022066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2023066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2024066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2025066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2026066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2027066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2028066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2029066208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2030066208000. Starting simulation... -info: Entering event queue @ 2031802486250. Starting simulation... -switching cpus -info: Entering event queue @ 2031802489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2032802489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2033802489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2034802489000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2035802489000. Starting simulation... -switching cpus -info: Entering event queue @ 2035802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2036802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2037802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2038802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2039802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2040802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2041802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2042802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2043802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2044802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2045802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2046802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2047802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2048802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2049802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2050802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2051802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2052802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2053802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2054802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2055802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2056802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2057802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2058802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2059802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2060802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2061802496500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2062802496500. Starting simulation... -info: Entering event queue @ 2064538734250. Starting simulation... -switching cpus -info: Entering event queue @ 2064538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2065538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2066538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2067538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2068538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2069538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2070538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2071538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2072538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2073538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2074538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2075538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2076538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2077538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2078538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2079538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2080538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2081538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2082538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2083538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2084538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2085538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2086538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2087538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2088538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2089538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2090538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2091538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2092538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2093538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2094538737000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2095538737000. Starting simulation... -info: Entering event queue @ 2097275022250. Starting simulation... -switching cpus -info: Entering event queue @ 2097275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2098275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2099275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2100275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2101275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2102275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2103275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2104275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2105275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2106275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2107275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2108275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2109275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2110275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2111275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2112275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2113275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2114275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2115275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2116275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2117275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2118275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2119275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2120275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2121275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2122275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2123275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2124275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2125275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2126275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2127275025000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2128275025000. Starting simulation... -info: Entering event queue @ 2130011306250. Starting simulation... -switching cpus -info: Entering event queue @ 2130011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2131011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2132011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2133011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2134011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2135011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2136011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2137011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2138011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2139011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2140011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2141011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2142011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2143011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2144011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2145011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2146011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2147011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2148011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2149011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2150011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2151011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2152011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2153011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2154011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2155011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2156011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2157011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2158011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2159011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2160011309000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2161011309000. Starting simulation... -info: Entering event queue @ 2162747241250. Starting simulation... -switching cpus -info: Entering event queue @ 2162747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2163747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2164747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2165747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2166747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2167747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2168747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2169747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2170747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2171747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2172747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2173747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2174747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2175747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2176747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2177747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2178747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2179747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2180747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2181747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2182747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2183747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2184747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2185747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2186747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2187747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2188747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2189747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2190747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2191747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2192747244000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2193747244000. Starting simulation... -info: Entering event queue @ 2195483842250. Starting simulation... -switching cpus -info: Entering event queue @ 2195483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2196483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2197483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2198483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2199483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2200483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2201483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2202483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2203483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2204483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2205483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2206483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2207483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2208483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2209483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2210483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2211483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2212483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2213483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2214483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2215483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2216483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2217483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2218483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2219483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2220483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2221483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2222483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2223483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2224483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2225483845000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2226483845000. Starting simulation... -info: Entering event queue @ 2228219817250. Starting simulation... -switching cpus -info: Entering event queue @ 2228219820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2229219820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2230219820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2231219820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2232219820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2233219820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2234219820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2235219820000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2236219820000. Starting simulation... -switching cpus -info: Entering event queue @ 2236219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2237219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2238219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2239219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2240219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2241219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2242219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2243219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2244219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2245219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2246219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2247219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2248219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2249219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2250219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2251219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2252219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2253219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2254219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2255219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2256219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2257219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2258219827500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2259219827500. Starting simulation... -info: Entering event queue @ 2260956062250. Starting simulation... -switching cpus -info: Entering event queue @ 2260956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2261956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2262956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2263956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2264956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2265956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2266956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2267956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2268956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2269956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2270956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2271956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2272956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2273956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2274956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2275956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2276956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2277956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2278956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2279956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2280956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2281956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2282956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2283956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2284956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2285956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2286956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2287956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2288956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2289956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2290956065000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2291956065000. Starting simulation... -info: Entering event queue @ 2293692349250. Starting simulation... -switching cpus -info: Entering event queue @ 2293692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2294692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2295692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2296692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2297692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2298692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2299692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2300692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2301692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2302692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2303692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2304692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2305692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2306692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2307692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2308692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2309692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2310692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2311692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2312692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2313692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2314692352000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2315692352000. Starting simulation... -switching cpus -info: Entering event queue @ 2315692410000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2316692410000. Starting simulation... -switching cpus -info: Entering event queue @ 2316692443000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2317692443000. Starting simulation... -switching cpus -info: Entering event queue @ 2317692450500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2318692450500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2319692450500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2320692450500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2321692450500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2322692450500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2323692450500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2324692450500. Starting simulation... -info: Entering event queue @ 2326428637250. Starting simulation... -switching cpus -info: Entering event queue @ 2326428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2327428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2328428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2329428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2330428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2331428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2332428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2333428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2334428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2335428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2336428640000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2337428640000. Starting simulation... -switching cpus -info: Entering event queue @ 2337428647500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2338428647500. Starting simulation... -switching cpus -info: Entering event queue @ 2338428655000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2339428655000. Starting simulation... -switching cpus -info: Entering event queue @ 2339428750000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2340428750000. Starting simulation... -switching cpus -info: Entering event queue @ 2340428757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2341428757500. Starting simulation... -switching cpus -info: Entering event queue @ 2341428765000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2342428765000. Starting simulation... -switching cpus -info: Entering event queue @ 2342428793000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2343428793000. Starting simulation... -switching cpus -info: Entering event queue @ 2343428910000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2344428910000. Starting simulation... -switching cpus -info: Entering event queue @ 2344428917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2345428917500. Starting simulation... -switching cpus -info: Entering event queue @ 2345429049000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2346429049000. Starting simulation... -switching cpus -info: Entering event queue @ 2346429169000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2347429169000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2348429169000. Starting simulation... -switching cpus -info: Entering event queue @ 2348429176500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2349429176500. Starting simulation... -switching cpus -info: Entering event queue @ 2349429190000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2350429190000. Starting simulation... -switching cpus -info: Entering event queue @ 2350429305000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2351429305000. Starting simulation... -switching cpus -info: Entering event queue @ 2351429312500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2352429312500. Starting simulation... -switching cpus -info: Entering event queue @ 2352429345000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2353429345000. Starting simulation... -switching cpus -info: Entering event queue @ 2353429366000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2354429366000. Starting simulation... -switching cpus -info: Entering event queue @ 2354429463000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2355429463000. Starting simulation... -switching cpus -info: Entering event queue @ 2355429586000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2356429586000. Starting simulation... -switching cpus -info: Entering event queue @ 2356429633000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2357429633000. Starting simulation... -info: Entering event queue @ 2359165549250. Starting simulation... -switching cpus -info: Entering event queue @ 2359165552000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2360165552000. Starting simulation... -switching cpus -info: Entering event queue @ 2360165559500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2361165559500. Starting simulation... -switching cpus -info: Entering event queue @ 2361165567000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2362165567000. Starting simulation... -switching cpus -info: Entering event queue @ 2362165602000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2363165602000. Starting simulation... -switching cpus -info: Entering event queue @ 2363165722000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2364165722000. Starting simulation... -switching cpus -info: Entering event queue @ 2364165818000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2365165818000. Starting simulation... -switching cpus -info: Entering event queue @ 2365165956000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2366165956000. Starting simulation... -switching cpus -info: Entering event queue @ 2366166000000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2367166000000. Starting simulation... -switching cpus -info: Entering event queue @ 2367166007500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2368166007500. Starting simulation... -switching cpus -info: Entering event queue @ 2368166148000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2369166148000. Starting simulation... -switching cpus -info: Entering event queue @ 2369166232000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2370166232000. Starting simulation... -switching cpus -info: Entering event queue @ 2370166258000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2371166258000. Starting simulation... -switching cpus -info: Entering event queue @ 2371166376000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2372166376000. Starting simulation... -switching cpus -info: Entering event queue @ 2372166411000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2373166411000. Starting simulation... -switching cpus -info: Entering event queue @ 2373166428000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2374166428000. Starting simulation... -switching cpus -info: Entering event queue @ 2374166455000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2375166455000. Starting simulation... -switching cpus -info: Entering event queue @ 2375166576000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2376166576000. Starting simulation... -switching cpus -info: Entering event queue @ 2376166696000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2377166696000. Starting simulation... -switching cpus -info: Entering event queue @ 2377166781000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2378166781000. Starting simulation... -switching cpus -info: Entering event queue @ 2378166854000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2379166854000. Starting simulation... -switching cpus -info: Entering event queue @ 2379166934000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2380166934000. Starting simulation... -switching cpus -info: Entering event queue @ 2380167067000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2381167067000. Starting simulation... -switching cpus -info: Entering event queue @ 2381167110000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2382167110000. Starting simulation... -switching cpus -info: Entering event queue @ 2382167211000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2383167211000. Starting simulation... -switching cpus -info: Entering event queue @ 2383167257000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2384167257000. Starting simulation... -switching cpus -info: Entering event queue @ 2384167406000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2385167406000. Starting simulation... -switching cpus -info: Entering event queue @ 2385167550000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2386167550000. Starting simulation... -switching cpus -info: Entering event queue @ 2386167557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2387167557500. Starting simulation... -switching cpus -info: Entering event queue @ 2387167694000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2388167694000. Starting simulation... -switching cpus -info: Entering event queue @ 2388167701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2389167701500. Starting simulation... -switching cpus -info: Entering event queue @ 2389167857000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2390167857000. Starting simulation... -info: Entering event queue @ 2391903793250. Starting simulation... -switching cpus -info: Entering event queue @ 2391903869000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2392903869000. Starting simulation... -switching cpus -info: Entering event queue @ 2392903975000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2393903975000. Starting simulation... -switching cpus -info: Entering event queue @ 2393903982500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2394903982500. Starting simulation... -switching cpus -info: Entering event queue @ 2394903990000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2395903990000. Starting simulation... -switching cpus -info: Entering event queue @ 2395904067000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2396904067000. Starting simulation... -switching cpus -info: Entering event queue @ 2396904208000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2397904208000. Starting simulation... -switching cpus -info: Entering event queue @ 2397904284000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2398904284000. Starting simulation... -switching cpus -info: Entering event queue @ 2398904291500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2399904291500. Starting simulation... -switching cpus -info: Entering event queue @ 2399904429000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2400904429000. Starting simulation... -switching cpus -info: Entering event queue @ 2400904566000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2401904566000. Starting simulation... -switching cpus -info: Entering event queue @ 2401904685000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2402904685000. Starting simulation... -switching cpus -info: Entering event queue @ 2402904751000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2403904751000. Starting simulation... -switching cpus -info: Entering event queue @ 2403904799000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2404904799000. Starting simulation... -switching cpus -info: Entering event queue @ 2404904899000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2405904899000. Starting simulation... -switching cpus -info: Entering event queue @ 2405905038000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2406905038000. Starting simulation... -switching cpus -info: Entering event queue @ 2406905047000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2407905047000. Starting simulation... -switching cpus -info: Entering event queue @ 2407905061000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2408905061000. Starting simulation... -switching cpus -info: Entering event queue @ 2408905068500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2409905068500. Starting simulation... -switching cpus -info: Entering event queue @ 2409905214000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2410905214000. Starting simulation... -switching cpus -info: Entering event queue @ 2410905221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2411905221500. Starting simulation... -switching cpus -info: Entering event queue @ 2411905292000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2412905292000. Starting simulation... -switching cpus -info: Entering event queue @ 2412905313000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2413905313000. Starting simulation... -switching cpus -info: Entering event queue @ 2413905320500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2414905320500. Starting simulation... -switching cpus -info: Entering event queue @ 2414905328000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2415905328000. Starting simulation... -switching cpus -info: Entering event queue @ 2415905341000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2416905341000. Starting simulation... -switching cpus -info: Entering event queue @ 2416905490000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2417905490000. Starting simulation... -switching cpus -info: Entering event queue @ 2417905532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2418905532000. Starting simulation... -switching cpus -info: Entering event queue @ 2418905539500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2419905539500. Starting simulation... -switching cpus -info: Entering event queue @ 2419905643000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2420905643000. Starting simulation... -switching cpus -info: Entering event queue @ 2420905687000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2421905687000. Starting simulation... -switching cpus -info: Entering event queue @ 2421905694500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2422905694500. Starting simulation... -info: Entering event queue @ 2424637770250. Starting simulation... -switching cpus -info: Entering event queue @ 2424637773000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2425637773000. Starting simulation... -switching cpus -info: Entering event queue @ 2425637788000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2426637788000. Starting simulation... -switching cpus -info: Entering event queue @ 2426637903000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2427637903000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2428637903000. Starting simulation... -switching cpus -info: Entering event queue @ 2428638049000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2429638049000. Starting simulation... -switching cpus -info: Entering event queue @ 2429638099000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2430638099000. Starting simulation... -switching cpus -info: Entering event queue @ 2430638106500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2431638106500. Starting simulation... -switching cpus -info: Entering event queue @ 2431638195000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2432638195000. Starting simulation... -switching cpus -info: Entering event queue @ 2432638349000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2433638349000. Starting simulation... -switching cpus -info: Entering event queue @ 2433638486000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2434638486000. Starting simulation... -switching cpus -info: Entering event queue @ 2434638493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2435638493500. Starting simulation... -switching cpus -info: Entering event queue @ 2435638590000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2436638590000. Starting simulation... -switching cpus -info: Entering event queue @ 2436638614000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2437638614000. Starting simulation... -switching cpus -info: Entering event queue @ 2437638621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2438638621500. Starting simulation... -switching cpus -info: Entering event queue @ 2438638710000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2439638710000. Starting simulation... -switching cpus -info: Entering event queue @ 2439638725000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2440638725000. Starting simulation... -switching cpus -info: Entering event queue @ 2440638747000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2441638747000. Starting simulation... -switching cpus -info: Entering event queue @ 2441638754500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2442638754500. Starting simulation... -switching cpus -info: Entering event queue @ 2442638803000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2443638803000. Starting simulation... -switching cpus -info: Entering event queue @ 2443638912000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2444638912000. Starting simulation... -switching cpus -info: Entering event queue @ 2444639034000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2445639034000. Starting simulation... -switching cpus -info: Entering event queue @ 2445639125000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2446639125000. Starting simulation... -switching cpus -info: Entering event queue @ 2446639160000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2447639160000. Starting simulation... -switching cpus -info: Entering event queue @ 2447639271000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2448639271000. Starting simulation... -switching cpus -info: Entering event queue @ 2448639278500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2449639278500. Starting simulation... -switching cpus -info: Entering event queue @ 2449639286000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2450639286000. Starting simulation... -switching cpus -info: Entering event queue @ 2450639415000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2451639415000. Starting simulation... -switching cpus -info: Entering event queue @ 2451639552000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2452639552000. Starting simulation... -switching cpus -info: Entering event queue @ 2452639559500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2453639559500. Starting simulation... -switching cpus -info: Entering event queue @ 2453639643000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2454639643000. Starting simulation... -switching cpus -info: Entering event queue @ 2454639650500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2455639650500. Starting simulation... -info: Entering event queue @ 2457374369250. Starting simulation... -switching cpus -info: Entering event queue @ 2457374372000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2458374372000. Starting simulation... -switching cpus -info: Entering event queue @ 2458374511000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2459374511000. Starting simulation... -switching cpus -info: Entering event queue @ 2459374526000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2460374526000. Starting simulation... -switching cpus -info: Entering event queue @ 2460374533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2461374533500. Starting simulation... -switching cpus -info: Entering event queue @ 2461374550000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2462374550000. Starting simulation... -switching cpus -info: Entering event queue @ 2462374597000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2463374597000. Starting simulation... -switching cpus -info: Entering event queue @ 2463374619000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2464374619000. Starting simulation... -switching cpus -info: Entering event queue @ 2464374710000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2465374710000. Starting simulation... -switching cpus -info: Entering event queue @ 2465374766000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2466374766000. Starting simulation... -switching cpus -info: Entering event queue @ 2466374797000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2467374797000. Starting simulation... -switching cpus -info: Entering event queue @ 2467374945000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2468374945000. Starting simulation... -switching cpus -info: Entering event queue @ 2468374967000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2469374967000. Starting simulation... -switching cpus -info: Entering event queue @ 2469375044000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2470375044000. Starting simulation... -switching cpus -info: Entering event queue @ 2470375126000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2471375126000. Starting simulation... -switching cpus -info: Entering event queue @ 2471375215000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2472375215000. Starting simulation... -switching cpus -info: Entering event queue @ 2472375222500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2473375222500. Starting simulation... -switching cpus -info: Entering event queue @ 2473375265000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2474375265000. Starting simulation... -switching cpus -info: Entering event queue @ 2474375295000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2475375295000. Starting simulation... -switching cpus -info: Entering event queue @ 2475375442000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2476375442000. Starting simulation... -switching cpus -info: Entering event queue @ 2476375449500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2477375449500. Starting simulation... -switching cpus -info: Entering event queue @ 2477375520000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2478375520000. Starting simulation... -switching cpus -info: Entering event queue @ 2478375603000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2479375603000. Starting simulation... -switching cpus -info: Entering event queue @ 2479375656000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2480375656000. Starting simulation... -switching cpus -info: Entering event queue @ 2480375751000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2481375751000. Starting simulation... -switching cpus -info: Entering event queue @ 2481375870000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2482375870000. Starting simulation... -switching cpus -info: Entering event queue @ 2482375877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2483375877500. Starting simulation... -switching cpus -info: Entering event queue @ 2483375900000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2484375900000. Starting simulation... -switching cpus -info: Entering event queue @ 2484375923000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2485375923000. Starting simulation... -switching cpus -info: Entering event queue @ 2485376001000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2486376001000. Starting simulation... -switching cpus -info: Entering event queue @ 2486376008500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2487376008500. Starting simulation... -switching cpus -info: Entering event queue @ 2487376146000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2488376146000. Starting simulation... -info: Entering event queue @ 2490110657250. Starting simulation... -switching cpus -info: Entering event queue @ 2490110660000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2491110660000. Starting simulation... -switching cpus -info: Entering event queue @ 2491110682000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2492110682000. Starting simulation... -switching cpus -info: Entering event queue @ 2492110689500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2493110689500. Starting simulation... -switching cpus -info: Entering event queue @ 2493110765000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2494110765000. Starting simulation... -switching cpus -info: Entering event queue @ 2494110772500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2495110772500. Starting simulation... -switching cpus -info: Entering event queue @ 2495110780000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2496110780000. Starting simulation... -switching cpus -info: Entering event queue @ 2496110878000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2497110878000. Starting simulation... -switching cpus -info: Entering event queue @ 2497111028000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2498111028000. Starting simulation... -switching cpus -info: Entering event queue @ 2498111170000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2499111170000. Starting simulation... -switching cpus -info: Entering event queue @ 2499111184000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2500111184000. Starting simulation... -switching cpus -info: Entering event queue @ 2500111332000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2501111332000. Starting simulation... -switching cpus -info: Entering event queue @ 2501111339500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2502111339500. Starting simulation... -switching cpus -info: Entering event queue @ 2502111354000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2503111354000. Starting simulation... -switching cpus -info: Entering event queue @ 2503111446000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2504111446000. Starting simulation... -switching cpus -info: Entering event queue @ 2504111532000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2505111532000. Starting simulation... -switching cpus -info: Entering event queue @ 2505111539500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2506111539500. Starting simulation... -switching cpus -info: Entering event queue @ 2506111646000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2507111646000. Starting simulation... -switching cpus -info: Entering event queue @ 2507111682000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2508111682000. Starting simulation... -switching cpus -info: Entering event queue @ 2508111689500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2509111689500. Starting simulation... -switching cpus -info: Entering event queue @ 2509111831000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2510111831000. Starting simulation... -switching cpus -info: Entering event queue @ 2510111941000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2511111941000. Starting simulation... -switching cpus -info: Entering event queue @ 2511111948500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2512111948500. Starting simulation... -switching cpus -info: Entering event queue @ 2512111990000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2513111990000. Starting simulation... -switching cpus -info: Entering event queue @ 2513112001000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2514112001000. Starting simulation... -switching cpus -info: Entering event queue @ 2514112009000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2515112009000. Starting simulation... -switching cpus -info: Entering event queue @ 2515112016500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2516112016500. Starting simulation... -switching cpus -info: Entering event queue @ 2516112091000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2517112091000. Starting simulation... -switching cpus -info: Entering event queue @ 2517112172000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2518112172000. Starting simulation... -switching cpus -info: Entering event queue @ 2518112317000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2519112317000. Starting simulation... -switching cpus -info: Entering event queue @ 2519112324500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2520112324500. Starting simulation... -switching cpus -info: Entering event queue @ 2520112394000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2521112394000. Starting simulation... -info: Entering event queue @ 2522846938250. Starting simulation... -switching cpus -info: Entering event queue @ 2522846941000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2523846941000. Starting simulation... -switching cpus -info: Entering event queue @ 2523846948500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2524846948500. Starting simulation... -switching cpus -info: Entering event queue @ 2524847092000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2525847092000. Starting simulation... -switching cpus -info: Entering event queue @ 2525847224000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2526847224000. Starting simulation... -switching cpus -info: Entering event queue @ 2526847351000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2527847351000. Starting simulation... -switching cpus -info: Entering event queue @ 2527847362000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2528847362000. Starting simulation... -info: Entering event queue @ 2528847390000. Starting simulation... -switching cpus -info: Entering event queue @ 2528847597000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2529847597000. Starting simulation... -switching cpus -info: Entering event queue @ 2529847604500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2530847604500. Starting simulation... -switching cpus -info: Entering event queue @ 2530847667000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2531847667000. Starting simulation... -switching cpus -info: Entering event queue @ 2531847805000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2532847805000. Starting simulation... -switching cpus -info: Entering event queue @ 2532847812500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2533847812500. Starting simulation... -switching cpus -info: Entering event queue @ 2533847917000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2534847917000. Starting simulation... -switching cpus -info: Entering event queue @ 2534847924500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2535847924500. Starting simulation... -switching cpus -info: Entering event queue @ 2535847932000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2536847932000. Starting simulation... -switching cpus -info: Entering event queue @ 2536847958000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2537847958000. Starting simulation... -switching cpus -info: Entering event queue @ 2537847987000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2538847987000. Starting simulation... -switching cpus -info: Entering event queue @ 2538848125000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2539848125000. Starting simulation... -switching cpus -info: Entering event queue @ 2539848132500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2540848132500. Starting simulation... -switching cpus -info: Entering event queue @ 2540848144000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2541848144000. Starting simulation... -switching cpus -info: Entering event queue @ 2541848249000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2542848249000. Starting simulation... -switching cpus -info: Entering event queue @ 2542848256500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2543848256500. Starting simulation... -switching cpus -info: Entering event queue @ 2543848264000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2544848264000. Starting simulation... -switching cpus -info: Entering event queue @ 2544848271500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2545848271500. Starting simulation... -switching cpus -info: Entering event queue @ 2545848283000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2546848283000. Starting simulation... -switching cpus -info: Entering event queue @ 2546848427000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2547848427000. Starting simulation... -switching cpus -info: Entering event queue @ 2547848471000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2548848471000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2549848471000. Starting simulation... -switching cpus -info: Entering event queue @ 2549848567000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2550848567000. Starting simulation... -switching cpus -info: Entering event queue @ 2550848594000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2551848594000. Starting simulation... -switching cpus -info: Entering event queue @ 2551848739000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2552848739000. Starting simulation... -switching cpus -info: Entering event queue @ 2552848772000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2553848772000. Starting simulation... -info: Entering event queue @ 2555582877250. Starting simulation... -switching cpus -info: Entering event queue @ 2555582880000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2556582880000. Starting simulation... -switching cpus -info: Entering event queue @ 2556582963000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2557582963000. Starting simulation... -switching cpus -info: Entering event queue @ 2557582970500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2558582970500. Starting simulation... -switching cpus -info: Entering event queue @ 2558583082000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2559583082000. Starting simulation... -switching cpus -info: Entering event queue @ 2559583164000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2560583164000. Starting simulation... -switching cpus -info: Entering event queue @ 2560583171500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2561583171500. Starting simulation... -info: Entering event queue @ 2561583230000. Starting simulation... -switching cpus -info: Entering event queue @ 2561583429750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2562583429750. Starting simulation... -switching cpus -info: Entering event queue @ 2562583496000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2563583496000. Starting simulation... -switching cpus -info: Entering event queue @ 2563583643000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2564583643000. Starting simulation... -switching cpus -info: Entering event queue @ 2564583650500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2565583650500. Starting simulation... -switching cpus -info: Entering event queue @ 2565583710000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2566583710000. Starting simulation... -switching cpus -info: Entering event queue @ 2566583851000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2567583851000. Starting simulation... -switching cpus -info: Entering event queue @ 2567584002000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2568584002000. Starting simulation... -switching cpus -info: Entering event queue @ 2568584009500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2569584009500. Starting simulation... -switching cpus -info: Entering event queue @ 2569584017000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2570584017000. Starting simulation... -switching cpus -info: Entering event queue @ 2570584089000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2571584089000. Starting simulation... -switching cpus -info: Entering event queue @ 2571584096500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2572584096500. Starting simulation... -switching cpus -info: Entering event queue @ 2572584190000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2573584190000. Starting simulation... -switching cpus -info: Entering event queue @ 2573584197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2574584197500. Starting simulation... -switching cpus -info: Entering event queue @ 2574584350000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2575584350000. Starting simulation... -switching cpus -info: Entering event queue @ 2575584357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2576584357500. Starting simulation... -switching cpus -info: Entering event queue @ 2576584365000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2577584365000. Starting simulation... -switching cpus -info: Entering event queue @ 2577584454000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2578584454000. Starting simulation... -switching cpus -info: Entering event queue @ 2578584461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2579584461500. Starting simulation... -switching cpus -info: Entering event queue @ 2579584495000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2580584495000. Starting simulation... -switching cpus -info: Entering event queue @ 2580584642000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2581584642000. Starting simulation... -switching cpus -info: Entering event queue @ 2581584673000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2582584673000. Starting simulation... -switching cpus -info: Entering event queue @ 2582584799000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2583584799000. Starting simulation... -switching cpus -info: Entering event queue @ 2583584838000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2584584838000. Starting simulation... -switching cpus -info: Entering event queue @ 2584584958000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2585584958000. Starting simulation... -switching cpus -info: Entering event queue @ 2585585101000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2586585101000. Starting simulation... -info: Entering event queue @ 2588319477250. Starting simulation... -switching cpus -info: Entering event queue @ 2588319480000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2589319480000. Starting simulation... -switching cpus -info: Entering event queue @ 2589319487500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2590319487500. Starting simulation... -switching cpus -info: Entering event queue @ 2590319506000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2591319506000. Starting simulation... -switching cpus -info: Entering event queue @ 2591319513500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2592319513500. Starting simulation... -switching cpus -info: Entering event queue @ 2592319521000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2593319521000. Starting simulation... -switching cpus -info: Entering event queue @ 2593319528500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2594319528500. Starting simulation... -switching cpus -info: Entering event queue @ 2594319578000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2595319578000. Starting simulation... -switching cpus -info: Entering event queue @ 2595319585500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2596319585500. Starting simulation... -switching cpus -info: Entering event queue @ 2596319687000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2597319687000. Starting simulation... -switching cpus -info: Entering event queue @ 2597319740000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2598319740000. Starting simulation... -switching cpus -info: Entering event queue @ 2598319767000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2599319767000. Starting simulation... -switching cpus -info: Entering event queue @ 2599319774500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2600319774500. Starting simulation... -switching cpus -info: Entering event queue @ 2600319782000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2601319782000. Starting simulation... -switching cpus -info: Entering event queue @ 2601319789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2602319789500. Starting simulation... -switching cpus -info: Entering event queue @ 2602319797000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2603319797000. Starting simulation... -switching cpus -info: Entering event queue @ 2603319799500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2604319799500. Starting simulation... -switching cpus -info: Entering event queue @ 2604319800000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2605319800000. Starting simulation... -switching cpus -info: Entering event queue @ 2605319807500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2606319807500. Starting simulation... -switching cpus -info: Entering event queue @ 2606319815000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2607319815000. Starting simulation... -info: Entering event queue @ 2607319822500. Starting simulation... -switching cpus -info: Entering event queue @ 2607319825500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2608319825500. Starting simulation... -switching cpus -info: Entering event queue @ 2608319833000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2609319833000. Starting simulation... -switching cpus -info: Entering event queue @ 2609319840500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2610319840500. Starting simulation... -switching cpus -info: Entering event queue @ 2610319848000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2611319848000. Starting simulation... -switching cpus -info: Entering event queue @ 2611319855500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2612319855500. Starting simulation... -switching cpus -info: Entering event queue @ 2612319863000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2613319863000. Starting simulation... -switching cpus -info: Entering event queue @ 2613319870500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2614319870500. Starting simulation... -switching cpus -info: Entering event queue @ 2614319871000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2615319871000. Starting simulation... -switching cpus -info: Entering event queue @ 2615319878500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2616319878500. Starting simulation... -info: Entering event queue @ 2616319886000. Starting simulation... -switching cpus -info: Entering event queue @ 2616319887000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2617319887000. Starting simulation... -switching cpus -info: Entering event queue @ 2617319894500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2618319894500. Starting simulation... -switching cpus -info: Entering event queue @ 2618319896500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2619319896500. Starting simulation... -info: Entering event queue @ 2621055410250. Starting simulation... -switching cpus -info: Entering event queue @ 2621055413000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2622055413000. Starting simulation... -switching cpus -info: Entering event queue @ 2622055452000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2623055452000. Starting simulation... -switching cpus -info: Entering event queue @ 2623055459500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2624055459500. Starting simulation... -switching cpus -info: Entering event queue @ 2624055612000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2625055612000. Starting simulation... -switching cpus -info: Entering event queue @ 2625055673000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2626055673000. Starting simulation... -switching cpus -info: Entering event queue @ 2626055680500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2627055680500. Starting simulation... -info: Entering event queue @ 2627055945000. Starting simulation... -switching cpus -info: Entering event queue @ 2627055952500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2628055952500. Starting simulation... -info: Entering event queue @ 2628055960000. Starting simulation... -switching cpus -info: Entering event queue @ 2628055963000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2629055963000. Starting simulation... -switching cpus -info: Entering event queue @ 2629055970500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2630055970500. Starting simulation... -switching cpus -info: Entering event queue @ 2630055978000. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 98143dc12..e79723ba6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,25 +4,15 @@ sim_seconds 2.629717 # Nu sim_ticks 2629717216500 # Number of ticks simulated final_tick 2629717216500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 340896 # Simulator instruction rate (inst/s) -host_op_rate 433786 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 14888327014 # Simulator tick rate (ticks/s) -host_mem_usage 445372 # Number of bytes of host memory used -host_seconds 176.63 # Real time elapsed on the host +host_inst_rate 592417 # Simulator instruction rate (inst/s) +host_op_rate 753843 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25873243563 # Simulator tick rate (ticks/s) +host_mem_usage 401372 # Number of bytes of host memory used +host_seconds 101.64 # Real time elapsed on the host sim_insts 60212334 # Number of instructions simulated sim_ops 76619433 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 298016 # Number of bytes read from this memory @@ -509,6 +499,18 @@ system.physmem.writeRowHitRate 85.11 # Ro system.physmem.avgGap 159351.16 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined system.physmem.prechargeAllPercent 2.39 # Percentage of time for which DRAM has all the banks in precharge state +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.membus.throughput 54426353 # Throughput (bytes/s) system.membus.trans_dist::ReadReq 16743636 # Transaction distribution system.membus.trans_dist::ReadResp 16743636 # Transaction distribution @@ -553,6 +555,7 @@ system.membus.respLayer1.occupancy 4990533473 # La system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 35075577250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 62046 # number of replacements system.l2c.tags.tagsinuse 51605.865819 # Cycle average of tags in use system.l2c.tags.total_refs 1699437 # Total number of references to valid blocks. @@ -574,6 +577,15 @@ system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 system.l2c.tags.occ_percent::cpu1.inst 0.065179 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.049955 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.787443 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6483 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56716 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17277508 # Number of tag accesses +system.l2c.tags.data_accesses 17277508 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 9827 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 3607 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 412393 # number of ReadReq hits @@ -1124,6 +1136,14 @@ system.cpu0.icache.tags.occ_blocks::cpu1.inst 293.610060 system.cpu0.icache.tags.occ_percent::cpu0.inst 0.424303 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu1.inst 0.573457 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997760 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 62363171 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62363171 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 30192721 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 30456964 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 60649685 # number of ReadReq hits @@ -1246,6 +1266,13 @@ system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.082879 system.cpu0.dcache.tags.occ_percent::cpu0.data 0.360927 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638834 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999760 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 330 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 97784680 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 97784680 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 6519451 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 6679636 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 13199087 # number of ReadReq hits @@ -1503,6 +1530,8 @@ system.iocache.tags.total_refs 0 # To system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. system.iocache.tags.avg_refs nan # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.tag_accesses 0 # Number of tag accesses +system.iocache.tags.data_accesses 0 # Number of data accesses system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini index c331380ec..04fd84fb1 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -211,6 +211,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.dcache.tags @@ -227,6 +228,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.dtb] @@ -259,6 +261,7 @@ mshrs=10 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=1024 system=system tags=system.cpu.dtb_walker_cache.tags @@ -275,6 +278,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=1024 [system.cpu.fuPool] @@ -599,6 +603,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu.icache.tags @@ -615,6 +620,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu.interrupts] @@ -663,6 +669,7 @@ mshrs=10 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=1024 system=system tags=system.cpu.itb_walker_cache.tags @@ -679,6 +686,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=1024 [system.cpu.l2cache] @@ -696,6 +704,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.cpu.l2cache.tags @@ -712,6 +721,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.cpu.toL2Bus] @@ -1178,6 +1188,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -1194,6 +1205,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.membus] @@ -1523,7 +1535,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1546,7 +1558,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr index 96081bfab..0067e63a5 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr @@ -1,4 +1,3 @@ -warn: add_child('terminal'): child 'terminal' already has parent warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections @@ -10,4 +9,3 @@ warn: x86 cpuid: unimplemented function 8 warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. warn: instruction 'wbinvd' unimplemented -hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout index b43511df7..4c2ae2163 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:57:32 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 22:15:55 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5149801602000 because m5_exit instruction encountered +Exiting @ tick 5133933067000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index f9f231b7b..467207c9e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 5.133933 # Nu sim_ticks 5133933067000 # Number of ticks simulated final_tick 5133933067000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121984 # Simulator instruction rate (inst/s) -host_op_rate 241126 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1535878817 # Simulator tick rate (ticks/s) -host_mem_usage 781700 # Number of bytes of host memory used -host_seconds 3342.67 # Real time elapsed on the host +host_inst_rate 186687 # Simulator instruction rate (inst/s) +host_op_rate 369023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2350538489 # Simulator tick rate (ticks/s) +host_mem_usage 736008 # Number of bytes of host memory used +host_seconds 2184.15 # Real time elapsed on the host sim_insts 407751929 # Number of instructions simulated sim_ops 806002693 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 2437184 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 3904 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory @@ -473,6 +475,11 @@ system.iocache.tags.warmup_cycle 4992951939000 # C system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103980 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006499 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.006499 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428679 # Number of tag accesses +system.iocache.tags.data_accesses 428679 # Number of data accesses system.iocache.ReadReq_misses::pc.south_bridge.ide 911 # number of ReadReq misses system.iocache.ReadReq_misses::total 911 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -670,6 +677,7 @@ system.iobus.respLayer1.occupancy 53080252 # La system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 1642000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 85602749 # Number of BP lookups system.cpu.branchPred.condPredicted 85602749 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 882967 # Number of conditional branches incorrect @@ -679,6 +687,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 97.955165 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1444593 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 180696 # Number of incorrect RAS predictions. +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 453810576 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -986,6 +995,13 @@ system.cpu.icache.tags.warmup_cycle 147611306250 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 509.254964 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994639 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994639 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 215 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 196 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 9447804 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9447804 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 7477774 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 7477774 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 7477774 # number of demand (read+write) hits @@ -1070,6 +1086,13 @@ system.cpu.itb_walker_cache.tags.warmup_cycle 5105549292500 system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.004704 # Average occupied blocks per requestor system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375294 # Average percentage of cache occupancy system.cpu.itb_walker_cache.tags.occ_percent::total 0.375294 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 70243 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 70243 # Number of data accesses system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 20415 # number of ReadReq hits system.cpu.itb_walker_cache.ReadReq_hits::total 20415 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits @@ -1154,6 +1177,13 @@ system.cpu.dtb_walker_cache.tags.warmup_cycle 4994240386000 system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 14.842846 # Average occupied blocks per requestor system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.927678 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_percent::total 0.927678 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 390650 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 390650 # Number of data accesses system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 91726 # number of ReadReq hits system.cpu.dtb_walker_cache.ReadReq_hits::total 91726 # number of ReadReq hits system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 91726 # number of demand (read+write) hits @@ -1234,6 +1264,13 @@ system.cpu.dcache.tags.warmup_cycle 39724250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 511.997280 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999995 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999995 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 87846935 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 87846935 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 10898836 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 10898836 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 8096443 # number of WriteReq hits @@ -1362,6 +1399,15 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.045815 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.167251 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.989141 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63963 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 514 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3380 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54576 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.975998 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 34635418 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 34635418 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 64096 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 7642 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.inst 942107 # number of ReadReq hits diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini index f745e2f55..1b99afe98 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9.smp load_addr_mask=18446744073709551615 mem_mode=timing mem_ranges=0:134217727 @@ -968,7 +968,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -991,7 +991,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr index 4291cf7c2..9a873dc2a 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simerr @@ -1,4 +1,3 @@ -warn: add_child('terminal'): child 'terminal' already has parent warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections @@ -10,4 +9,3 @@ warn: x86 cpuid: unknown family 0x8086 hack: Assuming logical destinations are 1 << id. warn: Tried to clear PCI interrupt 14 warn: Unknown mouse command 0xe1. -hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout index ada852a91..f1f8b95c3 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:55:52 -gem5 started Oct 16 2013 01:57:05 -gem5 executing on zizzer -command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory +gem5 compiled Jan 22 2014 17:16:50 +gem5 started Jan 22 2014 22:26:32 +gem5 executing on u200540-lin +command line: build/X86_MESI_Two_Level/gem5.opt -d build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level -re tests/run.py build/X86_MESI_Two_Level/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_Two_Level Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp +info: kernel located at: /dist/binaries/x86_64-vmlinux-2.6.22.9.smp 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 5304492233500 because m5_exit instruction encountered +Exiting @ tick 5300435735500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 4656948e4..a38bc5b98 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -4,13 +4,15 @@ sim_seconds 5.300436 # Nu sim_ticks 5300435735500 # Number of ticks simulated final_tick 5300435735500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127150 # Simulator instruction rate (inst/s) -host_op_rate 243807 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6308537728 # Simulator tick rate (ticks/s) -host_mem_usage 832728 # Number of bytes of host memory used -host_seconds 840.20 # Real time elapsed on the host +host_inst_rate 165870 # Simulator instruction rate (inst/s) +host_op_rate 318050 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8229583651 # Simulator tick rate (ticks/s) +host_mem_usage 786300 # Number of bytes of host memory used +host_seconds 644.07 # Real time elapsed on the host sim_insts 106831806 # Number of instructions simulated sim_ops 204847037 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 35184 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 121960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 61480 # Number of bytes read from this memory @@ -364,6 +366,7 @@ system.piobus.respLayer3.occupancy 151500 # La system.piobus.respLayer3.utilization 0.0 # Layer utilization (%) system.piobus.respLayer4.occupancy 151500 # Layer occupancy (ticks) system.piobus.respLayer4.utilization 0.0 # Layer utilization (%) +system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 2 # delay histogram for all message system.ruby.delayHist::max_bucket 19 # delay histogram for all message system.ruby.delayHist::samples 10855755 # delay histogram for all message @@ -489,6 +492,7 @@ system.ruby.network.routers2.msg_bytes.Response_Control::2 14052096 system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41308992 system.ruby.network.routers2.msg_bytes.Writeback_Data::1 21888 system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8867440 +system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks system.ruby.dir_cntrl0.memBuffer.memReq 317877 # Total number of memory requests system.ruby.dir_cntrl0.memBuffer.memRead 175365 # Number of memory reads system.ruby.dir_cntrl0.memBuffer.memWrite 142512 # Number of memory writes @@ -566,6 +570,8 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu0.numCycles 10600871471 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -592,6 +598,7 @@ system.cpu0.not_idle_fraction 0.048149 # Pe system.cpu0.idle_fraction 0.951851 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu1.numCycles 10598039537 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini index 4079b1ad3..42cb40700 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini @@ -20,7 +20,7 @@ eventq_index=0 init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic mem_ranges=0:134217727 @@ -144,6 +144,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags @@ -160,6 +161,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.dtb] @@ -192,6 +194,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags @@ -208,6 +211,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=32768 [system.cpu0.interrupts] @@ -1205,6 +1209,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=50 +sequential_access=false size=1024 system=system tags=system.iocache.tags @@ -1221,6 +1226,7 @@ block_size=64 clk_domain=system.clk_domain eventq_index=0 hit_latency=50 +sequential_access=false size=1024 [system.l2c] @@ -1238,6 +1244,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=4194304 system=system tags=system.l2c.tags @@ -1254,6 +1261,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=4194304 [system.membus] @@ -1583,7 +1591,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -1606,7 +1614,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage eventq_index=0 -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr index 99453da63..246bb0fe6 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr @@ -1,9 +1,7 @@ -warn: add_child('terminal'): child 'terminal' already has parent warn: Sockets disabled, not accepting terminal connections warn: Reading current count from inactive timer. warn: Sockets disabled, not accepting gdb connections warn: Don't know what interrupt to clear for console. -hack: be nice to actually delete the event here warn: x86 cpuid: unknown family 0xbacc warn: x86 cpuid: unknown family 0x8086 warn: x86 cpuid: unknown family 0x8086 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout index 38a90266b..860a4f6c8 100755 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout @@ -1,17178 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:38:05 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 22:25:31 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 -info: Entering event queue @ 0. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1000000000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 2000000000. Starting simulation... -switching cpus -info: Entering event queue @ 2000001000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3000001000. Starting simulation... -switching cpus -info: Entering event queue @ 3000009000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4000009000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5000009000. Starting simulation... -switching cpus -info: Entering event queue @ 5000098000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 6000098000. Starting simulation... -switching cpus -info: Entering event queue @ 6000272500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 7000272500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 8000272500. Starting simulation... -switching cpus -info: Entering event queue @ 8000346000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 9000346000. Starting simulation... -switching cpus -info: Entering event queue @ 9000506500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 10000506500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 11000506500. Starting simulation... -switching cpus -info: Entering event queue @ 11000580000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 12000580000. Starting simulation... -switching cpus -info: Entering event queue @ 12000740500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 13000740500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 14000740500. Starting simulation... -switching cpus -info: Entering event queue @ 14000814000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 15000814000. Starting simulation... -switching cpus -info: Entering event queue @ 15000974500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 16000974500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 17000974500. Starting simulation... -switching cpus -info: Entering event queue @ 17001048000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 18001048000. Starting simulation... -switching cpus -info: Entering event queue @ 18001208500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 19001208500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 20001208500. Starting simulation... -switching cpus -info: Entering event queue @ 20001282000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 21001282000. Starting simulation... -switching cpus -info: Entering event queue @ 21001442500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 22001442500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 23001442500. Starting simulation... -switching cpus -info: Entering event queue @ 23001516000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 24001516000. Starting simulation... -switching cpus -info: Entering event queue @ 24001676500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 25001676500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 26001676500. Starting simulation... -switching cpus -info: Entering event queue @ 26001750000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 27001750000. Starting simulation... -switching cpus -info: Entering event queue @ 27001910500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 28001910500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 29001910500. Starting simulation... -switching cpus -info: Entering event queue @ 29001984000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 30001984000. Starting simulation... -switching cpus -info: Entering event queue @ 30002144500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 31002144500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 32002144500. Starting simulation... -switching cpus -info: Entering event queue @ 32002218000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 33002218000. Starting simulation... -switching cpus -info: Entering event queue @ 33002378500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 34002378500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 35002378500. Starting simulation... -switching cpus -info: Entering event queue @ 35002452000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 36002452000. Starting simulation... -switching cpus -info: Entering event queue @ 36002612500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 37002612500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 38002612500. Starting simulation... -switching cpus -info: Entering event queue @ 38002686000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 39002686000. Starting simulation... -switching cpus -info: Entering event queue @ 39002846500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 40002846500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 41002846500. Starting simulation... -switching cpus -info: Entering event queue @ 41002920000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 42002920000. Starting simulation... -switching cpus -info: Entering event queue @ 42003080500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 43003080500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 44003080500. Starting simulation... -switching cpus -info: Entering event queue @ 44003154000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 45003154000. Starting simulation... -switching cpus -info: Entering event queue @ 45003314500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 46003314500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 47003314500. Starting simulation... -switching cpus -info: Entering event queue @ 47003388000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 48003388000. Starting simulation... -switching cpus -info: Entering event queue @ 48003548500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 49003548500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 50003548500. Starting simulation... -switching cpus -info: Entering event queue @ 50003622000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 51003622000. Starting simulation... -switching cpus -info: Entering event queue @ 51003782500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 52003782500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 53003782500. Starting simulation... -switching cpus -info: Entering event queue @ 53003856000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 54003856000. Starting simulation... -switching cpus -info: Entering event queue @ 54004016500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 55004016500. Starting simulation... -switching cpus -info: Entering event queue @ 55004017500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 56004017500. Starting simulation... -switching cpus -info: Entering event queue @ 56004018000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 57004018000. Starting simulation... -switching cpus -info: Entering event queue @ 57004209500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 58004209500. Starting simulation... -switching cpus -info: Entering event queue @ 58004210500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 59004210500. Starting simulation... -switching cpus -info: Entering event queue @ 59004211000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 60004211000. Starting simulation... -switching cpus -info: Entering event queue @ 60004215000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 61004215000. Starting simulation... -switching cpus -info: Entering event queue @ 61004215500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 62004215500. Starting simulation... -switching cpus -info: Entering event queue @ 62004216000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 63004216000. Starting simulation... -switching cpus -info: Entering event queue @ 63004220000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 64004220000. Starting simulation... -switching cpus -info: Entering event queue @ 64004221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 65004221500. Starting simulation... -switching cpus -info: Entering event queue @ 65004222000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 66004222000. Starting simulation... -switching cpus -info: Entering event queue @ 66004232000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 67004232000. Starting simulation... -switching cpus -info: Entering event queue @ 67004232500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 68004232500. Starting simulation... -switching cpus -info: Entering event queue @ 68004233000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 69004233000. Starting simulation... -switching cpus -info: Entering event queue @ 69004237000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 70004237000. Starting simulation... -switching cpus -info: Entering event queue @ 70004238500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 71004238500. Starting simulation... -switching cpus -info: Entering event queue @ 71004239000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 72004239000. Starting simulation... -switching cpus -info: Entering event queue @ 72004243000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 73004243000. Starting simulation... -switching cpus -info: Entering event queue @ 73004244500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 74004244500. Starting simulation... -switching cpus -info: Entering event queue @ 74004245000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 75004245000. Starting simulation... -switching cpus -info: Entering event queue @ 75004255000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 76004255000. Starting simulation... -switching cpus -info: Entering event queue @ 76004256500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 77004256500. Starting simulation... -switching cpus -info: Entering event queue @ 77004257000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 78004257000. Starting simulation... -switching cpus -info: Entering event queue @ 78004267000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 79004267000. Starting simulation... -switching cpus -info: Entering event queue @ 79004267500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 80004267500. Starting simulation... -switching cpus -info: Entering event queue @ 80004268000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 81004268000. Starting simulation... -switching cpus -info: Entering event queue @ 81004272000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 82004272000. Starting simulation... -switching cpus -info: Entering event queue @ 82004273500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 83004273500. Starting simulation... -switching cpus -info: Entering event queue @ 83004274000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 84004274000. Starting simulation... -switching cpus -info: Entering event queue @ 84004278000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 85004278000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 86004278000. Starting simulation... -switching cpus -info: Entering event queue @ 86004278500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 87004278500. Starting simulation... -switching cpus -info: Entering event queue @ 87004288500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 88004288500. Starting simulation... -switching cpus -info: Entering event queue @ 88004289000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 89004289000. Starting simulation... -switching cpus -info: Entering event queue @ 89004289500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 90004289500. Starting simulation... -switching cpus -info: Entering event queue @ 90004299500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 91004299500. Starting simulation... -switching cpus -info: Entering event queue @ 91004300000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 92004300000. Starting simulation... -switching cpus -info: Entering event queue @ 92004300500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 93004300500. Starting simulation... -switching cpus -info: Entering event queue @ 93004304500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 94004304500. Starting simulation... -switching cpus -info: Entering event queue @ 94004305000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 95004305000. Starting simulation... -switching cpus -info: Entering event queue @ 95004305500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 96004305500. Starting simulation... -switching cpus -info: Entering event queue @ 96004309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 97004309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 98004309500. Starting simulation... -switching cpus -info: Entering event queue @ 98004317000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 99004317000. Starting simulation... -switching cpus -info: Entering event queue @ 99004389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 100004389500. Starting simulation... -switching cpus -info: Entering event queue @ 100004391000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 101004391000. Starting simulation... -switching cpus -info: Entering event queue @ 101004424000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 102004424000. Starting simulation... -switching cpus -info: Entering event queue @ 102004467500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 103004467500. Starting simulation... -switching cpus -info: Entering event queue @ 103004469000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 104004469000. Starting simulation... -switching cpus -info: Entering event queue @ 104004502000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 105004502000. Starting simulation... -switching cpus -info: Entering event queue @ 105004545500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 106004545500. Starting simulation... -switching cpus -info: Entering event queue @ 106004547000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 107004547000. Starting simulation... -switching cpus -info: Entering event queue @ 107004580000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 108004580000. Starting simulation... -switching cpus -info: Entering event queue @ 108004623500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 109004623500. Starting simulation... -switching cpus -info: Entering event queue @ 109004625000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 110004625000. Starting simulation... -switching cpus -info: Entering event queue @ 110004658000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 111004658000. Starting simulation... -switching cpus -info: Entering event queue @ 111004701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 112004701500. Starting simulation... -switching cpus -info: Entering event queue @ 112004703000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 113004703000. Starting simulation... -switching cpus -info: Entering event queue @ 113004736000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 114004736000. Starting simulation... -switching cpus -info: Entering event queue @ 114004779500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 115004779500. Starting simulation... -switching cpus -info: Entering event queue @ 115004781000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 116004781000. Starting simulation... -switching cpus -info: Entering event queue @ 116004814000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 117004814000. Starting simulation... -switching cpus -info: Entering event queue @ 117004857500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 118004857500. Starting simulation... -switching cpus -info: Entering event queue @ 118004859000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 119004859000. Starting simulation... -switching cpus -info: Entering event queue @ 119004892000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 120004892000. Starting simulation... -switching cpus -info: Entering event queue @ 120004935500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 121004935500. Starting simulation... -switching cpus -info: Entering event queue @ 121004937000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 122004937000. Starting simulation... -switching cpus -info: Entering event queue @ 122004970000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 123004970000. Starting simulation... -switching cpus -info: Entering event queue @ 123005013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 124005013500. Starting simulation... -switching cpus -info: Entering event queue @ 124005015000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 125005015000. Starting simulation... -switching cpus -info: Entering event queue @ 125005048000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 126005048000. Starting simulation... -switching cpus -info: Entering event queue @ 126005091500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 127005091500. Starting simulation... -switching cpus -info: Entering event queue @ 127005093000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 128005093000. Starting simulation... -switching cpus -info: Entering event queue @ 128005126000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 129005126000. Starting simulation... -switching cpus -info: Entering event queue @ 129005169500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 130005169500. Starting simulation... -switching cpus -info: Entering event queue @ 130005171000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 131005171000. Starting simulation... -switching cpus -info: Entering event queue @ 131005204000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 132005204000. Starting simulation... -switching cpus -info: Entering event queue @ 132005247500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 133005247500. Starting simulation... -switching cpus -info: Entering event queue @ 133005249000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 134005249000. Starting simulation... -switching cpus -info: Entering event queue @ 134005282000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 135005282000. Starting simulation... -switching cpus -info: Entering event queue @ 135005325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 136005325500. Starting simulation... -switching cpus -info: Entering event queue @ 136005327000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 137005327000. Starting simulation... -switching cpus -info: Entering event queue @ 137005360000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 138005360000. Starting simulation... -switching cpus -info: Entering event queue @ 138005403500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 139005403500. Starting simulation... -switching cpus -info: Entering event queue @ 139005405000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 140005405000. Starting simulation... -switching cpus -info: Entering event queue @ 140005438000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 141005438000. Starting simulation... -switching cpus -info: Entering event queue @ 141005481500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 142005481500. Starting simulation... -switching cpus -info: Entering event queue @ 142005483000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 143005483000. Starting simulation... -switching cpus -info: Entering event queue @ 143005516000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 144005516000. Starting simulation... -switching cpus -info: Entering event queue @ 144005559500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 145005559500. Starting simulation... -switching cpus -info: Entering event queue @ 145005561000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 146005561000. Starting simulation... -switching cpus -info: Entering event queue @ 146005594000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 147005594000. Starting simulation... -switching cpus -info: Entering event queue @ 147005637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 148005637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 149005637500. Starting simulation... -switching cpus -info: Entering event queue @ 149005645000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 150005645000. Starting simulation... -info: Entering event queue @ 150005938000. Starting simulation... -switching cpus -info: Entering event queue @ 150005945500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 151005945500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 152005945500. Starting simulation... -switching cpus -info: Entering event queue @ 152005953000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 153005953000. Starting simulation... -switching cpus -info: Entering event queue @ 155405582000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 156405582000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 157405582000. Starting simulation... -switching cpus -info: Entering event queue @ 157405589500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 158405589500. Starting simulation... -switching cpus -info: Entering event queue @ 159405533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 160405533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 161405533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 162405533500. Starting simulation... -switching cpus -info: Entering event queue @ 163405402000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 164405402000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 165405402000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 166405402000. Starting simulation... -switching cpus -info: Entering event queue @ 167405277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 168405277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 169405277500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 170405277500. Starting simulation... -switching cpus -info: Entering event queue @ 171405149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 172405149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 173405149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 174405149500. Starting simulation... -switching cpus -info: Entering event queue @ 175405018000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 176405018000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 177405018000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 178405018000. Starting simulation... -switching cpus -info: Entering event queue @ 179404893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 180404893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 181404893500. Starting simulation... -switching cpus -info: Entering event queue @ 181404901000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 182404901000. Starting simulation... -info: Entering event queue @ 183404700500. Starting simulation... -info: Entering event queue @ 183404701500. Starting simulation... -switching cpus -info: Entering event queue @ 183404706000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 184404706000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 185404706000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 186404706000. Starting simulation... -switching cpus -info: Entering event queue @ 187404637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 188404637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 189404637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 190404637500. Starting simulation... -switching cpus -info: Entering event queue @ 191404509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 192404509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 193404509500. Starting simulation... -switching cpus -info: Entering event queue @ 193404517000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 194404517000. Starting simulation... -info: Entering event queue @ 194405024000. Starting simulation... -switching cpus -info: Entering event queue @ 194405031500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 195405031500. Starting simulation... -switching cpus -info: Entering event queue @ 195405033000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 196405033000. Starting simulation... -switching cpus -info: Entering event queue @ 196405040500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 197405040500. Starting simulation... -switching cpus -info: Entering event queue @ 197405066000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 198405066000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 199405066000. Starting simulation... -info: Entering event queue @ 199405333000. Starting simulation... -switching cpus -info: Entering event queue @ 199405340500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 200405340500. Starting simulation... -info: Entering event queue @ 200405348500. Starting simulation... -switching cpus -info: Entering event queue @ 200405353000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 201405353000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 202405353000. Starting simulation... -switching cpus -info: Entering event queue @ 202405360500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 203405360500. Starting simulation... -info: Entering event queue @ 203405368000. Starting simulation... -switching cpus -info: Entering event queue @ 203405369000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 204405369000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 205405369000. Starting simulation... -info: Entering event queue @ 205405378500. Starting simulation... -switching cpus -info: Entering event queue @ 205405382000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 206405382000. Starting simulation... -info: Entering event queue @ 206405420000. Starting simulation... -switching cpus -info: Entering event queue @ 206405427500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 207405427500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 208405427500. Starting simulation... -switching cpus -info: Entering event queue @ 208405435000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 209405435000. Starting simulation... -switching cpus -info: Entering event queue @ 209405451000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 210405451000. Starting simulation... -switching cpus -info: Entering event queue @ 210405452000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 211405452000. Starting simulation... -switching cpus -info: Entering event queue @ 211405462500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 212405462500. Starting simulation... -info: Entering event queue @ 212405472000. Starting simulation... -switching cpus -info: Entering event queue @ 212405473000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 213405473000. Starting simulation... -switching cpus -info: Entering event queue @ 213405473500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 214405473500. Starting simulation... -info: Entering event queue @ 214405524000. Starting simulation... -switching cpus -info: Entering event queue @ 214405643750. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 215405643750. Starting simulation... -info: Entering event queue @ 215405728500. Starting simulation... -switching cpus -info: Entering event queue @ 215406099750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 216406099750. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 217406099750. Starting simulation... -switching cpus -info: Entering event queue @ 217406107250. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 218406107250. Starting simulation... -info: Entering event queue @ 218406116500. Starting simulation... -info: Entering event queue @ 218406122500. Starting simulation... -switching cpus -info: Entering event queue @ 218406127000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 219406127000. Starting simulation... -switching cpus -info: Entering event queue @ 219406127500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 220406127500. Starting simulation... -switching cpus -info: Entering event queue @ 220406135000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 221406135000. Starting simulation... -info: Entering event queue @ 221406151500. Starting simulation... -info: Entering event queue @ 221406161000. Starting simulation... -info: Entering event queue @ 221406165500. Starting simulation... -switching cpus -info: Entering event queue @ 221406166500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 222406166500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 223406166500. Starting simulation... -info: Entering event queue @ 223406175000. Starting simulation... -switching cpus -info: Entering event queue @ 223406178500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 224406178500. Starting simulation... -info: Entering event queue @ 224406203500. Starting simulation... -switching cpus -info: Entering event queue @ 224406209000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 225406209000. Starting simulation... -switching cpus -info: Entering event queue @ 225406210000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 226406210000. Starting simulation... -switching cpus -info: Entering event queue @ 226406217500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 227406217500. Starting simulation... -info: Entering event queue @ 227406280000. Starting simulation... -switching cpus -info: Entering event queue @ 227406429750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 228406429750. Starting simulation... -switching cpus -info: Entering event queue @ 228406430000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 229406430000. Starting simulation... -switching cpus -info: Entering event queue @ 229406437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 230406437500. Starting simulation... -info: Entering event queue @ 231403229000. Starting simulation... -info: Entering event queue @ 231403230000. Starting simulation... -switching cpus -info: Entering event queue @ 231403234500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 232403234500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 233403234500. Starting simulation... -switching cpus -info: Entering event queue @ 233403242000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 234403242000. Starting simulation... -switching cpus -info: Entering event queue @ 235403101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 236403101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 237403101500. Starting simulation... -switching cpus -info: Entering event queue @ 237403109000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 238403109000. Starting simulation... -switching cpus -info: Entering event queue @ 239402973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 240402973500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 241402973500. Starting simulation... -switching cpus -info: Entering event queue @ 241402981000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 242402981000. Starting simulation... -info: Entering event queue @ 243402845000. Starting simulation... -info: Entering event queue @ 243402846000. Starting simulation... -switching cpus -info: Entering event queue @ 243402850500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 244402850500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 245402850500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 246402850500. Starting simulation... -switching cpus -info: Entering event queue @ 247402717500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 248402717500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 249402717500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 250402717500. Starting simulation... -switching cpus -info: Entering event queue @ 251402589500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 252402589500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 253402589500. Starting simulation... -switching cpus -info: Entering event queue @ 253402597000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 254402597000. Starting simulation... -switching cpus -info: Entering event queue @ 255402461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 256402461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 257402461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 258402461500. Starting simulation... -switching cpus -info: Entering event queue @ 259402333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 260402333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 261402333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 262402333500. Starting simulation... -switching cpus -info: Entering event queue @ 263402205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 264402205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 265402205500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 266402205500. Starting simulation... -switching cpus -info: Entering event queue @ 267402077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 268402077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 269402077500. Starting simulation... -switching cpus -info: Entering event queue @ 269402085000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 270402085000. Starting simulation... -switching cpus -info: Entering event queue @ 271401949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 272401949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 273401949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 274401949500. Starting simulation... -switching cpus -info: Entering event queue @ 275401821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 276401821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 277401821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 278401821500. Starting simulation... -switching cpus -info: Entering event queue @ 279401693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 280401693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 281401693500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 282401693500. Starting simulation... -switching cpus -info: Entering event queue @ 283401565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 284401565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 285401565500. Starting simulation... -switching cpus -info: Entering event queue @ 285401573000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 286401573000. Starting simulation... -switching cpus -info: Entering event queue @ 287401437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 288401437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 289401437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 290401437500. Starting simulation... -switching cpus -info: Entering event queue @ 291401309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 292401309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 293401309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 294401309500. Starting simulation... -switching cpus -info: Entering event queue @ 295401181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 296401181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 297401181500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 298401181500. Starting simulation... -switching cpus -info: Entering event queue @ 299401053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 300401053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 301401053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 302401053500. Starting simulation... -switching cpus -info: Entering event queue @ 303400925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 304400925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 305400925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 306400925500. Starting simulation... -switching cpus -info: Entering event queue @ 307400797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 308400797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 309400797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 310400797500. Starting simulation... -switching cpus -info: Entering event queue @ 311400669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 312400669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 313400669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 314400669500. Starting simulation... -switching cpus -info: Entering event queue @ 315400541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 316400541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 317400541500. Starting simulation... -switching cpus -info: Entering event queue @ 317400549000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 318400549000. Starting simulation... -switching cpus -info: Entering event queue @ 319400413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 320400413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 321400413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 322400413500. Starting simulation... -switching cpus -info: Entering event queue @ 323400285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 324400285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 325400285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 326400285500. Starting simulation... -switching cpus -info: Entering event queue @ 327400157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 328400157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 329400157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 330400157500. Starting simulation... -switching cpus -info: Entering event queue @ 331400029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 332400029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 333400029500. Starting simulation... -switching cpus -info: Entering event queue @ 333400037000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 334400037000. Starting simulation... -switching cpus -info: Entering event queue @ 335399901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 336399901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 337399901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 338399901500. Starting simulation... -switching cpus -info: Entering event queue @ 339399773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 340399773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 341399773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 342399773500. Starting simulation... -switching cpus -info: Entering event queue @ 343399645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 344399645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 345399645500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 346399645500. Starting simulation... -switching cpus -info: Entering event queue @ 347399517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 348399517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 349399517500. Starting simulation... -switching cpus -info: Entering event queue @ 349399525000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 350399525000. Starting simulation... -switching cpus -info: Entering event queue @ 351399389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 352399389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 353399389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 354399389500. Starting simulation... -switching cpus -info: Entering event queue @ 355399261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 356399261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 357399261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 358399261500. Starting simulation... -switching cpus -info: Entering event queue @ 359399133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 360399133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 361399133500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 362399133500. Starting simulation... -switching cpus -info: Entering event queue @ 363399005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 364399005500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 365399005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 366399005500. Starting simulation... -switching cpus -info: Entering event queue @ 367398877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 368398877500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 369398877500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 370398877500. Starting simulation... -switching cpus -info: Entering event queue @ 371398749500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 372398749500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 373398749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 374398749500. Starting simulation... -switching cpus -info: Entering event queue @ 375398621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 376398621500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 377398621500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 378398621500. Starting simulation... -switching cpus -info: Entering event queue @ 379398493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 380398493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 381398493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 382398493500. Starting simulation... -switching cpus -info: Entering event queue @ 383398365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 384398365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 385398365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 386398365500. Starting simulation... -switching cpus -info: Entering event queue @ 387398237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 388398237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 389398237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 390398237500. Starting simulation... -switching cpus -info: Entering event queue @ 391398109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 392398109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 393398109500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 394398109500. Starting simulation... -switching cpus -info: Entering event queue @ 395397981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 396397981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 397397981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 398397981500. Starting simulation... -switching cpus -info: Entering event queue @ 399397853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 400397853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 401397853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 402397853500. Starting simulation... -switching cpus -info: Entering event queue @ 403397725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 404397725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 405397725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 406397725500. Starting simulation... -switching cpus -info: Entering event queue @ 407397597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 408397597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 409397597500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 410397597500. Starting simulation... -switching cpus -info: Entering event queue @ 411397469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 412397469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 413397469500. Starting simulation... -switching cpus -info: Entering event queue @ 413397477000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 414397477000. Starting simulation... -switching cpus -info: Entering event queue @ 415397341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 416397341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 417397341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 418397341500. Starting simulation... -switching cpus -info: Entering event queue @ 419397213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 420397213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 421397213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 422397213500. Starting simulation... -switching cpus -info: Entering event queue @ 423397085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 424397085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 425397085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 426397085500. Starting simulation... -switching cpus -info: Entering event queue @ 427396957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 428396957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 429396957500. Starting simulation... -switching cpus -info: Entering event queue @ 429396965000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 430396965000. Starting simulation... -switching cpus -info: Entering event queue @ 431396829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 432396829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 433396829500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 434396829500. Starting simulation... -switching cpus -info: Entering event queue @ 435396701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 436396701500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 437396701500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 438396701500. Starting simulation... -switching cpus -info: Entering event queue @ 439396573500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 440396573500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 441396573500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 442396573500. Starting simulation... -switching cpus -info: Entering event queue @ 443396445500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 444396445500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 445396445500. Starting simulation... -switching cpus -info: Entering event queue @ 445396453000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 446396453000. Starting simulation... -switching cpus -info: Entering event queue @ 447396317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 448396317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 449396317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 450396317500. Starting simulation... -switching cpus -info: Entering event queue @ 451396189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 452396189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 453396189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 454396189500. Starting simulation... -switching cpus -info: Entering event queue @ 455396061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 456396061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 457396061500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 458396061500. Starting simulation... -switching cpus -info: Entering event queue @ 459395933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 460395933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 461395933500. Starting simulation... -switching cpus -info: Entering event queue @ 461395941000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 462395941000. Starting simulation... -switching cpus -info: Entering event queue @ 463395805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 464395805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 465395805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 466395805500. Starting simulation... -switching cpus -info: Entering event queue @ 467395677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 468395677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 469395677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 470395677500. Starting simulation... -switching cpus -info: Entering event queue @ 471395549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 472395549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 473395549500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 474395549500. Starting simulation... -switching cpus -info: Entering event queue @ 475395421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 476395421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 477395421500. Starting simulation... -switching cpus -info: Entering event queue @ 477395429000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 478395429000. Starting simulation... -switching cpus -info: Entering event queue @ 479395293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 480395293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 481395293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 482395293500. Starting simulation... -switching cpus -info: Entering event queue @ 483395165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 484395165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 485395165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 486395165500. Starting simulation... -switching cpus -info: Entering event queue @ 487395037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 488395037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 489395037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 490395037500. Starting simulation... -switching cpus -info: Entering event queue @ 491394909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 492394909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 493394909500. Starting simulation... -switching cpus -info: Entering event queue @ 493394917000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 494394917000. Starting simulation... -switching cpus -info: Entering event queue @ 495394781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 496394781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 497394781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 498394781500. Starting simulation... -switching cpus -info: Entering event queue @ 499394653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 500394653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 501394653500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 502394653500. Starting simulation... -switching cpus -info: Entering event queue @ 503394525500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 504394525500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 505394525500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 506394525500. Starting simulation... -switching cpus -info: Entering event queue @ 507394397500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 508394397500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 509394397500. Starting simulation... -switching cpus -info: Entering event queue @ 509394405000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 510394405000. Starting simulation... -switching cpus -info: Entering event queue @ 511394269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 512394269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 513394269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 514394269500. Starting simulation... -switching cpus -info: Entering event queue @ 515394141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 516394141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 517394141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 518394141500. Starting simulation... -switching cpus -info: Entering event queue @ 519394013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 520394013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 521394013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 522394013500. Starting simulation... -switching cpus -info: Entering event queue @ 523393885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 524393885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 525393885500. Starting simulation... -switching cpus -info: Entering event queue @ 525393893000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 526393893000. Starting simulation... -switching cpus -info: Entering event queue @ 527393757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 528393757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 529393757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 530393757500. Starting simulation... -switching cpus -info: Entering event queue @ 531393629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 532393629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 533393629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 534393629500. Starting simulation... -switching cpus -info: Entering event queue @ 535393501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 536393501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 537393501500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 538393501500. Starting simulation... -switching cpus -info: Entering event queue @ 539393373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 540393373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 541393373500. Starting simulation... -switching cpus -info: Entering event queue @ 541393381000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 542393381000. Starting simulation... -switching cpus -info: Entering event queue @ 543393245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 544393245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 545393245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 546393245500. Starting simulation... -switching cpus -info: Entering event queue @ 547393117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 548393117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 549393117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 550393117500. Starting simulation... -switching cpus -info: Entering event queue @ 551392989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 552392989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 553392989500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 554392989500. Starting simulation... -switching cpus -info: Entering event queue @ 555392861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 556392861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 557392861500. Starting simulation... -switching cpus -info: Entering event queue @ 557392869000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 558392869000. Starting simulation... -switching cpus -info: Entering event queue @ 559392733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 560392733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 561392733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 562392733500. Starting simulation... -switching cpus -info: Entering event queue @ 563392605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 564392605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 565392605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 566392605500. Starting simulation... -switching cpus -info: Entering event queue @ 567392477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 568392477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 569392477500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 570392477500. Starting simulation... -switching cpus -info: Entering event queue @ 571392349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 572392349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 573392349500. Starting simulation... -switching cpus -info: Entering event queue @ 573392357000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 574392357000. Starting simulation... -switching cpus -info: Entering event queue @ 575392221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 576392221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 577392221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 578392221500. Starting simulation... -switching cpus -info: Entering event queue @ 579392093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 580392093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 581392093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 582392093500. Starting simulation... -switching cpus -info: Entering event queue @ 583391965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 584391965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 585391965500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 586391965500. Starting simulation... -switching cpus -info: Entering event queue @ 587391837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 588391837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 589391837500. Starting simulation... -switching cpus -info: Entering event queue @ 589391845000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 590391845000. Starting simulation... -switching cpus -info: Entering event queue @ 591391709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 592391709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 593391709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 594391709500. Starting simulation... -switching cpus -info: Entering event queue @ 595391581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 596391581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 597391581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 598391581500. Starting simulation... -switching cpus -info: Entering event queue @ 599391453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 600391453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 601391453500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 602391453500. Starting simulation... -switching cpus -info: Entering event queue @ 603391325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 604391325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 605391325500. Starting simulation... -switching cpus -info: Entering event queue @ 605391333000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 606391333000. Starting simulation... -switching cpus -info: Entering event queue @ 607391197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 608391197500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 609391197500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 610391197500. Starting simulation... -switching cpus -info: Entering event queue @ 611391069500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 612391069500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 613391069500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 614391069500. Starting simulation... -switching cpus -info: Entering event queue @ 615390941500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 616390941500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 617390941500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 618390941500. Starting simulation... -switching cpus -info: Entering event queue @ 619390813500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 620390813500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 621390813500. Starting simulation... -switching cpus -info: Entering event queue @ 621390821000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 622390821000. Starting simulation... -switching cpus -info: Entering event queue @ 623390685500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 624390685500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 625390685500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 626390685500. Starting simulation... -switching cpus -info: Entering event queue @ 627390557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 628390557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 629390557500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 630390557500. Starting simulation... -switching cpus -info: Entering event queue @ 631390429500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 632390429500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 633390429500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 634390429500. Starting simulation... -switching cpus -info: Entering event queue @ 635390301500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 636390301500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 637390301500. Starting simulation... -switching cpus -info: Entering event queue @ 637390309000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 638390309000. Starting simulation... -switching cpus -info: Entering event queue @ 639390173500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 640390173500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 641390173500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 642390173500. Starting simulation... -switching cpus -info: Entering event queue @ 643390045500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 644390045500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 645390045500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 646390045500. Starting simulation... -switching cpus -info: Entering event queue @ 647389917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 648389917500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 649389917500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 650389917500. Starting simulation... -switching cpus -info: Entering event queue @ 651389789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 652389789500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 653389789500. Starting simulation... -switching cpus -info: Entering event queue @ 653389797000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 654389797000. Starting simulation... -switching cpus -info: Entering event queue @ 655389661500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 656389661500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 657389661500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 658389661500. Starting simulation... -switching cpus -info: Entering event queue @ 659389533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 660389533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 661389533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 662389533500. Starting simulation... -switching cpus -info: Entering event queue @ 663389405500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 664389405500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 665389405500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 666389405500. Starting simulation... -switching cpus -info: Entering event queue @ 667389277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 668389277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 669389277500. Starting simulation... -switching cpus -info: Entering event queue @ 669389285000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 670389285000. Starting simulation... -switching cpus -info: Entering event queue @ 671389149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 672389149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 673389149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 674389149500. Starting simulation... -switching cpus -info: Entering event queue @ 675389021500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 676389021500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 677389021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 678389021500. Starting simulation... -switching cpus -info: Entering event queue @ 679388893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 680388893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 681388893500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 682388893500. Starting simulation... -switching cpus -info: Entering event queue @ 683388765500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 684388765500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 685388765500. Starting simulation... -switching cpus -info: Entering event queue @ 685388773000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 686388773000. Starting simulation... -switching cpus -info: Entering event queue @ 687388637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 688388637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 689388637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 690388637500. Starting simulation... -switching cpus -info: Entering event queue @ 691388509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 692388509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 693388509500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 694388509500. Starting simulation... -switching cpus -info: Entering event queue @ 695388381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 696388381500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 697388381500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 698388381500. Starting simulation... -switching cpus -info: Entering event queue @ 699388253500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 700388253500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 701388253500. Starting simulation... -switching cpus -info: Entering event queue @ 701388261000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 702388261000. Starting simulation... -switching cpus -info: Entering event queue @ 703388125500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 704388125500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 705388125500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 706388125500. Starting simulation... -switching cpus -info: Entering event queue @ 707387997500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 708387997500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 709387997500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 710387997500. Starting simulation... -switching cpus -info: Entering event queue @ 711387869500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 712387869500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 713387869500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 714387869500. Starting simulation... -switching cpus -info: Entering event queue @ 715387741500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 716387741500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 717387741500. Starting simulation... -switching cpus -info: Entering event queue @ 717387749000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 718387749000. Starting simulation... -switching cpus -info: Entering event queue @ 719387613500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 720387613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 721387613500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 722387613500. Starting simulation... -switching cpus -info: Entering event queue @ 723387485500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 724387485500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 725387485500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 726387485500. Starting simulation... -switching cpus -info: Entering event queue @ 727387357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 728387357500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 729387357500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 730387357500. Starting simulation... -switching cpus -info: Entering event queue @ 731387229500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 732387229500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 733387229500. Starting simulation... -switching cpus -info: Entering event queue @ 733387237000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 734387237000. Starting simulation... -switching cpus -info: Entering event queue @ 735387101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 736387101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 737387101500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 738387101500. Starting simulation... -switching cpus -info: Entering event queue @ 739386973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 740386973500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 741386973500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 742386973500. Starting simulation... -switching cpus -info: Entering event queue @ 743386845500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 744386845500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 745386845500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 746386845500. Starting simulation... -switching cpus -info: Entering event queue @ 747386717500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 748386717500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 749386717500. Starting simulation... -switching cpus -info: Entering event queue @ 749386725000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 750386725000. Starting simulation... -switching cpus -info: Entering event queue @ 751386589500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 752386589500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 753386589500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 754386589500. Starting simulation... -switching cpus -info: Entering event queue @ 755386461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 756386461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 757386461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 758386461500. Starting simulation... -switching cpus -info: Entering event queue @ 759386333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 760386333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 761386333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 762386333500. Starting simulation... -switching cpus -info: Entering event queue @ 763386205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 764386205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 765386205500. Starting simulation... -switching cpus -info: Entering event queue @ 765386213000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 766386213000. Starting simulation... -switching cpus -info: Entering event queue @ 767386077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 768386077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 769386077500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 770386077500. Starting simulation... -switching cpus -info: Entering event queue @ 771385949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 772385949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 773385949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 774385949500. Starting simulation... -switching cpus -info: Entering event queue @ 775385821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 776385821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 777385821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 778385821500. Starting simulation... -switching cpus -info: Entering event queue @ 779385693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 780385693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 781385693500. Starting simulation... -switching cpus -info: Entering event queue @ 781385701000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 782385701000. Starting simulation... -switching cpus -info: Entering event queue @ 783385565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 784385565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 785385565500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 786385565500. Starting simulation... -switching cpus -info: Entering event queue @ 787385437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 788385437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 789385437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 790385437500. Starting simulation... -switching cpus -info: Entering event queue @ 791385309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 792385309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 793385309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 794385309500. Starting simulation... -switching cpus -info: Entering event queue @ 795385181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 796385181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 797385181500. Starting simulation... -switching cpus -info: Entering event queue @ 797385189000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 798385189000. Starting simulation... -switching cpus -info: Entering event queue @ 799385053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 800385053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 801385053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 802385053500. Starting simulation... -switching cpus -info: Entering event queue @ 803384925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 804384925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 805384925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 806384925500. Starting simulation... -switching cpus -info: Entering event queue @ 807384797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 808384797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 809384797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 810384797500. Starting simulation... -switching cpus -info: Entering event queue @ 811384669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 812384669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 813384669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 814384669500. Starting simulation... -switching cpus -info: Entering event queue @ 815384541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 816384541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 817384541500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 818384541500. Starting simulation... -switching cpus -info: Entering event queue @ 819384413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 820384413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 821384413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 822384413500. Starting simulation... -switching cpus -info: Entering event queue @ 823384285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 824384285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 825384285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 826384285500. Starting simulation... -switching cpus -info: Entering event queue @ 827384157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 828384157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 829384157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 830384157500. Starting simulation... -switching cpus -info: Entering event queue @ 831384029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 832384029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 833384029500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 834384029500. Starting simulation... -switching cpus -info: Entering event queue @ 835383901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 836383901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 837383901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 838383901500. Starting simulation... -switching cpus -info: Entering event queue @ 839383773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 840383773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 841383773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 842383773500. Starting simulation... -switching cpus -info: Entering event queue @ 843383645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 844383645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 845383645500. Starting simulation... -switching cpus -info: Entering event queue @ 845383653000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 846383653000. Starting simulation... -switching cpus -info: Entering event queue @ 847383517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 848383517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 849383517500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 850383517500. Starting simulation... -switching cpus -info: Entering event queue @ 851383389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 852383389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 853383389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 854383389500. Starting simulation... -switching cpus -info: Entering event queue @ 855383261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 856383261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 857383261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 858383261500. Starting simulation... -switching cpus -info: Entering event queue @ 859383133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 860383133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 861383133500. Starting simulation... -switching cpus -info: Entering event queue @ 861383141000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 862383141000. Starting simulation... -switching cpus -info: Entering event queue @ 863383005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 864383005500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 865383005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 866383005500. Starting simulation... -switching cpus -info: Entering event queue @ 867382877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 868382877500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 869382877500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 870382877500. Starting simulation... -switching cpus -info: Entering event queue @ 871382749500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 872382749500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 873382749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 874382749500. Starting simulation... -switching cpus -info: Entering event queue @ 875382621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 876382621500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 877382621500. Starting simulation... -switching cpus -info: Entering event queue @ 877382629000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 878382629000. Starting simulation... -switching cpus -info: Entering event queue @ 879382493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 880382493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 881382493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 882382493500. Starting simulation... -switching cpus -info: Entering event queue @ 883382365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 884382365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 885382365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 886382365500. Starting simulation... -switching cpus -info: Entering event queue @ 887382237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 888382237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 889382237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 890382237500. Starting simulation... -switching cpus -info: Entering event queue @ 891382109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 892382109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 893382109500. Starting simulation... -switching cpus -info: Entering event queue @ 893382117000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 894382117000. Starting simulation... -switching cpus -info: Entering event queue @ 895381981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 896381981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 897381981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 898381981500. Starting simulation... -switching cpus -info: Entering event queue @ 899381853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 900381853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 901381853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 902381853500. Starting simulation... -switching cpus -info: Entering event queue @ 903381725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 904381725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 905381725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 906381725500. Starting simulation... -switching cpus -info: Entering event queue @ 907381597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 908381597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 909381597500. Starting simulation... -switching cpus -info: Entering event queue @ 909381605000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 910381605000. Starting simulation... -switching cpus -info: Entering event queue @ 911381469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 912381469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 913381469500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 914381469500. Starting simulation... -switching cpus -info: Entering event queue @ 915381341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 916381341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 917381341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 918381341500. Starting simulation... -switching cpus -info: Entering event queue @ 919381213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 920381213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 921381213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 922381213500. Starting simulation... -switching cpus -info: Entering event queue @ 923381085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 924381085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 925381085500. Starting simulation... -switching cpus -info: Entering event queue @ 925381093000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 926381093000. Starting simulation... -switching cpus -info: Entering event queue @ 927380957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 928380957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 929380957500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 930380957500. Starting simulation... -switching cpus -info: Entering event queue @ 931380829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 932380829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 933380829500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 934380829500. Starting simulation... -switching cpus -info: Entering event queue @ 935380701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 936380701500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 937380701500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 938380701500. Starting simulation... -switching cpus -info: Entering event queue @ 939380573500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 940380573500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 941380573500. Starting simulation... -switching cpus -info: Entering event queue @ 941380581000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 942380581000. Starting simulation... -switching cpus -info: Entering event queue @ 943380445500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 944380445500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 945380445500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 946380445500. Starting simulation... -switching cpus -info: Entering event queue @ 947380317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 948380317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 949380317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 950380317500. Starting simulation... -switching cpus -info: Entering event queue @ 951380189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 952380189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 953380189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 954380189500. Starting simulation... -switching cpus -info: Entering event queue @ 955380061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 956380061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 957380061500. Starting simulation... -switching cpus -info: Entering event queue @ 957380069000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 958380069000. Starting simulation... -switching cpus -info: Entering event queue @ 959379933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 960379933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 961379933500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 962379933500. Starting simulation... -switching cpus -info: Entering event queue @ 963379805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 964379805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 965379805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 966379805500. Starting simulation... -switching cpus -info: Entering event queue @ 967379677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 968379677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 969379677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 970379677500. Starting simulation... -switching cpus -info: Entering event queue @ 971379549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 972379549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 973379549500. Starting simulation... -switching cpus -info: Entering event queue @ 973379557000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 974379557000. Starting simulation... -switching cpus -info: Entering event queue @ 975379421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 976379421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 977379421500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 978379421500. Starting simulation... -switching cpus -info: Entering event queue @ 979379293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 980379293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 981379293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 982379293500. Starting simulation... -switching cpus -info: Entering event queue @ 983379165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 984379165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 985379165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 986379165500. Starting simulation... -switching cpus -info: Entering event queue @ 987379037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 988379037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 989379037500. Starting simulation... -switching cpus -info: Entering event queue @ 989379045000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 990379045000. Starting simulation... -switching cpus -info: Entering event queue @ 991378909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 992378909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 993378909500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 994378909500. Starting simulation... -switching cpus -info: Entering event queue @ 995378781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 996378781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 997378781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 998378781500. Starting simulation... -switching cpus -info: Entering event queue @ 999378653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1000378653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1001378653500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1002378653500. Starting simulation... -switching cpus -info: Entering event queue @ 1003378525500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1004378525500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1005378525500. Starting simulation... -switching cpus -info: Entering event queue @ 1005378533000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1006378533000. Starting simulation... -switching cpus -info: Entering event queue @ 1007378397500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1008378397500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1009378397500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1010378397500. Starting simulation... -switching cpus -info: Entering event queue @ 1011378269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1012378269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1013378269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1014378269500. Starting simulation... -switching cpus -info: Entering event queue @ 1015378141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1016378141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1017378141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1018378141500. Starting simulation... -switching cpus -info: Entering event queue @ 1019378013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1020378013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1021378013500. Starting simulation... -switching cpus -info: Entering event queue @ 1021378021000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1022378021000. Starting simulation... -switching cpus -info: Entering event queue @ 1023377885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1024377885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1025377885500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1026377885500. Starting simulation... -switching cpus -info: Entering event queue @ 1027377757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1028377757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1029377757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1030377757500. Starting simulation... -switching cpus -info: Entering event queue @ 1031377629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1032377629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1033377629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1034377629500. Starting simulation... -switching cpus -info: Entering event queue @ 1035377501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1036377501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1037377501500. Starting simulation... -switching cpus -info: Entering event queue @ 1037377509000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1038377509000. Starting simulation... -switching cpus -info: Entering event queue @ 1039377373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1040377373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1041377373500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1042377373500. Starting simulation... -switching cpus -info: Entering event queue @ 1043377245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1044377245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1045377245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1046377245500. Starting simulation... -switching cpus -info: Entering event queue @ 1047377117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1048377117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1049377117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1050377117500. Starting simulation... -switching cpus -info: Entering event queue @ 1051376989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1052376989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1053376989500. Starting simulation... -switching cpus -info: Entering event queue @ 1053376997000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1054376997000. Starting simulation... -switching cpus -info: Entering event queue @ 1055376861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1056376861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1057376861500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1058376861500. Starting simulation... -switching cpus -info: Entering event queue @ 1059376733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1060376733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1061376733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1062376733500. Starting simulation... -switching cpus -info: Entering event queue @ 1063376605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1064376605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1065376605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1066376605500. Starting simulation... -switching cpus -info: Entering event queue @ 1067376477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1068376477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1069376477500. Starting simulation... -switching cpus -info: Entering event queue @ 1069376485000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1070376485000. Starting simulation... -switching cpus -info: Entering event queue @ 1071376349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1072376349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1073376349500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1074376349500. Starting simulation... -switching cpus -info: Entering event queue @ 1075376221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1076376221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1077376221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1078376221500. Starting simulation... -switching cpus -info: Entering event queue @ 1079376093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1080376093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1081376093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1082376093500. Starting simulation... -switching cpus -info: Entering event queue @ 1083375965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1084375965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1085375965500. Starting simulation... -switching cpus -info: Entering event queue @ 1085375973000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1086375973000. Starting simulation... -switching cpus -info: Entering event queue @ 1087375837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1088375837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1089375837500. Starting simulation... -switching cpus -info: Entering event queue @ 1089375845000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1090375845000. Starting simulation... -switching cpus -info: Entering event queue @ 1091375709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1092375709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1093375709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1094375709500. Starting simulation... -switching cpus -info: Entering event queue @ 1095375581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1096375581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1097375581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1098375581500. Starting simulation... -switching cpus -info: Entering event queue @ 1099375453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1100375453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1101375453500. Starting simulation... -switching cpus -info: Entering event queue @ 1101375461000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1102375461000. Starting simulation... -switching cpus -info: Entering event queue @ 1103375325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1104375325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1105375325500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1106375325500. Starting simulation... -switching cpus -info: Entering event queue @ 1107375197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1108375197500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1109375197500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1110375197500. Starting simulation... -switching cpus -info: Entering event queue @ 1111375069500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1112375069500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1113375069500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1114375069500. Starting simulation... -switching cpus -info: Entering event queue @ 1115374941500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1116374941500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1117374941500. Starting simulation... -switching cpus -info: Entering event queue @ 1117374949000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1118374949000. Starting simulation... -switching cpus -info: Entering event queue @ 1119374813500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1120374813500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1121374813500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1122374813500. Starting simulation... -switching cpus -info: Entering event queue @ 1123374685500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1124374685500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1125374685500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1126374685500. Starting simulation... -switching cpus -info: Entering event queue @ 1127374557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1128374557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1129374557500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1130374557500. Starting simulation... -switching cpus -info: Entering event queue @ 1131374429500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1132374429500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1133374429500. Starting simulation... -switching cpus -info: Entering event queue @ 1133374437000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1134374437000. Starting simulation... -switching cpus -info: Entering event queue @ 1135374301500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1136374301500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1137374301500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1138374301500. Starting simulation... -switching cpus -info: Entering event queue @ 1139374173500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1140374173500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1141374173500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1142374173500. Starting simulation... -switching cpus -info: Entering event queue @ 1143374045500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1144374045500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1145374045500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1146374045500. Starting simulation... -switching cpus -info: Entering event queue @ 1147373917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1148373917500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1149373917500. Starting simulation... -switching cpus -info: Entering event queue @ 1149373925000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1150373925000. Starting simulation... -switching cpus -info: Entering event queue @ 1151373789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1152373789500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1153373789500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1154373789500. Starting simulation... -switching cpus -info: Entering event queue @ 1155373661500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1156373661500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1157373661500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1158373661500. Starting simulation... -switching cpus -info: Entering event queue @ 1159373533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1160373533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1161373533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1162373533500. Starting simulation... -switching cpus -info: Entering event queue @ 1163373405500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1164373405500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1165373405500. Starting simulation... -switching cpus -info: Entering event queue @ 1165373413000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1166373413000. Starting simulation... -switching cpus -info: Entering event queue @ 1167373277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1168373277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1169373277500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1170373277500. Starting simulation... -switching cpus -info: Entering event queue @ 1171373149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1172373149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1173373149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1174373149500. Starting simulation... -switching cpus -info: Entering event queue @ 1175373021500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1176373021500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1177373021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1178373021500. Starting simulation... -switching cpus -info: Entering event queue @ 1179372893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1180372893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1181372893500. Starting simulation... -switching cpus -info: Entering event queue @ 1181372901000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1182372901000. Starting simulation... -switching cpus -info: Entering event queue @ 1183372765500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1184372765500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1185372765500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1186372765500. Starting simulation... -switching cpus -info: Entering event queue @ 1187372637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1188372637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1189372637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1190372637500. Starting simulation... -switching cpus -info: Entering event queue @ 1191372509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1192372509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1193372509500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1194372509500. Starting simulation... -switching cpus -info: Entering event queue @ 1195372381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1196372381500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1197372381500. Starting simulation... -switching cpus -info: Entering event queue @ 1197372389000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1198372389000. Starting simulation... -switching cpus -info: Entering event queue @ 1199372253500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1200372253500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1201372253500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1202372253500. Starting simulation... -switching cpus -info: Entering event queue @ 1203372125500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1204372125500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1205372125500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1206372125500. Starting simulation... -switching cpus -info: Entering event queue @ 1207371997500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1208371997500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1209371997500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1210371997500. Starting simulation... -switching cpus -info: Entering event queue @ 1211371869500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1212371869500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1213371869500. Starting simulation... -switching cpus -info: Entering event queue @ 1213371877000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1214371877000. Starting simulation... -switching cpus -info: Entering event queue @ 1215371741500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1216371741500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1217371741500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1218371741500. Starting simulation... -switching cpus -info: Entering event queue @ 1219371613500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1220371613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1221371613500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1222371613500. Starting simulation... -switching cpus -info: Entering event queue @ 1223371485500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1224371485500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1225371485500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1226371485500. Starting simulation... -switching cpus -info: Entering event queue @ 1227371357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1228371357500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1229371357500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1230371357500. Starting simulation... -switching cpus -info: Entering event queue @ 1231371229500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1232371229500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1233371229500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1234371229500. Starting simulation... -switching cpus -info: Entering event queue @ 1235371101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1236371101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1237371101500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1238371101500. Starting simulation... -switching cpus -info: Entering event queue @ 1239370973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1240370973500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1241370973500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1242370973500. Starting simulation... -switching cpus -info: Entering event queue @ 1243370845500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1244370845500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1245370845500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1246370845500. Starting simulation... -switching cpus -info: Entering event queue @ 1247370717500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1248370717500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1249370717500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1250370717500. Starting simulation... -switching cpus -info: Entering event queue @ 1251370589500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1252370589500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1253370589500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1254370589500. Starting simulation... -switching cpus -info: Entering event queue @ 1255370461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1256370461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1257370461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1258370461500. Starting simulation... -switching cpus -info: Entering event queue @ 1259370333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1260370333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1261370333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1262370333500. Starting simulation... -switching cpus -info: Entering event queue @ 1263370205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1264370205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1265370205500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1266370205500. Starting simulation... -switching cpus -info: Entering event queue @ 1267370077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1268370077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1269370077500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1270370077500. Starting simulation... -switching cpus -info: Entering event queue @ 1271369949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1272369949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1273369949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1274369949500. Starting simulation... -switching cpus -info: Entering event queue @ 1275369821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1276369821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1277369821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1278369821500. Starting simulation... -switching cpus -info: Entering event queue @ 1279369693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1280369693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1281369693500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1282369693500. Starting simulation... -switching cpus -info: Entering event queue @ 1283369565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1284369565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1285369565500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1286369565500. Starting simulation... -switching cpus -info: Entering event queue @ 1287369437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1288369437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1289369437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1290369437500. Starting simulation... -switching cpus -info: Entering event queue @ 1291369309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1292369309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1293369309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1294369309500. Starting simulation... -switching cpus -info: Entering event queue @ 1295369181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1296369181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1297369181500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1298369181500. Starting simulation... -switching cpus -info: Entering event queue @ 1299369053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1300369053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1301369053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1302369053500. Starting simulation... -switching cpus -info: Entering event queue @ 1303368925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1304368925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1305368925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1306368925500. Starting simulation... -switching cpus -info: Entering event queue @ 1307368797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1308368797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1309368797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1310368797500. Starting simulation... -switching cpus -info: Entering event queue @ 1311368669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1312368669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1313368669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1314368669500. Starting simulation... -switching cpus -info: Entering event queue @ 1315368541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1316368541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1317368541500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1318368541500. Starting simulation... -switching cpus -info: Entering event queue @ 1319368413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1320368413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1321368413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1322368413500. Starting simulation... -switching cpus -info: Entering event queue @ 1323368285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1324368285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1325368285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1326368285500. Starting simulation... -switching cpus -info: Entering event queue @ 1327368157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1328368157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1329368157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1330368157500. Starting simulation... -switching cpus -info: Entering event queue @ 1331368029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1332368029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1333368029500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1334368029500. Starting simulation... -switching cpus -info: Entering event queue @ 1335367901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1336367901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1337367901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1338367901500. Starting simulation... -switching cpus -info: Entering event queue @ 1339367773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1340367773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1341367773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1342367773500. Starting simulation... -switching cpus -info: Entering event queue @ 1343367645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1344367645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1345367645500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1346367645500. Starting simulation... -switching cpus -info: Entering event queue @ 1347367517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1348367517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1349367517500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1350367517500. Starting simulation... -switching cpus -info: Entering event queue @ 1351367389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1352367389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1353367389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1354367389500. Starting simulation... -switching cpus -info: Entering event queue @ 1355367261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1356367261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1357367261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1358367261500. Starting simulation... -switching cpus -info: Entering event queue @ 1359367133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1360367133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1361367133500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1362367133500. Starting simulation... -switching cpus -info: Entering event queue @ 1363367005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1364367005500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1365367005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1366367005500. Starting simulation... -switching cpus -info: Entering event queue @ 1367366877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1368366877500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1369366877500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1370366877500. Starting simulation... -switching cpus -info: Entering event queue @ 1371366749500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1372366749500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1373366749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1374366749500. Starting simulation... -switching cpus -info: Entering event queue @ 1375366621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1376366621500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1377366621500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1378366621500. Starting simulation... -switching cpus -info: Entering event queue @ 1379366493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1380366493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1381366493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1382366493500. Starting simulation... -switching cpus -info: Entering event queue @ 1383366365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1384366365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1385366365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1386366365500. Starting simulation... -switching cpus -info: Entering event queue @ 1387366237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1388366237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1389366237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1390366237500. Starting simulation... -switching cpus -info: Entering event queue @ 1391366109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1392366109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1393366109500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1394366109500. Starting simulation... -switching cpus -info: Entering event queue @ 1395365981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1396365981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1397365981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1398365981500. Starting simulation... -switching cpus -info: Entering event queue @ 1399365853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1400365853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1401365853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1402365853500. Starting simulation... -switching cpus -info: Entering event queue @ 1403365725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1404365725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1405365725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1406365725500. Starting simulation... -switching cpus -info: Entering event queue @ 1407365597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1408365597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1409365597500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1410365597500. Starting simulation... -switching cpus -info: Entering event queue @ 1411365469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1412365469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1413365469500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1414365469500. Starting simulation... -switching cpus -info: Entering event queue @ 1415365341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1416365341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1417365341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1418365341500. Starting simulation... -switching cpus -info: Entering event queue @ 1419365213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1420365213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1421365213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1422365213500. Starting simulation... -switching cpus -info: Entering event queue @ 1423365085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1424365085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1425365085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1426365085500. Starting simulation... -switching cpus -info: Entering event queue @ 1427364957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1428364957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1429364957500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1430364957500. Starting simulation... -switching cpus -info: Entering event queue @ 1431364829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1432364829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1433364829500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1434364829500. Starting simulation... -switching cpus -info: Entering event queue @ 1435364701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1436364701500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1437364701500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1438364701500. Starting simulation... -switching cpus -info: Entering event queue @ 1439364573500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1440364573500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1441364573500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1442364573500. Starting simulation... -switching cpus -info: Entering event queue @ 1443364445500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1444364445500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1445364445500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1446364445500. Starting simulation... -switching cpus -info: Entering event queue @ 1447364317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1448364317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1449364317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1450364317500. Starting simulation... -switching cpus -info: Entering event queue @ 1451364189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1452364189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1453364189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1454364189500. Starting simulation... -switching cpus -info: Entering event queue @ 1455364061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1456364061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1457364061500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1458364061500. Starting simulation... -switching cpus -info: Entering event queue @ 1459363933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1460363933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1461363933500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1462363933500. Starting simulation... -switching cpus -info: Entering event queue @ 1463363805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1464363805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1465363805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1466363805500. Starting simulation... -switching cpus -info: Entering event queue @ 1467363677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1468363677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1469363677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1470363677500. Starting simulation... -switching cpus -info: Entering event queue @ 1471363549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1472363549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1473363549500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1474363549500. Starting simulation... -switching cpus -info: Entering event queue @ 1475363421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1476363421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1477363421500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1478363421500. Starting simulation... -switching cpus -info: Entering event queue @ 1479363293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1480363293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1481363293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1482363293500. Starting simulation... -switching cpus -info: Entering event queue @ 1483363165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1484363165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1485363165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1486363165500. Starting simulation... -switching cpus -info: Entering event queue @ 1487363037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1488363037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1489363037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1490363037500. Starting simulation... -switching cpus -info: Entering event queue @ 1491362909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1492362909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1493362909500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1494362909500. Starting simulation... -switching cpus -info: Entering event queue @ 1495362781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1496362781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1497362781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1498362781500. Starting simulation... -switching cpus -info: Entering event queue @ 1499362653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1500362653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1501362653500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1502362653500. Starting simulation... -switching cpus -info: Entering event queue @ 1503362525500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1504362525500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1505362525500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1506362525500. Starting simulation... -switching cpus -info: Entering event queue @ 1507362397500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1508362397500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1509362397500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1510362397500. Starting simulation... -switching cpus -info: Entering event queue @ 1511362269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1512362269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1513362269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1514362269500. Starting simulation... -switching cpus -info: Entering event queue @ 1515362141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1516362141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1517362141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1518362141500. Starting simulation... -switching cpus -info: Entering event queue @ 1519362013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1520362013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1521362013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1522362013500. Starting simulation... -switching cpus -info: Entering event queue @ 1523361885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1524361885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1525361885500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1526361885500. Starting simulation... -switching cpus -info: Entering event queue @ 1527361757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1528361757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1529361757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1530361757500. Starting simulation... -switching cpus -info: Entering event queue @ 1531361629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1532361629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1533361629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1534361629500. Starting simulation... -switching cpus -info: Entering event queue @ 1535361501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1536361501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1537361501500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1538361501500. Starting simulation... -switching cpus -info: Entering event queue @ 1539361373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1540361373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1541361373500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1542361373500. Starting simulation... -switching cpus -info: Entering event queue @ 1543361245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1544361245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1545361245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1546361245500. Starting simulation... -switching cpus -info: Entering event queue @ 1547361117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1548361117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1549361117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1550361117500. Starting simulation... -switching cpus -info: Entering event queue @ 1551360989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1552360989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1553360989500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1554360989500. Starting simulation... -switching cpus -info: Entering event queue @ 1555360861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1556360861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1557360861500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1558360861500. Starting simulation... -switching cpus -info: Entering event queue @ 1559360733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1560360733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1561360733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1562360733500. Starting simulation... -switching cpus -info: Entering event queue @ 1563360605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1564360605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1565360605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1566360605500. Starting simulation... -switching cpus -info: Entering event queue @ 1567360477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1568360477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1569360477500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1570360477500. Starting simulation... -switching cpus -info: Entering event queue @ 1571360349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1572360349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1573360349500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1574360349500. Starting simulation... -switching cpus -info: Entering event queue @ 1575360221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1576360221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1577360221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1578360221500. Starting simulation... -switching cpus -info: Entering event queue @ 1579360093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1580360093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1581360093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1582360093500. Starting simulation... -switching cpus -info: Entering event queue @ 1583359965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1584359965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1585359965500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1586359965500. Starting simulation... -switching cpus -info: Entering event queue @ 1587359837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1588359837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1589359837500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1590359837500. Starting simulation... -switching cpus -info: Entering event queue @ 1591359709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1592359709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1593359709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1594359709500. Starting simulation... -switching cpus -info: Entering event queue @ 1595359581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1596359581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1597359581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1598359581500. Starting simulation... -switching cpus -info: Entering event queue @ 1599359453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1600359453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1601359453500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1602359453500. Starting simulation... -switching cpus -info: Entering event queue @ 1603359325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1604359325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1605359325500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1606359325500. Starting simulation... -switching cpus -info: Entering event queue @ 1607359197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1608359197500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1609359197500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1610359197500. Starting simulation... -switching cpus -info: Entering event queue @ 1611359069500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1612359069500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1613359069500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1614359069500. Starting simulation... -switching cpus -info: Entering event queue @ 1615358941500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1616358941500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1617358941500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1618358941500. Starting simulation... -switching cpus -info: Entering event queue @ 1619358813500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1620358813500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1621358813500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1622358813500. Starting simulation... -switching cpus -info: Entering event queue @ 1623358685500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1624358685500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1625358685500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1626358685500. Starting simulation... -switching cpus -info: Entering event queue @ 1627358557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1628358557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1629358557500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1630358557500. Starting simulation... -switching cpus -info: Entering event queue @ 1631358429500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1632358429500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1633358429500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1634358429500. Starting simulation... -switching cpus -info: Entering event queue @ 1635358301500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1636358301500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1637358301500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1638358301500. Starting simulation... -switching cpus -info: Entering event queue @ 1639358173500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1640358173500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1641358173500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1642358173500. Starting simulation... -switching cpus -info: Entering event queue @ 1643358045500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1644358045500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1645358045500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1646358045500. Starting simulation... -switching cpus -info: Entering event queue @ 1647357917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1648357917500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1649357917500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1650357917500. Starting simulation... -switching cpus -info: Entering event queue @ 1651357789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1652357789500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1653357789500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1654357789500. Starting simulation... -switching cpus -info: Entering event queue @ 1655357661500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1656357661500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1657357661500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1658357661500. Starting simulation... -switching cpus -info: Entering event queue @ 1659357533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1660357533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1661357533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1662357533500. Starting simulation... -switching cpus -info: Entering event queue @ 1663357405500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1664357405500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1665357405500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1666357405500. Starting simulation... -switching cpus -info: Entering event queue @ 1667357277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1668357277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1669357277500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1670357277500. Starting simulation... -switching cpus -info: Entering event queue @ 1671357149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1672357149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1673357149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1674357149500. Starting simulation... -switching cpus -info: Entering event queue @ 1675357021500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1676357021500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1677357021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1678357021500. Starting simulation... -switching cpus -info: Entering event queue @ 1679356893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1680356893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1681356893500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1682356893500. Starting simulation... -switching cpus -info: Entering event queue @ 1683356765500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1684356765500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1685356765500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1686356765500. Starting simulation... -switching cpus -info: Entering event queue @ 1687356637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1688356637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1689356637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1690356637500. Starting simulation... -switching cpus -info: Entering event queue @ 1691356509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1692356509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1693356509500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1694356509500. Starting simulation... -switching cpus -info: Entering event queue @ 1695356381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1696356381500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1697356381500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1698356381500. Starting simulation... -switching cpus -info: Entering event queue @ 1699356253500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1700356253500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1701356253500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1702356253500. Starting simulation... -switching cpus -info: Entering event queue @ 1703356125500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1704356125500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1705356125500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1706356125500. Starting simulation... -switching cpus -info: Entering event queue @ 1707355997500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1708355997500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1709355997500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1710355997500. Starting simulation... -switching cpus -info: Entering event queue @ 1711355869500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1712355869500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1713355869500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1714355869500. Starting simulation... -switching cpus -info: Entering event queue @ 1715355741500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1716355741500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1717355741500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1718355741500. Starting simulation... -switching cpus -info: Entering event queue @ 1719355613500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1720355613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1721355613500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1722355613500. Starting simulation... -switching cpus -info: Entering event queue @ 1723355485500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1724355485500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1725355485500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1726355485500. Starting simulation... -switching cpus -info: Entering event queue @ 1727355357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1728355357500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1729355357500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1730355357500. Starting simulation... -switching cpus -info: Entering event queue @ 1731355229500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1732355229500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1733355229500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1734355229500. Starting simulation... -switching cpus -info: Entering event queue @ 1735355101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1736355101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1737355101500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1738355101500. Starting simulation... -switching cpus -info: Entering event queue @ 1739354973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1740354973500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1741354973500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1742354973500. Starting simulation... -switching cpus -info: Entering event queue @ 1743354845500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1744354845500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1745354845500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1746354845500. Starting simulation... -switching cpus -info: Entering event queue @ 1747354717500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1748354717500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1749354717500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1750354717500. Starting simulation... -switching cpus -info: Entering event queue @ 1751354589500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1752354589500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1753354589500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1754354589500. Starting simulation... -switching cpus -info: Entering event queue @ 1755354461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1756354461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1757354461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1758354461500. Starting simulation... -switching cpus -info: Entering event queue @ 1759354333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1760354333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1761354333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1762354333500. Starting simulation... -switching cpus -info: Entering event queue @ 1763354205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1764354205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1765354205500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1766354205500. Starting simulation... -switching cpus -info: Entering event queue @ 1767354077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1768354077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1769354077500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1770354077500. Starting simulation... -switching cpus -info: Entering event queue @ 1771353949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1772353949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1773353949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1774353949500. Starting simulation... -switching cpus -info: Entering event queue @ 1775353821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1776353821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1777353821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1778353821500. Starting simulation... -switching cpus -info: Entering event queue @ 1779353693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1780353693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1781353693500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1782353693500. Starting simulation... -switching cpus -info: Entering event queue @ 1783353565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1784353565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1785353565500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1786353565500. Starting simulation... -switching cpus -info: Entering event queue @ 1787353437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1788353437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1789353437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1790353437500. Starting simulation... -switching cpus -info: Entering event queue @ 1791353309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1792353309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1793353309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1794353309500. Starting simulation... -switching cpus -info: Entering event queue @ 1795353181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1796353181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1797353181500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1798353181500. Starting simulation... -switching cpus -info: Entering event queue @ 1799353053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1800353053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1801353053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1802353053500. Starting simulation... -switching cpus -info: Entering event queue @ 1803352925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1804352925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1805352925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1806352925500. Starting simulation... -switching cpus -info: Entering event queue @ 1807352797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1808352797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1809352797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1810352797500. Starting simulation... -switching cpus -info: Entering event queue @ 1811352669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1812352669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1813352669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1814352669500. Starting simulation... -switching cpus -info: Entering event queue @ 1815352541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1816352541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1817352541500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1818352541500. Starting simulation... -switching cpus -info: Entering event queue @ 1819352413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1820352413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1821352413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1822352413500. Starting simulation... -switching cpus -info: Entering event queue @ 1823352285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1824352285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1825352285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1826352285500. Starting simulation... -switching cpus -info: Entering event queue @ 1827352157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1828352157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1829352157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1830352157500. Starting simulation... -switching cpus -info: Entering event queue @ 1831352029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1832352029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1833352029500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1834352029500. Starting simulation... -switching cpus -info: Entering event queue @ 1835351901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1836351901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1837351901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1838351901500. Starting simulation... -switching cpus -info: Entering event queue @ 1839351773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1840351773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1841351773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1842351773500. Starting simulation... -switching cpus -info: Entering event queue @ 1843351645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1844351645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1845351645500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1846351645500. Starting simulation... -switching cpus -info: Entering event queue @ 1847351517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1848351517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1849351517500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1850351517500. Starting simulation... -switching cpus -info: Entering event queue @ 1851351389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1852351389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1853351389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1854351389500. Starting simulation... -switching cpus -info: Entering event queue @ 1855351261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1856351261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1857351261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1858351261500. Starting simulation... -switching cpus -info: Entering event queue @ 1859351133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1860351133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1861351133500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1862351133500. Starting simulation... -switching cpus -info: Entering event queue @ 1863351005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1864351005500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1865351005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1866351005500. Starting simulation... -switching cpus -info: Entering event queue @ 1867350877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1868350877500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1869350877500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1870350877500. Starting simulation... -switching cpus -info: Entering event queue @ 1871350749500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1872350749500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1873350749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1874350749500. Starting simulation... -switching cpus -info: Entering event queue @ 1875350621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1876350621500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1877350621500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1878350621500. Starting simulation... -switching cpus -info: Entering event queue @ 1879350493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1880350493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1881350493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1882350493500. Starting simulation... -switching cpus -info: Entering event queue @ 1883350365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1884350365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1885350365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1886350365500. Starting simulation... -switching cpus -info: Entering event queue @ 1887350237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1888350237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1889350237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1890350237500. Starting simulation... -switching cpus -info: Entering event queue @ 1891350109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1892350109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1893350109500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1894350109500. Starting simulation... -switching cpus -info: Entering event queue @ 1895349981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1896349981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1897349981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1898349981500. Starting simulation... -switching cpus -info: Entering event queue @ 1899349853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1900349853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1901349853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1902349853500. Starting simulation... -switching cpus -info: Entering event queue @ 1903349725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1904349725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1905349725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1906349725500. Starting simulation... -switching cpus -info: Entering event queue @ 1907349597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1908349597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1909349597500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1910349597500. Starting simulation... -switching cpus -info: Entering event queue @ 1911349469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1912349469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 1913349469500. Starting simulation... -switching cpus -info: Entering event queue @ 1913349477000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1914349477000. Starting simulation... -switching cpus -info: Entering event queue @ 1915349341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1916349341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1917349341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1918349341500. Starting simulation... -switching cpus -info: Entering event queue @ 1919349213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1920349213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1921349213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1922349213500. Starting simulation... -switching cpus -info: Entering event queue @ 1923349085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1924349085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1925349085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1926349085500. Starting simulation... -switching cpus -info: Entering event queue @ 1927348957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1928348957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1929348957500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1930348957500. Starting simulation... -switching cpus -info: Entering event queue @ 1931348829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1932348829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1933348829500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1934348829500. Starting simulation... -switching cpus -info: Entering event queue @ 1935348701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1936348701500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1937348701500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1938348701500. Starting simulation... -switching cpus -info: Entering event queue @ 1939348573500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1940348573500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1941348573500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1942348573500. Starting simulation... -switching cpus -info: Entering event queue @ 1943348445500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1944348445500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1945348445500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1946348445500. Starting simulation... -switching cpus -info: Entering event queue @ 1947348317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1948348317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1949348317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1950348317500. Starting simulation... -switching cpus -info: Entering event queue @ 1951348189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1952348189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1953348189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1954348189500. Starting simulation... -switching cpus -info: Entering event queue @ 1955348061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1956348061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1957348061500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1958348061500. Starting simulation... -switching cpus -info: Entering event queue @ 1959347933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1960347933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1961347933500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1962347933500. Starting simulation... -switching cpus -info: Entering event queue @ 1963347805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1964347805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1965347805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1966347805500. Starting simulation... -switching cpus -info: Entering event queue @ 1967347677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1968347677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1969347677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1970347677500. Starting simulation... -switching cpus -info: Entering event queue @ 1971347549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1972347549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1973347549500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1974347549500. Starting simulation... -switching cpus -info: Entering event queue @ 1975347421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1976347421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1977347421500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1978347421500. Starting simulation... -switching cpus -info: Entering event queue @ 1979347293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1980347293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1981347293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1982347293500. Starting simulation... -switching cpus -info: Entering event queue @ 1983347165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1984347165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1985347165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1986347165500. Starting simulation... -switching cpus -info: Entering event queue @ 1987347037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1988347037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1989347037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1990347037500. Starting simulation... -switching cpus -info: Entering event queue @ 1991346909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1992346909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1993346909500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1994346909500. Starting simulation... -switching cpus -info: Entering event queue @ 1995346781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 1996346781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 1997346781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1998346781500. Starting simulation... -switching cpus -info: Entering event queue @ 1999346653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2000346653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2001346653500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2002346653500. Starting simulation... -switching cpus -info: Entering event queue @ 2003346525500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2004346525500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2005346525500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2006346525500. Starting simulation... -switching cpus -info: Entering event queue @ 2007346397500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2008346397500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2009346397500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2010346397500. Starting simulation... -switching cpus -info: Entering event queue @ 2011346269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2012346269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2013346269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2014346269500. Starting simulation... -switching cpus -info: Entering event queue @ 2015346141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2016346141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2017346141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2018346141500. Starting simulation... -switching cpus -info: Entering event queue @ 2019346013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2020346013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2021346013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2022346013500. Starting simulation... -switching cpus -info: Entering event queue @ 2023345885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2024345885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2025345885500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2026345885500. Starting simulation... -switching cpus -info: Entering event queue @ 2027345757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2028345757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2029345757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2030345757500. Starting simulation... -switching cpus -info: Entering event queue @ 2031345629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2032345629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2033345629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2034345629500. Starting simulation... -switching cpus -info: Entering event queue @ 2035345501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2036345501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2037345501500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2038345501500. Starting simulation... -switching cpus -info: Entering event queue @ 2039345373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2040345373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2041345373500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2042345373500. Starting simulation... -switching cpus -info: Entering event queue @ 2043345245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2044345245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2045345245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2046345245500. Starting simulation... -switching cpus -info: Entering event queue @ 2047345117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2048345117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2049345117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2050345117500. Starting simulation... -switching cpus -info: Entering event queue @ 2051344989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2052344989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2053344989500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2054344989500. Starting simulation... -switching cpus -info: Entering event queue @ 2055344861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2056344861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2057344861500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2058344861500. Starting simulation... -switching cpus -info: Entering event queue @ 2059344733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2060344733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2061344733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2062344733500. Starting simulation... -switching cpus -info: Entering event queue @ 2063344605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2064344605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2065344605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2066344605500. Starting simulation... -switching cpus -info: Entering event queue @ 2067344477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2068344477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2069344477500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2070344477500. Starting simulation... -switching cpus -info: Entering event queue @ 2071344349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2072344349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2073344349500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2074344349500. Starting simulation... -switching cpus -info: Entering event queue @ 2075344221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2076344221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2077344221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2078344221500. Starting simulation... -switching cpus -info: Entering event queue @ 2079344093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2080344093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2081344093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2082344093500. Starting simulation... -switching cpus -info: Entering event queue @ 2083343965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2084343965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2085343965500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2086343965500. Starting simulation... -switching cpus -info: Entering event queue @ 2087343837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2088343837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2089343837500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2090343837500. Starting simulation... -switching cpus -info: Entering event queue @ 2091343709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2092343709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2093343709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2094343709500. Starting simulation... -switching cpus -info: Entering event queue @ 2095343581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2096343581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2097343581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2098343581500. Starting simulation... -switching cpus -info: Entering event queue @ 2099343453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2100343453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2101343453500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2102343453500. Starting simulation... -switching cpus -info: Entering event queue @ 2103343325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2104343325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2105343325500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2106343325500. Starting simulation... -switching cpus -info: Entering event queue @ 2107343197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2108343197500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2109343197500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2110343197500. Starting simulation... -switching cpus -info: Entering event queue @ 2111343069500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2112343069500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2113343069500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2114343069500. Starting simulation... -switching cpus -info: Entering event queue @ 2115342941500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2116342941500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2117342941500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2118342941500. Starting simulation... -switching cpus -info: Entering event queue @ 2119342813500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2120342813500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2121342813500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2122342813500. Starting simulation... -switching cpus -info: Entering event queue @ 2123342685500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2124342685500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2125342685500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2126342685500. Starting simulation... -switching cpus -info: Entering event queue @ 2127342557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2128342557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2129342557500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2130342557500. Starting simulation... -switching cpus -info: Entering event queue @ 2131342429500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2132342429500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2133342429500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2134342429500. Starting simulation... -switching cpus -info: Entering event queue @ 2135342301500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2136342301500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2137342301500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2138342301500. Starting simulation... -switching cpus -info: Entering event queue @ 2139342173500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2140342173500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2141342173500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2142342173500. Starting simulation... -switching cpus -info: Entering event queue @ 2143342045500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2144342045500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2145342045500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2146342045500. Starting simulation... -switching cpus -info: Entering event queue @ 2147341917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2148341917500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2149341917500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2150341917500. Starting simulation... -switching cpus -info: Entering event queue @ 2151341789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2152341789500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2153341789500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2154341789500. Starting simulation... -switching cpus -info: Entering event queue @ 2155341661500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2156341661500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2157341661500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2158341661500. Starting simulation... -switching cpus -info: Entering event queue @ 2159341533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2160341533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2161341533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2162341533500. Starting simulation... -switching cpus -info: Entering event queue @ 2163341405500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2164341405500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2165341405500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2166341405500. Starting simulation... -switching cpus -info: Entering event queue @ 2167341277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2168341277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2169341277500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2170341277500. Starting simulation... -switching cpus -info: Entering event queue @ 2171341149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2172341149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2173341149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2174341149500. Starting simulation... -switching cpus -info: Entering event queue @ 2175341021500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2176341021500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2177341021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2178341021500. Starting simulation... -switching cpus -info: Entering event queue @ 2179340893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2180340893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2181340893500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2182340893500. Starting simulation... -switching cpus -info: Entering event queue @ 2183340765500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2184340765500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2185340765500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2186340765500. Starting simulation... -switching cpus -info: Entering event queue @ 2187340637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2188340637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2189340637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2190340637500. Starting simulation... -switching cpus -info: Entering event queue @ 2191340509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2192340509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2193340509500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2194340509500. Starting simulation... -switching cpus -info: Entering event queue @ 2195340381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2196340381500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2197340381500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2198340381500. Starting simulation... -switching cpus -info: Entering event queue @ 2199340253500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2200340253500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2201340253500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2202340253500. Starting simulation... -switching cpus -info: Entering event queue @ 2203340125500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2204340125500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2205340125500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2206340125500. Starting simulation... -switching cpus -info: Entering event queue @ 2207339997500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2208339997500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2209339997500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2210339997500. Starting simulation... -switching cpus -info: Entering event queue @ 2211339869500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2212339869500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2213339869500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2214339869500. Starting simulation... -switching cpus -info: Entering event queue @ 2215339741500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2216339741500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2217339741500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2218339741500. Starting simulation... -switching cpus -info: Entering event queue @ 2219339613500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2220339613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2221339613500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2222339613500. Starting simulation... -switching cpus -info: Entering event queue @ 2223339485500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2224339485500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2225339485500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2226339485500. Starting simulation... -switching cpus -info: Entering event queue @ 2227339357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2228339357500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2229339357500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2230339357500. Starting simulation... -switching cpus -info: Entering event queue @ 2231339229500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2232339229500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2233339229500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2234339229500. Starting simulation... -switching cpus -info: Entering event queue @ 2235339101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2236339101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2237339101500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2238339101500. Starting simulation... -switching cpus -info: Entering event queue @ 2239338973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2240338973500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2241338973500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2242338973500. Starting simulation... -switching cpus -info: Entering event queue @ 2243338845500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2244338845500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2245338845500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2246338845500. Starting simulation... -switching cpus -info: Entering event queue @ 2247338717500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2248338717500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2249338717500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2250338717500. Starting simulation... -switching cpus -info: Entering event queue @ 2251338589500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2252338589500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2253338589500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2254338589500. Starting simulation... -switching cpus -info: Entering event queue @ 2255338461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2256338461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2257338461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2258338461500. Starting simulation... -switching cpus -info: Entering event queue @ 2259338333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2260338333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2261338333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2262338333500. Starting simulation... -switching cpus -info: Entering event queue @ 2263338205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2264338205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2265338205500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2266338205500. Starting simulation... -switching cpus -info: Entering event queue @ 2267338077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2268338077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2269338077500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2270338077500. Starting simulation... -switching cpus -info: Entering event queue @ 2271337949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2272337949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2273337949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2274337949500. Starting simulation... -switching cpus -info: Entering event queue @ 2275337821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2276337821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2277337821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2278337821500. Starting simulation... -switching cpus -info: Entering event queue @ 2279337693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2280337693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2281337693500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2282337693500. Starting simulation... -switching cpus -info: Entering event queue @ 2283337565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2284337565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2285337565500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2286337565500. Starting simulation... -switching cpus -info: Entering event queue @ 2287337437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2288337437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2289337437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2290337437500. Starting simulation... -switching cpus -info: Entering event queue @ 2291337309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2292337309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2293337309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2294337309500. Starting simulation... -switching cpus -info: Entering event queue @ 2295337181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2296337181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2297337181500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2298337181500. Starting simulation... -switching cpus -info: Entering event queue @ 2299337053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2300337053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2301337053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2302337053500. Starting simulation... -switching cpus -info: Entering event queue @ 2303336925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2304336925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2305336925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2306336925500. Starting simulation... -switching cpus -info: Entering event queue @ 2307336797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2308336797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2309336797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2310336797500. Starting simulation... -switching cpus -info: Entering event queue @ 2311336669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2312336669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2313336669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2314336669500. Starting simulation... -switching cpus -info: Entering event queue @ 2315336541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2316336541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2317336541500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2318336541500. Starting simulation... -switching cpus -info: Entering event queue @ 2319336413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2320336413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2321336413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2322336413500. Starting simulation... -switching cpus -info: Entering event queue @ 2323336285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2324336285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2325336285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2326336285500. Starting simulation... -switching cpus -info: Entering event queue @ 2327336157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2328336157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2329336157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2330336157500. Starting simulation... -switching cpus -info: Entering event queue @ 2331336029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2332336029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2333336029500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2334336029500. Starting simulation... -switching cpus -info: Entering event queue @ 2335335901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2336335901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2337335901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2338335901500. Starting simulation... -switching cpus -info: Entering event queue @ 2339335773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2340335773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2341335773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2342335773500. Starting simulation... -switching cpus -info: Entering event queue @ 2343335645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2344335645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2345335645500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2346335645500. Starting simulation... -switching cpus -info: Entering event queue @ 2347335517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2348335517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2349335517500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2350335517500. Starting simulation... -switching cpus -info: Entering event queue @ 2351335389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2352335389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2353335389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2354335389500. Starting simulation... -switching cpus -info: Entering event queue @ 2355335261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2356335261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2357335261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2358335261500. Starting simulation... -switching cpus -info: Entering event queue @ 2359335133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2360335133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2361335133500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2362335133500. Starting simulation... -switching cpus -info: Entering event queue @ 2363335005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2364335005500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2365335005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2366335005500. Starting simulation... -switching cpus -info: Entering event queue @ 2367334877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2368334877500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2369334877500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2370334877500. Starting simulation... -switching cpus -info: Entering event queue @ 2371334749500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2372334749500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2373334749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2374334749500. Starting simulation... -switching cpus -info: Entering event queue @ 2375334621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2376334621500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2377334621500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2378334621500. Starting simulation... -switching cpus -info: Entering event queue @ 2379334493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2380334493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2381334493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2382334493500. Starting simulation... -switching cpus -info: Entering event queue @ 2383334365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2384334365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2385334365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2386334365500. Starting simulation... -switching cpus -info: Entering event queue @ 2387334237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2388334237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2389334237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2390334237500. Starting simulation... -switching cpus -info: Entering event queue @ 2391334109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2392334109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2393334109500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2394334109500. Starting simulation... -switching cpus -info: Entering event queue @ 2395333981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2396333981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2397333981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2398333981500. Starting simulation... -switching cpus -info: Entering event queue @ 2399333853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2400333853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2401333853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2402333853500. Starting simulation... -switching cpus -info: Entering event queue @ 2403333725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2404333725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2405333725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2406333725500. Starting simulation... -switching cpus -info: Entering event queue @ 2407333597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2408333597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2409333597500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2410333597500. Starting simulation... -switching cpus -info: Entering event queue @ 2411333469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2412333469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2413333469500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2414333469500. Starting simulation... -switching cpus -info: Entering event queue @ 2415333341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2416333341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2417333341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2418333341500. Starting simulation... -switching cpus -info: Entering event queue @ 2419333213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2420333213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2421333213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2422333213500. Starting simulation... -switching cpus -info: Entering event queue @ 2423333085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2424333085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2425333085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2426333085500. Starting simulation... -switching cpus -info: Entering event queue @ 2427332957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2428332957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2429332957500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2430332957500. Starting simulation... -switching cpus -info: Entering event queue @ 2431332829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2432332829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2433332829500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2434332829500. Starting simulation... -switching cpus -info: Entering event queue @ 2435332701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2436332701500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2437332701500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2438332701500. Starting simulation... -switching cpus -info: Entering event queue @ 2439332573500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2440332573500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2441332573500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2442332573500. Starting simulation... -switching cpus -info: Entering event queue @ 2443332445500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2444332445500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2445332445500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2446332445500. Starting simulation... -switching cpus -info: Entering event queue @ 2447332317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2448332317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2449332317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2450332317500. Starting simulation... -switching cpus -info: Entering event queue @ 2451332189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2452332189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2453332189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2454332189500. Starting simulation... -switching cpus -info: Entering event queue @ 2455332061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2456332061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2457332061500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2458332061500. Starting simulation... -switching cpus -info: Entering event queue @ 2459331933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2460331933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2461331933500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2462331933500. Starting simulation... -switching cpus -info: Entering event queue @ 2463331805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2464331805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2465331805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2466331805500. Starting simulation... -switching cpus -info: Entering event queue @ 2467331677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2468331677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2469331677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2470331677500. Starting simulation... -switching cpus -info: Entering event queue @ 2471331549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2472331549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2473331549500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2474331549500. Starting simulation... -switching cpus -info: Entering event queue @ 2475331421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2476331421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2477331421500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2478331421500. Starting simulation... -switching cpus -info: Entering event queue @ 2479331293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2480331293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2481331293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2482331293500. Starting simulation... -switching cpus -info: Entering event queue @ 2483331165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2484331165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2485331165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2486331165500. Starting simulation... -switching cpus -info: Entering event queue @ 2487331037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2488331037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2489331037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2490331037500. Starting simulation... -switching cpus -info: Entering event queue @ 2491330909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2492330909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2493330909500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2494330909500. Starting simulation... -switching cpus -info: Entering event queue @ 2495330781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2496330781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2497330781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2498330781500. Starting simulation... -switching cpus -info: Entering event queue @ 2499330653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2500330653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2501330653500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2502330653500. Starting simulation... -switching cpus -info: Entering event queue @ 2503330525500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2504330525500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2505330525500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2506330525500. Starting simulation... -switching cpus -info: Entering event queue @ 2507330397500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2508330397500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2509330397500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2510330397500. Starting simulation... -switching cpus -info: Entering event queue @ 2511330269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2512330269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2513330269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2514330269500. Starting simulation... -switching cpus -info: Entering event queue @ 2515330141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2516330141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2517330141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2518330141500. Starting simulation... -switching cpus -info: Entering event queue @ 2519330013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2520330013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2521330013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2522330013500. Starting simulation... -switching cpus -info: Entering event queue @ 2523329885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2524329885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2525329885500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2526329885500. Starting simulation... -switching cpus -info: Entering event queue @ 2527329757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2528329757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2529329757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2530329757500. Starting simulation... -switching cpus -info: Entering event queue @ 2531329629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2532329629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2533329629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2534329629500. Starting simulation... -switching cpus -info: Entering event queue @ 2535329501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2536329501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2537329501500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2538329501500. Starting simulation... -switching cpus -info: Entering event queue @ 2539329373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2540329373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2541329373500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2542329373500. Starting simulation... -switching cpus -info: Entering event queue @ 2543329245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2544329245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2545329245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2546329245500. Starting simulation... -switching cpus -info: Entering event queue @ 2547329117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2548329117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2549329117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2550329117500. Starting simulation... -switching cpus -info: Entering event queue @ 2551328989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2552328989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2553328989500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2554328989500. Starting simulation... -switching cpus -info: Entering event queue @ 2555328861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2556328861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2557328861500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2558328861500. Starting simulation... -switching cpus -info: Entering event queue @ 2559328733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2560328733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2561328733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2562328733500. Starting simulation... -switching cpus -info: Entering event queue @ 2563328605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2564328605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2565328605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2566328605500. Starting simulation... -switching cpus -info: Entering event queue @ 2567328477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2568328477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2569328477500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2570328477500. Starting simulation... -switching cpus -info: Entering event queue @ 2571328349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2572328349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2573328349500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2574328349500. Starting simulation... -switching cpus -info: Entering event queue @ 2575328221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2576328221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2577328221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2578328221500. Starting simulation... -switching cpus -info: Entering event queue @ 2579328093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2580328093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2581328093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2582328093500. Starting simulation... -switching cpus -info: Entering event queue @ 2583327965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2584327965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2585327965500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2586327965500. Starting simulation... -switching cpus -info: Entering event queue @ 2587327837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2588327837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2589327837500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2590327837500. Starting simulation... -switching cpus -info: Entering event queue @ 2591327709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2592327709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2593327709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2594327709500. Starting simulation... -switching cpus -info: Entering event queue @ 2595327581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2596327581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2597327581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2598327581500. Starting simulation... -switching cpus -info: Entering event queue @ 2599327453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2600327453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2601327453500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2602327453500. Starting simulation... -switching cpus -info: Entering event queue @ 2603327325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2604327325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2605327325500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2606327325500. Starting simulation... -switching cpus -info: Entering event queue @ 2607327197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 2608327197500. Starting simulation... -switching cpus -info: Entering event queue @ 2608327199000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2609327199000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2610327199000. Starting simulation... -switching cpus -info: Entering event queue @ 2611327069500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2612327069500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2613327069500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2614327069500. Starting simulation... -switching cpus -info: Entering event queue @ 2615326941500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2616326941500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2617326941500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2618326941500. Starting simulation... -switching cpus -info: Entering event queue @ 2619326813500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2620326813500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2621326813500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2622326813500. Starting simulation... -switching cpus -info: Entering event queue @ 2623326685500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2624326685500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2625326685500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2626326685500. Starting simulation... -switching cpus -info: Entering event queue @ 2627326557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2628326557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2629326557500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2630326557500. Starting simulation... -switching cpus -info: Entering event queue @ 2631326429500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2632326429500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2633326429500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2634326429500. Starting simulation... -switching cpus -info: Entering event queue @ 2635326301500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2636326301500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2637326301500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2638326301500. Starting simulation... -switching cpus -info: Entering event queue @ 2639326173500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2640326173500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2641326173500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2642326173500. Starting simulation... -switching cpus -info: Entering event queue @ 2643326045500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2644326045500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2645326045500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2646326045500. Starting simulation... -switching cpus -info: Entering event queue @ 2647325917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2648325917500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2649325917500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2650325917500. Starting simulation... -switching cpus -info: Entering event queue @ 2651325789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2652325789500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2653325789500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2654325789500. Starting simulation... -switching cpus -info: Entering event queue @ 2655325661500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2656325661500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2657325661500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2658325661500. Starting simulation... -switching cpus -info: Entering event queue @ 2659325533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2660325533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2661325533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2662325533500. Starting simulation... -switching cpus -info: Entering event queue @ 2663325405500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2664325405500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2665325405500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2666325405500. Starting simulation... -switching cpus -info: Entering event queue @ 2667325277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2668325277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2669325277500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2670325277500. Starting simulation... -switching cpus -info: Entering event queue @ 2671325149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2672325149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2673325149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2674325149500. Starting simulation... -switching cpus -info: Entering event queue @ 2675325021500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2676325021500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2677325021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2678325021500. Starting simulation... -switching cpus -info: Entering event queue @ 2679324893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2680324893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2681324893500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2682324893500. Starting simulation... -switching cpus -info: Entering event queue @ 2683324765500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2684324765500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2685324765500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2686324765500. Starting simulation... -switching cpus -info: Entering event queue @ 2687324637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2688324637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2689324637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2690324637500. Starting simulation... -switching cpus -info: Entering event queue @ 2691324509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2692324509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2693324509500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2694324509500. Starting simulation... -switching cpus -info: Entering event queue @ 2695324381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2696324381500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2697324381500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2698324381500. Starting simulation... -switching cpus -info: Entering event queue @ 2699324253500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2700324253500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2701324253500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2702324253500. Starting simulation... -switching cpus -info: Entering event queue @ 2703324125500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2704324125500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2705324125500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2706324125500. Starting simulation... -switching cpus -info: Entering event queue @ 2707323997500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2708323997500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2709323997500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2710323997500. Starting simulation... -switching cpus -info: Entering event queue @ 2711323869500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2712323869500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2713323869500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2714323869500. Starting simulation... -switching cpus -info: Entering event queue @ 2715323741500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2716323741500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2717323741500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2718323741500. Starting simulation... -switching cpus -info: Entering event queue @ 2719323613500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2720323613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2721323613500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2722323613500. Starting simulation... -switching cpus -info: Entering event queue @ 2723323485500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2724323485500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2725323485500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2726323485500. Starting simulation... -switching cpus -info: Entering event queue @ 2727323357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2728323357500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2729323357500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2730323357500. Starting simulation... -switching cpus -info: Entering event queue @ 2731323229500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2732323229500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2733323229500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2734323229500. Starting simulation... -switching cpus -info: Entering event queue @ 2735323101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2736323101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2737323101500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2738323101500. Starting simulation... -switching cpus -info: Entering event queue @ 2739322973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2740322973500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2741322973500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2742322973500. Starting simulation... -switching cpus -info: Entering event queue @ 2743322845500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2744322845500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2745322845500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2746322845500. Starting simulation... -switching cpus -info: Entering event queue @ 2747322717500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2748322717500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2749322717500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2750322717500. Starting simulation... -switching cpus -info: Entering event queue @ 2751322589500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2752322589500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2753322589500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2754322589500. Starting simulation... -switching cpus -info: Entering event queue @ 2755322461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2756322461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2757322461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2758322461500. Starting simulation... -switching cpus -info: Entering event queue @ 2759322333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2760322333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2761322333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2762322333500. Starting simulation... -switching cpus -info: Entering event queue @ 2763322205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2764322205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2765322205500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2766322205500. Starting simulation... -switching cpus -info: Entering event queue @ 2767322077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2768322077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2769322077500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2770322077500. Starting simulation... -switching cpus -info: Entering event queue @ 2771321949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2772321949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2773321949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2774321949500. Starting simulation... -switching cpus -info: Entering event queue @ 2775321821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2776321821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2777321821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2778321821500. Starting simulation... -switching cpus -info: Entering event queue @ 2779321693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2780321693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2781321693500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2782321693500. Starting simulation... -switching cpus -info: Entering event queue @ 2783321565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2784321565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2785321565500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2786321565500. Starting simulation... -switching cpus -info: Entering event queue @ 2787321437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2788321437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2789321437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2790321437500. Starting simulation... -switching cpus -info: Entering event queue @ 2791321309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2792321309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2793321309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2794321309500. Starting simulation... -switching cpus -info: Entering event queue @ 2795321181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2796321181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2797321181500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2798321181500. Starting simulation... -switching cpus -info: Entering event queue @ 2799321053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2800321053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2801321053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2802321053500. Starting simulation... -switching cpus -info: Entering event queue @ 2803320925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2804320925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2805320925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2806320925500. Starting simulation... -switching cpus -info: Entering event queue @ 2807320797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2808320797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2809320797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2810320797500. Starting simulation... -switching cpus -info: Entering event queue @ 2811320669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2812320669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2813320669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2814320669500. Starting simulation... -switching cpus -info: Entering event queue @ 2815320541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2816320541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2817320541500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2818320541500. Starting simulation... -switching cpus -info: Entering event queue @ 2819320413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2820320413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2821320413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2822320413500. Starting simulation... -switching cpus -info: Entering event queue @ 2823320285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2824320285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2825320285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2826320285500. Starting simulation... -switching cpus -info: Entering event queue @ 2827320157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2828320157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2829320157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2830320157500. Starting simulation... -switching cpus -info: Entering event queue @ 2831320029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2832320029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2833320029500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2834320029500. Starting simulation... -switching cpus -info: Entering event queue @ 2835319901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2836319901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2837319901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2838319901500. Starting simulation... -switching cpus -info: Entering event queue @ 2839319773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2840319773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2841319773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2842319773500. Starting simulation... -switching cpus -info: Entering event queue @ 2843319645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2844319645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2845319645500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2846319645500. Starting simulation... -switching cpus -info: Entering event queue @ 2847319517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2848319517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2849319517500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2850319517500. Starting simulation... -switching cpus -info: Entering event queue @ 2851319389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2852319389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2853319389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2854319389500. Starting simulation... -switching cpus -info: Entering event queue @ 2855319261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2856319261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2857319261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2858319261500. Starting simulation... -switching cpus -info: Entering event queue @ 2859319133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2860319133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2861319133500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2862319133500. Starting simulation... -switching cpus -info: Entering event queue @ 2863319005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2864319005500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2865319005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2866319005500. Starting simulation... -switching cpus -info: Entering event queue @ 2867318877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2868318877500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2869318877500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2870318877500. Starting simulation... -switching cpus -info: Entering event queue @ 2871318749500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2872318749500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2873318749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2874318749500. Starting simulation... -switching cpus -info: Entering event queue @ 2875318621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2876318621500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2877318621500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2878318621500. Starting simulation... -switching cpus -info: Entering event queue @ 2879318493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2880318493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2881318493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2882318493500. Starting simulation... -switching cpus -info: Entering event queue @ 2883318365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2884318365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2885318365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2886318365500. Starting simulation... -switching cpus -info: Entering event queue @ 2887318237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2888318237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2889318237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2890318237500. Starting simulation... -switching cpus -info: Entering event queue @ 2891318109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2892318109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2893318109500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2894318109500. Starting simulation... -switching cpus -info: Entering event queue @ 2895317981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2896317981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2897317981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2898317981500. Starting simulation... -switching cpus -info: Entering event queue @ 2899317853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2900317853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2901317853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2902317853500. Starting simulation... -switching cpus -info: Entering event queue @ 2903317725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2904317725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2905317725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2906317725500. Starting simulation... -switching cpus -info: Entering event queue @ 2907317597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2908317597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2909317597500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2910317597500. Starting simulation... -switching cpus -info: Entering event queue @ 2911317469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2912317469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2913317469500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2914317469500. Starting simulation... -switching cpus -info: Entering event queue @ 2915317341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2916317341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2917317341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2918317341500. Starting simulation... -switching cpus -info: Entering event queue @ 2919317213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2920317213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2921317213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2922317213500. Starting simulation... -switching cpus -info: Entering event queue @ 2923317085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2924317085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2925317085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2926317085500. Starting simulation... -switching cpus -info: Entering event queue @ 2927316957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2928316957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2929316957500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2930316957500. Starting simulation... -switching cpus -info: Entering event queue @ 2931316829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2932316829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2933316829500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2934316829500. Starting simulation... -switching cpus -info: Entering event queue @ 2935316701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2936316701500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2937316701500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2938316701500. Starting simulation... -switching cpus -info: Entering event queue @ 2939316573500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2940316573500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2941316573500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2942316573500. Starting simulation... -switching cpus -info: Entering event queue @ 2943316445500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2944316445500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2945316445500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2946316445500. Starting simulation... -switching cpus -info: Entering event queue @ 2947316317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2948316317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2949316317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2950316317500. Starting simulation... -switching cpus -info: Entering event queue @ 2951316189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2952316189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2953316189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2954316189500. Starting simulation... -switching cpus -info: Entering event queue @ 2955316061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2956316061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2957316061500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2958316061500. Starting simulation... -switching cpus -info: Entering event queue @ 2959315933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2960315933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2961315933500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2962315933500. Starting simulation... -switching cpus -info: Entering event queue @ 2963315805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2964315805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2965315805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2966315805500. Starting simulation... -switching cpus -info: Entering event queue @ 2967315677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2968315677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2969315677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2970315677500. Starting simulation... -switching cpus -info: Entering event queue @ 2971315549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2972315549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2973315549500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2974315549500. Starting simulation... -switching cpus -info: Entering event queue @ 2975315421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2976315421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2977315421500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2978315421500. Starting simulation... -switching cpus -info: Entering event queue @ 2979315293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2980315293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2981315293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2982315293500. Starting simulation... -switching cpus -info: Entering event queue @ 2983315165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2984315165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2985315165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2986315165500. Starting simulation... -switching cpus -info: Entering event queue @ 2987315037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2988315037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2989315037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2990315037500. Starting simulation... -switching cpus -info: Entering event queue @ 2991314909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2992314909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2993314909500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2994314909500. Starting simulation... -switching cpus -info: Entering event queue @ 2995314781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 2996314781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 2997314781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2998314781500. Starting simulation... -switching cpus -info: Entering event queue @ 2999314653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3000314653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3001314653500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3002314653500. Starting simulation... -switching cpus -info: Entering event queue @ 3003314525500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3004314525500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3005314525500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3006314525500. Starting simulation... -switching cpus -info: Entering event queue @ 3007314397500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3008314397500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3009314397500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3010314397500. Starting simulation... -switching cpus -info: Entering event queue @ 3011314269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3012314269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3013314269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3014314269500. Starting simulation... -switching cpus -info: Entering event queue @ 3015314141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3016314141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3017314141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3018314141500. Starting simulation... -switching cpus -info: Entering event queue @ 3019314013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3020314013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3021314013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3022314013500. Starting simulation... -switching cpus -info: Entering event queue @ 3023313885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3024313885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3025313885500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3026313885500. Starting simulation... -switching cpus -info: Entering event queue @ 3027313757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3028313757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3029313757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3030313757500. Starting simulation... -switching cpus -info: Entering event queue @ 3031313629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3032313629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3033313629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3034313629500. Starting simulation... -switching cpus -info: Entering event queue @ 3035313501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3036313501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3037313501500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3038313501500. Starting simulation... -switching cpus -info: Entering event queue @ 3039313373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3040313373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3041313373500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3042313373500. Starting simulation... -switching cpus -info: Entering event queue @ 3043313245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3044313245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3045313245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3046313245500. Starting simulation... -switching cpus -info: Entering event queue @ 3047313117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3048313117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3049313117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3050313117500. Starting simulation... -switching cpus -info: Entering event queue @ 3051312989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3052312989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3053312989500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3054312989500. Starting simulation... -switching cpus -info: Entering event queue @ 3055312861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3056312861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3057312861500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3058312861500. Starting simulation... -switching cpus -info: Entering event queue @ 3059312733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3060312733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3061312733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3062312733500. Starting simulation... -switching cpus -info: Entering event queue @ 3063312605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3064312605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3065312605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3066312605500. Starting simulation... -switching cpus -info: Entering event queue @ 3067312477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3068312477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3069312477500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3070312477500. Starting simulation... -switching cpus -info: Entering event queue @ 3071312349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3072312349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3073312349500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3074312349500. Starting simulation... -switching cpus -info: Entering event queue @ 3075312221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3076312221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3077312221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3078312221500. Starting simulation... -switching cpus -info: Entering event queue @ 3079312093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3080312093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3081312093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3082312093500. Starting simulation... -switching cpus -info: Entering event queue @ 3083311965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3084311965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3085311965500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3086311965500. Starting simulation... -switching cpus -info: Entering event queue @ 3087311837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3088311837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3089311837500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3090311837500. Starting simulation... -switching cpus -info: Entering event queue @ 3091311709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3092311709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3093311709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3094311709500. Starting simulation... -switching cpus -info: Entering event queue @ 3095311581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3096311581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3097311581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3098311581500. Starting simulation... -switching cpus -info: Entering event queue @ 3099311453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3100311453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3101311453500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3102311453500. Starting simulation... -switching cpus -info: Entering event queue @ 3103311325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3104311325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3105311325500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3106311325500. Starting simulation... -switching cpus -info: Entering event queue @ 3107311197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3108311197500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3109311197500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3110311197500. Starting simulation... -switching cpus -info: Entering event queue @ 3111311069500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3112311069500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3113311069500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3114311069500. Starting simulation... -switching cpus -info: Entering event queue @ 3115310941500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3116310941500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3117310941500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3118310941500. Starting simulation... -switching cpus -info: Entering event queue @ 3119310813500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3120310813500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3121310813500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3122310813500. Starting simulation... -switching cpus -info: Entering event queue @ 3123310685500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3124310685500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3125310685500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3126310685500. Starting simulation... -switching cpus -info: Entering event queue @ 3127310557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3128310557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3129310557500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3130310557500. Starting simulation... -switching cpus -info: Entering event queue @ 3131310429500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3132310429500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3133310429500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3134310429500. Starting simulation... -switching cpus -info: Entering event queue @ 3135310301500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3136310301500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3137310301500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3138310301500. Starting simulation... -switching cpus -info: Entering event queue @ 3139310173500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3140310173500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3141310173500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3142310173500. Starting simulation... -switching cpus -info: Entering event queue @ 3143310045500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3144310045500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3145310045500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3146310045500. Starting simulation... -switching cpus -info: Entering event queue @ 3147309917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3148309917500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3149309917500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3150309917500. Starting simulation... -switching cpus -info: Entering event queue @ 3151309789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3152309789500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3153309789500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3154309789500. Starting simulation... -switching cpus -info: Entering event queue @ 3155309661500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3156309661500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3157309661500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3158309661500. Starting simulation... -switching cpus -info: Entering event queue @ 3159309533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3160309533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3161309533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3162309533500. Starting simulation... -switching cpus -info: Entering event queue @ 3163309405500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3164309405500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3165309405500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3166309405500. Starting simulation... -switching cpus -info: Entering event queue @ 3167309277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3168309277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3169309277500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3170309277500. Starting simulation... -switching cpus -info: Entering event queue @ 3171309149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3172309149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3173309149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3174309149500. Starting simulation... -switching cpus -info: Entering event queue @ 3175309021500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3176309021500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3177309021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3178309021500. Starting simulation... -switching cpus -info: Entering event queue @ 3179308893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3180308893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3181308893500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3182308893500. Starting simulation... -switching cpus -info: Entering event queue @ 3183308765500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3184308765500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3185308765500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3186308765500. Starting simulation... -switching cpus -info: Entering event queue @ 3187308637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3188308637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3189308637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3190308637500. Starting simulation... -switching cpus -info: Entering event queue @ 3191308509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3192308509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3193308509500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3194308509500. Starting simulation... -switching cpus -info: Entering event queue @ 3195308381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3196308381500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3197308381500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3198308381500. Starting simulation... -switching cpus -info: Entering event queue @ 3199308253500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3200308253500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3201308253500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3202308253500. Starting simulation... -switching cpus -info: Entering event queue @ 3203308125500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3204308125500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3205308125500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3206308125500. Starting simulation... -switching cpus -info: Entering event queue @ 3207307997500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3208307997500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3209307997500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3210307997500. Starting simulation... -switching cpus -info: Entering event queue @ 3211307869500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3212307869500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3213307869500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3214307869500. Starting simulation... -switching cpus -info: Entering event queue @ 3215307741500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3216307741500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3217307741500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3218307741500. Starting simulation... -switching cpus -info: Entering event queue @ 3219307613500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3220307613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3221307613500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3222307613500. Starting simulation... -switching cpus -info: Entering event queue @ 3223307485500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3224307485500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3225307485500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3226307485500. Starting simulation... -switching cpus -info: Entering event queue @ 3227307357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3228307357500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3229307357500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3230307357500. Starting simulation... -switching cpus -info: Entering event queue @ 3231307229500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3232307229500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3233307229500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3234307229500. Starting simulation... -switching cpus -info: Entering event queue @ 3235307101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3236307101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3237307101500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3238307101500. Starting simulation... -switching cpus -info: Entering event queue @ 3239306973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 3240306973500. Starting simulation... -switching cpus -info: Entering event queue @ 3240306974000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 3241306974000. Starting simulation... -info: Entering event queue @ 3241306981500. Starting simulation... -switching cpus -info: Entering event queue @ 3241306982500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3242306982500. Starting simulation... -switching cpus -info: Entering event queue @ 3242306992000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3243306992000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 3244306992000. Starting simulation... -switching cpus -info: Entering event queue @ 3244306999500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3245306999500. Starting simulation... -switching cpus -info: Entering event queue @ 3245307007000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3246307007000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 3247307007000. Starting simulation... -info: Entering event queue @ 3247307019000. Starting simulation... -switching cpus -info: Entering event queue @ 3247307021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3248307021500. Starting simulation... -switching cpus -info: Entering event queue @ 3248307029000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 3249307029000. Starting simulation... -switching cpus -info: Entering event queue @ 3249307029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 3250307029500. Starting simulation... -switching cpus -info: Entering event queue @ 3250307030000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3251307030000. Starting simulation... -switching cpus -info: Entering event queue @ 3251307037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3252307037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3253307037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3254307037500. Starting simulation... -switching cpus -info: Entering event queue @ 3255306461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3256306461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3257306461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3258306461500. Starting simulation... -switching cpus -info: Entering event queue @ 3259306333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3260306333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3261306333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3262306333500. Starting simulation... -switching cpus -info: Entering event queue @ 3263306205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3264306205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3265306205500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3266306205500. Starting simulation... -switching cpus -info: Entering event queue @ 3267306077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3268306077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3269306077500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3270306077500. Starting simulation... -switching cpus -info: Entering event queue @ 3271305949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3272305949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3273305949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3274305949500. Starting simulation... -switching cpus -info: Entering event queue @ 3275305821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3276305821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3277305821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3278305821500. Starting simulation... -switching cpus -info: Entering event queue @ 3279305693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3280305693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3281305693500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3282305693500. Starting simulation... -switching cpus -info: Entering event queue @ 3283305565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3284305565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3285305565500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3286305565500. Starting simulation... -switching cpus -info: Entering event queue @ 3287305437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3288305437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3289305437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3290305437500. Starting simulation... -switching cpus -info: Entering event queue @ 3291305309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3292305309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3293305309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3294305309500. Starting simulation... -switching cpus -info: Entering event queue @ 3295305181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3296305181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3297305181500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3298305181500. Starting simulation... -switching cpus -info: Entering event queue @ 3299305053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3300305053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3301305053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3302305053500. Starting simulation... -switching cpus -info: Entering event queue @ 3303304925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3304304925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3305304925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3306304925500. Starting simulation... -switching cpus -info: Entering event queue @ 3307304797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3308304797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3309304797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3310304797500. Starting simulation... -switching cpus -info: Entering event queue @ 3311304669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3312304669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3313304669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3314304669500. Starting simulation... -switching cpus -info: Entering event queue @ 3315304541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3316304541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3317304541500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3318304541500. Starting simulation... -switching cpus -info: Entering event queue @ 3319304413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3320304413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3321304413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3322304413500. Starting simulation... -switching cpus -info: Entering event queue @ 3323304285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3324304285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3325304285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3326304285500. Starting simulation... -switching cpus -info: Entering event queue @ 3327304157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3328304157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3329304157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3330304157500. Starting simulation... -switching cpus -info: Entering event queue @ 3331304029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3332304029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3333304029500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3334304029500. Starting simulation... -switching cpus -info: Entering event queue @ 3335303901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3336303901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3337303901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3338303901500. Starting simulation... -switching cpus -info: Entering event queue @ 3339303773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3340303773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3341303773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3342303773500. Starting simulation... -switching cpus -info: Entering event queue @ 3343303645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3344303645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3345303645500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3346303645500. Starting simulation... -switching cpus -info: Entering event queue @ 3347303517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3348303517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3349303517500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3350303517500. Starting simulation... -switching cpus -info: Entering event queue @ 3351303389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3352303389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3353303389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3354303389500. Starting simulation... -switching cpus -info: Entering event queue @ 3355303261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3356303261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3357303261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3358303261500. Starting simulation... -switching cpus -info: Entering event queue @ 3359303133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3360303133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3361303133500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3362303133500. Starting simulation... -switching cpus -info: Entering event queue @ 3363303005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3364303005500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3365303005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3366303005500. Starting simulation... -switching cpus -info: Entering event queue @ 3367302877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3368302877500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3369302877500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3370302877500. Starting simulation... -switching cpus -info: Entering event queue @ 3371302749500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3372302749500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3373302749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3374302749500. Starting simulation... -switching cpus -info: Entering event queue @ 3375302621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3376302621500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3377302621500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3378302621500. Starting simulation... -switching cpus -info: Entering event queue @ 3379302493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3380302493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3381302493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3382302493500. Starting simulation... -switching cpus -info: Entering event queue @ 3383302365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3384302365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3385302365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3386302365500. Starting simulation... -switching cpus -info: Entering event queue @ 3387302237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3388302237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3389302237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3390302237500. Starting simulation... -switching cpus -info: Entering event queue @ 3391302109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3392302109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3393302109500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3394302109500. Starting simulation... -switching cpus -info: Entering event queue @ 3395301981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3396301981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3397301981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3398301981500. Starting simulation... -switching cpus -info: Entering event queue @ 3399301853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3400301853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3401301853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3402301853500. Starting simulation... -switching cpus -info: Entering event queue @ 3403301725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3404301725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3405301725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3406301725500. Starting simulation... -switching cpus -info: Entering event queue @ 3407301597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3408301597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3409301597500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3410301597500. Starting simulation... -switching cpus -info: Entering event queue @ 3411301469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3412301469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3413301469500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3414301469500. Starting simulation... -switching cpus -info: Entering event queue @ 3415301341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3416301341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3417301341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3418301341500. Starting simulation... -switching cpus -info: Entering event queue @ 3419301213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3420301213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3421301213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3422301213500. Starting simulation... -switching cpus -info: Entering event queue @ 3423301085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3424301085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3425301085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3426301085500. Starting simulation... -switching cpus -info: Entering event queue @ 3427300957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3428300957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3429300957500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3430300957500. Starting simulation... -switching cpus -info: Entering event queue @ 3431300829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3432300829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3433300829500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3434300829500. Starting simulation... -switching cpus -info: Entering event queue @ 3435300701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3436300701500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3437300701500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3438300701500. Starting simulation... -switching cpus -info: Entering event queue @ 3439300573500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3440300573500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3441300573500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3442300573500. Starting simulation... -switching cpus -info: Entering event queue @ 3443300445500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3444300445500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3445300445500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3446300445500. Starting simulation... -switching cpus -info: Entering event queue @ 3447300317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3448300317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3449300317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3450300317500. Starting simulation... -switching cpus -info: Entering event queue @ 3451300189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3452300189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3453300189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3454300189500. Starting simulation... -switching cpus -info: Entering event queue @ 3455300061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3456300061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3457300061500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3458300061500. Starting simulation... -switching cpus -info: Entering event queue @ 3459299933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3460299933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3461299933500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3462299933500. Starting simulation... -switching cpus -info: Entering event queue @ 3463299805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3464299805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3465299805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3466299805500. Starting simulation... -switching cpus -info: Entering event queue @ 3467299677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3468299677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3469299677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3470299677500. Starting simulation... -switching cpus -info: Entering event queue @ 3471299549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3472299549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3473299549500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3474299549500. Starting simulation... -switching cpus -info: Entering event queue @ 3475299421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3476299421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3477299421500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3478299421500. Starting simulation... -switching cpus -info: Entering event queue @ 3479299293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3480299293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3481299293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3482299293500. Starting simulation... -switching cpus -info: Entering event queue @ 3483299165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3484299165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3485299165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3486299165500. Starting simulation... -switching cpus -info: Entering event queue @ 3487299037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3488299037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3489299037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3490299037500. Starting simulation... -switching cpus -info: Entering event queue @ 3491298909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3492298909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3493298909500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3494298909500. Starting simulation... -switching cpus -info: Entering event queue @ 3495298781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3496298781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3497298781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3498298781500. Starting simulation... -switching cpus -info: Entering event queue @ 3499298653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3500298653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3501298653500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3502298653500. Starting simulation... -switching cpus -info: Entering event queue @ 3503298525500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3504298525500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3505298525500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3506298525500. Starting simulation... -switching cpus -info: Entering event queue @ 3507298397500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3508298397500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3509298397500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3510298397500. Starting simulation... -switching cpus -info: Entering event queue @ 3511298269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3512298269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3513298269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3514298269500. Starting simulation... -switching cpus -info: Entering event queue @ 3515298141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3516298141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3517298141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3518298141500. Starting simulation... -switching cpus -info: Entering event queue @ 3519298013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3520298013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3521298013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3522298013500. Starting simulation... -switching cpus -info: Entering event queue @ 3523297885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3524297885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3525297885500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3526297885500. Starting simulation... -switching cpus -info: Entering event queue @ 3527297757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3528297757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3529297757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3530297757500. Starting simulation... -switching cpus -info: Entering event queue @ 3531297629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3532297629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3533297629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3534297629500. Starting simulation... -switching cpus -info: Entering event queue @ 3535297501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3536297501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3537297501500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3538297501500. Starting simulation... -switching cpus -info: Entering event queue @ 3539297373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3540297373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3541297373500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3542297373500. Starting simulation... -switching cpus -info: Entering event queue @ 3543297245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3544297245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3545297245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3546297245500. Starting simulation... -switching cpus -info: Entering event queue @ 3547297117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3548297117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3549297117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3550297117500. Starting simulation... -switching cpus -info: Entering event queue @ 3551296989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3552296989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3553296989500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3554296989500. Starting simulation... -switching cpus -info: Entering event queue @ 3555296861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3556296861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3557296861500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3558296861500. Starting simulation... -switching cpus -info: Entering event queue @ 3559296733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3560296733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3561296733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3562296733500. Starting simulation... -switching cpus -info: Entering event queue @ 3563296605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3564296605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3565296605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3566296605500. Starting simulation... -switching cpus -info: Entering event queue @ 3567296477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3568296477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3569296477500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3570296477500. Starting simulation... -switching cpus -info: Entering event queue @ 3571296349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3572296349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3573296349500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3574296349500. Starting simulation... -switching cpus -info: Entering event queue @ 3575296221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3576296221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3577296221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3578296221500. Starting simulation... -switching cpus -info: Entering event queue @ 3579296093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3580296093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3581296093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3582296093500. Starting simulation... -switching cpus -info: Entering event queue @ 3583295965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3584295965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3585295965500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3586295965500. Starting simulation... -switching cpus -info: Entering event queue @ 3587295837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3588295837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3589295837500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3590295837500. Starting simulation... -switching cpus -info: Entering event queue @ 3591295709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3592295709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3593295709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3594295709500. Starting simulation... -switching cpus -info: Entering event queue @ 3595295581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3596295581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3597295581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3598295581500. Starting simulation... -switching cpus -info: Entering event queue @ 3599295453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3600295453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3601295453500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3602295453500. Starting simulation... -switching cpus -info: Entering event queue @ 3603295325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3604295325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3605295325500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3606295325500. Starting simulation... -switching cpus -info: Entering event queue @ 3607295197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3608295197500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3609295197500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3610295197500. Starting simulation... -switching cpus -info: Entering event queue @ 3611295069500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3612295069500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3613295069500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3614295069500. Starting simulation... -switching cpus -info: Entering event queue @ 3615294941500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3616294941500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3617294941500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3618294941500. Starting simulation... -switching cpus -info: Entering event queue @ 3619294813500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3620294813500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3621294813500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3622294813500. Starting simulation... -switching cpus -info: Entering event queue @ 3623294685500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3624294685500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3625294685500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3626294685500. Starting simulation... -switching cpus -info: Entering event queue @ 3627294557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3628294557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3629294557500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3630294557500. Starting simulation... -switching cpus -info: Entering event queue @ 3631294429500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3632294429500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3633294429500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3634294429500. Starting simulation... -switching cpus -info: Entering event queue @ 3635294301500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3636294301500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3637294301500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3638294301500. Starting simulation... -switching cpus -info: Entering event queue @ 3639294173500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3640294173500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3641294173500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3642294173500. Starting simulation... -switching cpus -info: Entering event queue @ 3643294045500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3644294045500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3645294045500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3646294045500. Starting simulation... -switching cpus -info: Entering event queue @ 3647293917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3648293917500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3649293917500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3650293917500. Starting simulation... -switching cpus -info: Entering event queue @ 3651293789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3652293789500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3653293789500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3654293789500. Starting simulation... -switching cpus -info: Entering event queue @ 3655293661500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3656293661500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3657293661500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3658293661500. Starting simulation... -switching cpus -info: Entering event queue @ 3659293533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3660293533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3661293533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3662293533500. Starting simulation... -switching cpus -info: Entering event queue @ 3663293405500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3664293405500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3665293405500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3666293405500. Starting simulation... -switching cpus -info: Entering event queue @ 3667293277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3668293277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3669293277500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3670293277500. Starting simulation... -switching cpus -info: Entering event queue @ 3671293149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3672293149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3673293149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3674293149500. Starting simulation... -switching cpus -info: Entering event queue @ 3675293021500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3676293021500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3677293021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3678293021500. Starting simulation... -switching cpus -info: Entering event queue @ 3679292893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3680292893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3681292893500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3682292893500. Starting simulation... -switching cpus -info: Entering event queue @ 3683292765500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3684292765500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3685292765500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3686292765500. Starting simulation... -switching cpus -info: Entering event queue @ 3687292637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3688292637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3689292637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3690292637500. Starting simulation... -switching cpus -info: Entering event queue @ 3691292509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3692292509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3693292509500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3694292509500. Starting simulation... -switching cpus -info: Entering event queue @ 3695292381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3696292381500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3697292381500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3698292381500. Starting simulation... -switching cpus -info: Entering event queue @ 3699292253500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3700292253500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3701292253500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3702292253500. Starting simulation... -switching cpus -info: Entering event queue @ 3703292125500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3704292125500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3705292125500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3706292125500. Starting simulation... -switching cpus -info: Entering event queue @ 3707291997500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3708291997500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3709291997500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3710291997500. Starting simulation... -switching cpus -info: Entering event queue @ 3711291869500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3712291869500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3713291869500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3714291869500. Starting simulation... -switching cpus -info: Entering event queue @ 3715291741500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3716291741500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3717291741500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3718291741500. Starting simulation... -switching cpus -info: Entering event queue @ 3719291613500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3720291613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3721291613500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3722291613500. Starting simulation... -switching cpus -info: Entering event queue @ 3723291485500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3724291485500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3725291485500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3726291485500. Starting simulation... -switching cpus -info: Entering event queue @ 3727291357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3728291357500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3729291357500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3730291357500. Starting simulation... -switching cpus -info: Entering event queue @ 3731291229500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3732291229500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3733291229500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3734291229500. Starting simulation... -switching cpus -info: Entering event queue @ 3735291101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3736291101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3737291101500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3738291101500. Starting simulation... -switching cpus -info: Entering event queue @ 3739290973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3740290973500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3741290973500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3742290973500. Starting simulation... -switching cpus -info: Entering event queue @ 3743290845500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3744290845500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3745290845500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3746290845500. Starting simulation... -switching cpus -info: Entering event queue @ 3747290717500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3748290717500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3749290717500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3750290717500. Starting simulation... -switching cpus -info: Entering event queue @ 3751290589500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3752290589500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3753290589500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3754290589500. Starting simulation... -switching cpus -info: Entering event queue @ 3755290461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3756290461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3757290461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3758290461500. Starting simulation... -switching cpus -info: Entering event queue @ 3759290333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3760290333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3761290333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3762290333500. Starting simulation... -switching cpus -info: Entering event queue @ 3763290205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3764290205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3765290205500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3766290205500. Starting simulation... -switching cpus -info: Entering event queue @ 3767290077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3768290077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3769290077500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3770290077500. Starting simulation... -switching cpus -info: Entering event queue @ 3771289949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3772289949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3773289949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3774289949500. Starting simulation... -switching cpus -info: Entering event queue @ 3775289821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3776289821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3777289821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3778289821500. Starting simulation... -switching cpus -info: Entering event queue @ 3779289693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3780289693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3781289693500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3782289693500. Starting simulation... -switching cpus -info: Entering event queue @ 3783289565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3784289565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3785289565500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3786289565500. Starting simulation... -switching cpus -info: Entering event queue @ 3787289437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3788289437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3789289437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3790289437500. Starting simulation... -switching cpus -info: Entering event queue @ 3791289309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3792289309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3793289309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3794289309500. Starting simulation... -switching cpus -info: Entering event queue @ 3795289181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3796289181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3797289181500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3798289181500. Starting simulation... -switching cpus -info: Entering event queue @ 3799289053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3800289053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3801289053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3802289053500. Starting simulation... -switching cpus -info: Entering event queue @ 3803288925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3804288925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3805288925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3806288925500. Starting simulation... -switching cpus -info: Entering event queue @ 3807288797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3808288797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3809288797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3810288797500. Starting simulation... -switching cpus -info: Entering event queue @ 3811288669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3812288669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3813288669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3814288669500. Starting simulation... -switching cpus -info: Entering event queue @ 3815288541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3816288541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3817288541500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3818288541500. Starting simulation... -switching cpus -info: Entering event queue @ 3819288413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3820288413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3821288413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3822288413500. Starting simulation... -switching cpus -info: Entering event queue @ 3823288285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3824288285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3825288285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3826288285500. Starting simulation... -switching cpus -info: Entering event queue @ 3827288157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3828288157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3829288157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3830288157500. Starting simulation... -switching cpus -info: Entering event queue @ 3831288029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3832288029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3833288029500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3834288029500. Starting simulation... -switching cpus -info: Entering event queue @ 3835287901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3836287901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3837287901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3838287901500. Starting simulation... -switching cpus -info: Entering event queue @ 3839287773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3840287773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3841287773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3842287773500. Starting simulation... -switching cpus -info: Entering event queue @ 3843287645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3844287645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3845287645500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3846287645500. Starting simulation... -switching cpus -info: Entering event queue @ 3847287517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3848287517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3849287517500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3850287517500. Starting simulation... -switching cpus -info: Entering event queue @ 3851287389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3852287389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3853287389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3854287389500. Starting simulation... -switching cpus -info: Entering event queue @ 3855287261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3856287261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3857287261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3858287261500. Starting simulation... -switching cpus -info: Entering event queue @ 3859287133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3860287133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3861287133500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3862287133500. Starting simulation... -switching cpus -info: Entering event queue @ 3863287005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 3864287005500. Starting simulation... -switching cpus -info: Entering event queue @ 3864287006000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 3865287006000. Starting simulation... -switching cpus -info: Entering event queue @ 3865287013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3866287013500. Starting simulation... -switching cpus -info: Entering event queue @ 3866287017500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3867287017500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 3868287017500. Starting simulation... -switching cpus -info: Entering event queue @ 3868287018500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3869287018500. Starting simulation... -switching cpus -info: Entering event queue @ 3869287022500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 3870287022500. Starting simulation... -switching cpus -info: Entering event queue @ 3870287023500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 3871287023500. Starting simulation... -switching cpus -info: Entering event queue @ 3871287024000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3872287024000. Starting simulation... -switching cpus -info: Entering event queue @ 3872287031500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 3873287031500. Starting simulation... -switching cpus -info: Entering event queue @ 3873287032500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3874287032500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3875287032500. Starting simulation... -info: Entering event queue @ 3875287061250. Starting simulation... -switching cpus -info: Entering event queue @ 3875287068750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3876287068750. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3877287068750. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3878287068750. Starting simulation... -switching cpus -info: Entering event queue @ 3879286493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3880286493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3881286493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3882286493500. Starting simulation... -switching cpus -info: Entering event queue @ 3883286365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3884286365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3885286365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3886286365500. Starting simulation... -switching cpus -info: Entering event queue @ 3887286237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3888286237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3889286237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3890286237500. Starting simulation... -switching cpus -info: Entering event queue @ 3891286109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3892286109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3893286109500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3894286109500. Starting simulation... -switching cpus -info: Entering event queue @ 3895285981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3896285981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3897285981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3898285981500. Starting simulation... -switching cpus -info: Entering event queue @ 3899285853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3900285853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3901285853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3902285853500. Starting simulation... -switching cpus -info: Entering event queue @ 3903285725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3904285725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3905285725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3906285725500. Starting simulation... -switching cpus -info: Entering event queue @ 3907285597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3908285597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3909285597500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3910285597500. Starting simulation... -switching cpus -info: Entering event queue @ 3911285469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3912285469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3913285469500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3914285469500. Starting simulation... -switching cpus -info: Entering event queue @ 3915285341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3916285341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3917285341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3918285341500. Starting simulation... -switching cpus -info: Entering event queue @ 3919285213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3920285213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3921285213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3922285213500. Starting simulation... -switching cpus -info: Entering event queue @ 3923285085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3924285085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3925285085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3926285085500. Starting simulation... -switching cpus -info: Entering event queue @ 3927284957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3928284957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3929284957500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3930284957500. Starting simulation... -switching cpus -info: Entering event queue @ 3931284829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3932284829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3933284829500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3934284829500. Starting simulation... -switching cpus -info: Entering event queue @ 3935284701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3936284701500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3937284701500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3938284701500. Starting simulation... -switching cpus -info: Entering event queue @ 3939284573500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3940284573500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3941284573500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3942284573500. Starting simulation... -switching cpus -info: Entering event queue @ 3943284445500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3944284445500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3945284445500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3946284445500. Starting simulation... -switching cpus -info: Entering event queue @ 3947284317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3948284317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3949284317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3950284317500. Starting simulation... -switching cpus -info: Entering event queue @ 3951284189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3952284189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3953284189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3954284189500. Starting simulation... -switching cpus -info: Entering event queue @ 3955284061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3956284061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3957284061500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3958284061500. Starting simulation... -switching cpus -info: Entering event queue @ 3959283933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3960283933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3961283933500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3962283933500. Starting simulation... -switching cpus -info: Entering event queue @ 3963283805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3964283805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3965283805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3966283805500. Starting simulation... -switching cpus -info: Entering event queue @ 3967283677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3968283677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3969283677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3970283677500. Starting simulation... -switching cpus -info: Entering event queue @ 3971283549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3972283549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3973283549500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3974283549500. Starting simulation... -switching cpus -info: Entering event queue @ 3975283421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3976283421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3977283421500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3978283421500. Starting simulation... -switching cpus -info: Entering event queue @ 3979283293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3980283293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3981283293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3982283293500. Starting simulation... -switching cpus -info: Entering event queue @ 3983283165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3984283165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3985283165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3986283165500. Starting simulation... -switching cpus -info: Entering event queue @ 3987283037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3988283037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3989283037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3990283037500. Starting simulation... -switching cpus -info: Entering event queue @ 3991282909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3992282909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3993282909500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3994282909500. Starting simulation... -switching cpus -info: Entering event queue @ 3995282781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 3996282781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 3997282781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 3998282781500. Starting simulation... -switching cpus -info: Entering event queue @ 3999282653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4000282653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4001282653500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4002282653500. Starting simulation... -switching cpus -info: Entering event queue @ 4003282525500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4004282525500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4005282525500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4006282525500. Starting simulation... -switching cpus -info: Entering event queue @ 4007282397500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4008282397500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4009282397500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4010282397500. Starting simulation... -switching cpus -info: Entering event queue @ 4011282269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4012282269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4013282269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4014282269500. Starting simulation... -switching cpus -info: Entering event queue @ 4015282141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4016282141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4017282141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4018282141500. Starting simulation... -switching cpus -info: Entering event queue @ 4019282013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4020282013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4021282013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4022282013500. Starting simulation... -switching cpus -info: Entering event queue @ 4023281885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4024281885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4025281885500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4026281885500. Starting simulation... -switching cpus -info: Entering event queue @ 4027281757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4028281757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4029281757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4030281757500. Starting simulation... -switching cpus -info: Entering event queue @ 4031281629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4032281629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4033281629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4034281629500. Starting simulation... -switching cpus -info: Entering event queue @ 4035281501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4036281501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4037281501500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4038281501500. Starting simulation... -switching cpus -info: Entering event queue @ 4039281373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4040281373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4041281373500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4042281373500. Starting simulation... -switching cpus -info: Entering event queue @ 4043281245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4044281245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4045281245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4046281245500. Starting simulation... -switching cpus -info: Entering event queue @ 4047281117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4048281117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4049281117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4050281117500. Starting simulation... -switching cpus -info: Entering event queue @ 4051280989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4052280989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4053280989500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4054280989500. Starting simulation... -switching cpus -info: Entering event queue @ 4055280861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4056280861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4057280861500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4058280861500. Starting simulation... -switching cpus -info: Entering event queue @ 4059280733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4060280733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4061280733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4062280733500. Starting simulation... -switching cpus -info: Entering event queue @ 4063280605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4064280605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4065280605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4066280605500. Starting simulation... -switching cpus -info: Entering event queue @ 4067280477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4068280477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4069280477500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4070280477500. Starting simulation... -switching cpus -info: Entering event queue @ 4071280349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4072280349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4073280349500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4074280349500. Starting simulation... -switching cpus -info: Entering event queue @ 4075280221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4076280221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4077280221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4078280221500. Starting simulation... -switching cpus -info: Entering event queue @ 4079280093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4080280093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4081280093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4082280093500. Starting simulation... -switching cpus -info: Entering event queue @ 4083279965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4084279965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4085279965500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4086279965500. Starting simulation... -switching cpus -info: Entering event queue @ 4087279837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4088279837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4089279837500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4090279837500. Starting simulation... -switching cpus -info: Entering event queue @ 4091279709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4092279709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4093279709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4094279709500. Starting simulation... -switching cpus -info: Entering event queue @ 4095279581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4096279581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4097279581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4098279581500. Starting simulation... -switching cpus -info: Entering event queue @ 4099279453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4100279453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4101279453500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4102279453500. Starting simulation... -switching cpus -info: Entering event queue @ 4103279325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4104279325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4105279325500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4106279325500. Starting simulation... -switching cpus -info: Entering event queue @ 4107279197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4108279197500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4109279197500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4110279197500. Starting simulation... -switching cpus -info: Entering event queue @ 4111279069500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4112279069500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4113279069500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4114279069500. Starting simulation... -switching cpus -info: Entering event queue @ 4115278941500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4116278941500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4117278941500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4118278941500. Starting simulation... -switching cpus -info: Entering event queue @ 4119278813500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4120278813500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4121278813500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4122278813500. Starting simulation... -switching cpus -info: Entering event queue @ 4123278685500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4124278685500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4125278685500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4126278685500. Starting simulation... -switching cpus -info: Entering event queue @ 4127278557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4128278557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4129278557500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4130278557500. Starting simulation... -switching cpus -info: Entering event queue @ 4131278429500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4132278429500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4133278429500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4134278429500. Starting simulation... -switching cpus -info: Entering event queue @ 4135278301500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4136278301500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4137278301500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4138278301500. Starting simulation... -switching cpus -info: Entering event queue @ 4139278173500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4140278173500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4141278173500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4142278173500. Starting simulation... -switching cpus -info: Entering event queue @ 4143278045500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4144278045500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4145278045500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4146278045500. Starting simulation... -switching cpus -info: Entering event queue @ 4147277917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4148277917500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4149277917500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4150277917500. Starting simulation... -switching cpus -info: Entering event queue @ 4151277789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4152277789500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4153277789500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4154277789500. Starting simulation... -switching cpus -info: Entering event queue @ 4155277661500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4156277661500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4157277661500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4158277661500. Starting simulation... -switching cpus -info: Entering event queue @ 4159277533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4160277533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4161277533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4162277533500. Starting simulation... -switching cpus -info: Entering event queue @ 4163277405500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4164277405500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4165277405500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4166277405500. Starting simulation... -switching cpus -info: Entering event queue @ 4167277277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4168277277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4169277277500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4170277277500. Starting simulation... -switching cpus -info: Entering event queue @ 4171277149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4172277149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4173277149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4174277149500. Starting simulation... -switching cpus -info: Entering event queue @ 4175277021500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4176277021500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4177277021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4178277021500. Starting simulation... -switching cpus -info: Entering event queue @ 4179276893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4180276893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4181276893500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4182276893500. Starting simulation... -switching cpus -info: Entering event queue @ 4183276765500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4184276765500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4185276765500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4186276765500. Starting simulation... -switching cpus -info: Entering event queue @ 4187276637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4188276637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4189276637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4190276637500. Starting simulation... -switching cpus -info: Entering event queue @ 4191276509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4192276509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4193276509500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4194276509500. Starting simulation... -switching cpus -info: Entering event queue @ 4195276381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4196276381500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4197276381500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4198276381500. Starting simulation... -switching cpus -info: Entering event queue @ 4199276253500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4200276253500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4201276253500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4202276253500. Starting simulation... -switching cpus -info: Entering event queue @ 4203276125500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4204276125500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4205276125500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4206276125500. Starting simulation... -switching cpus -info: Entering event queue @ 4207275997500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4208275997500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4209275997500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4210275997500. Starting simulation... -switching cpus -info: Entering event queue @ 4211275869500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4212275869500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4213275869500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4214275869500. Starting simulation... -switching cpus -info: Entering event queue @ 4215275741500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4216275741500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4217275741500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4218275741500. Starting simulation... -switching cpus -info: Entering event queue @ 4219275613500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4220275613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4221275613500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4222275613500. Starting simulation... -switching cpus -info: Entering event queue @ 4223275485500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4224275485500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4225275485500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4226275485500. Starting simulation... -switching cpus -info: Entering event queue @ 4227275357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4228275357500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4229275357500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4230275357500. Starting simulation... -switching cpus -info: Entering event queue @ 4231275229500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4232275229500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4233275229500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4234275229500. Starting simulation... -switching cpus -info: Entering event queue @ 4235275101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4236275101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4237275101500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4238275101500. Starting simulation... -switching cpus -info: Entering event queue @ 4239274973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4240274973500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4241274973500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4242274973500. Starting simulation... -switching cpus -info: Entering event queue @ 4243274845500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4244274845500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4245274845500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4246274845500. Starting simulation... -switching cpus -info: Entering event queue @ 4247274717500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4248274717500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4249274717500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4250274717500. Starting simulation... -switching cpus -info: Entering event queue @ 4251274589500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4252274589500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4253274589500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4254274589500. Starting simulation... -switching cpus -info: Entering event queue @ 4255274461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4256274461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4257274461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4258274461500. Starting simulation... -switching cpus -info: Entering event queue @ 4259274333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4260274333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4261274333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4262274333500. Starting simulation... -switching cpus -info: Entering event queue @ 4263274205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4264274205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4265274205500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4266274205500. Starting simulation... -switching cpus -info: Entering event queue @ 4267274077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4268274077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4269274077500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4270274077500. Starting simulation... -switching cpus -info: Entering event queue @ 4271273949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4272273949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4273273949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4274273949500. Starting simulation... -switching cpus -info: Entering event queue @ 4275273821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4276273821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4277273821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4278273821500. Starting simulation... -switching cpus -info: Entering event queue @ 4279273693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4280273693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4281273693500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4282273693500. Starting simulation... -switching cpus -info: Entering event queue @ 4283273565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4284273565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4285273565500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4286273565500. Starting simulation... -switching cpus -info: Entering event queue @ 4287273437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4288273437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4289273437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4290273437500. Starting simulation... -switching cpus -info: Entering event queue @ 4291273309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4292273309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4293273309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4294273309500. Starting simulation... -switching cpus -info: Entering event queue @ 4295273181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4296273181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4297273181500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4298273181500. Starting simulation... -switching cpus -info: Entering event queue @ 4299273053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4300273053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4301273053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4302273053500. Starting simulation... -switching cpus -info: Entering event queue @ 4303272925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4304272925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4305272925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4306272925500. Starting simulation... -switching cpus -info: Entering event queue @ 4307272797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4308272797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4309272797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4310272797500. Starting simulation... -switching cpus -info: Entering event queue @ 4311272669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4312272669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4313272669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4314272669500. Starting simulation... -switching cpus -info: Entering event queue @ 4315272541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4316272541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4317272541500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4318272541500. Starting simulation... -switching cpus -info: Entering event queue @ 4319272413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4320272413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4321272413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4322272413500. Starting simulation... -switching cpus -info: Entering event queue @ 4323272285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4324272285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4325272285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4326272285500. Starting simulation... -switching cpus -info: Entering event queue @ 4327272157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4328272157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4329272157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4330272157500. Starting simulation... -switching cpus -info: Entering event queue @ 4331272029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4332272029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4333272029500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4334272029500. Starting simulation... -switching cpus -info: Entering event queue @ 4335271901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4336271901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4337271901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4338271901500. Starting simulation... -switching cpus -info: Entering event queue @ 4339271773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4340271773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4341271773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4342271773500. Starting simulation... -switching cpus -info: Entering event queue @ 4343271645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4344271645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4345271645500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4346271645500. Starting simulation... -switching cpus -info: Entering event queue @ 4347271517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4348271517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4349271517500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4350271517500. Starting simulation... -switching cpus -info: Entering event queue @ 4351271389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4352271389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4353271389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4354271389500. Starting simulation... -switching cpus -info: Entering event queue @ 4355271261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4356271261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4357271261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4358271261500. Starting simulation... -switching cpus -info: Entering event queue @ 4359271133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4360271133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4361271133500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4362271133500. Starting simulation... -switching cpus -info: Entering event queue @ 4363271005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4364271005500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4365271005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4366271005500. Starting simulation... -switching cpus -info: Entering event queue @ 4367270877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4368270877500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4369270877500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4370270877500. Starting simulation... -switching cpus -info: Entering event queue @ 4371270749500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4372270749500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4373270749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4374270749500. Starting simulation... -switching cpus -info: Entering event queue @ 4375270621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4376270621500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4377270621500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4378270621500. Starting simulation... -switching cpus -info: Entering event queue @ 4379270493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4380270493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4381270493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4382270493500. Starting simulation... -switching cpus -info: Entering event queue @ 4383270365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4384270365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4385270365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4386270365500. Starting simulation... -switching cpus -info: Entering event queue @ 4387270237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4388270237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4389270237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4390270237500. Starting simulation... -switching cpus -info: Entering event queue @ 4391270109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4392270109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4393270109500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4394270109500. Starting simulation... -switching cpus -info: Entering event queue @ 4395269981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4396269981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4397269981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4398269981500. Starting simulation... -switching cpus -info: Entering event queue @ 4399269853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4400269853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4401269853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4402269853500. Starting simulation... -switching cpus -info: Entering event queue @ 4403269725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4404269725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4405269725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4406269725500. Starting simulation... -switching cpus -info: Entering event queue @ 4407269597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4408269597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4409269597500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4410269597500. Starting simulation... -switching cpus -info: Entering event queue @ 4411269469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4412269469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4413269469500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4414269469500. Starting simulation... -switching cpus -info: Entering event queue @ 4415269341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4416269341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4417269341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4418269341500. Starting simulation... -switching cpus -info: Entering event queue @ 4419269213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4420269213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4421269213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4422269213500. Starting simulation... -switching cpus -info: Entering event queue @ 4423269085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4424269085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4425269085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4426269085500. Starting simulation... -switching cpus -info: Entering event queue @ 4427268957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4428268957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4429268957500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4430268957500. Starting simulation... -switching cpus -info: Entering event queue @ 4431268829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4432268829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 4433268829500. Starting simulation... -switching cpus -info: Entering event queue @ 4433268830000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4434268830000. Starting simulation... -switching cpus -info: Entering event queue @ 4434268834000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4435268834000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 4436268834000. Starting simulation... -switching cpus -info: Entering event queue @ 4436268835000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4437268835000. Starting simulation... -switching cpus -info: Entering event queue @ 4437268839000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4438268839000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 4439268839000. Starting simulation... -switching cpus -info: Entering event queue @ 4439268840500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4440268840500. Starting simulation... -switching cpus -info: Entering event queue @ 4440268844500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4441268844500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4442268844500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4443268844500. Starting simulation... -switching cpus -info: Entering event queue @ 4443268849000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4444268849000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4445268849000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4446268849000. Starting simulation... -switching cpus -info: Entering event queue @ 4447268317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4448268317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4449268317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4450268317500. Starting simulation... -switching cpus -info: Entering event queue @ 4451268189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4452268189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4453268189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4454268189500. Starting simulation... -switching cpus -info: Entering event queue @ 4455268061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4456268061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4457268061500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4458268061500. Starting simulation... -switching cpus -info: Entering event queue @ 4459267933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4460267933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4461267933500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4462267933500. Starting simulation... -switching cpus -info: Entering event queue @ 4463267805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4464267805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4465267805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4466267805500. Starting simulation... -switching cpus -info: Entering event queue @ 4467267677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4468267677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4469267677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4470267677500. Starting simulation... -switching cpus -info: Entering event queue @ 4471267549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4472267549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4473267549500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4474267549500. Starting simulation... -switching cpus -info: Entering event queue @ 4475267421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4476267421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4477267421500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4478267421500. Starting simulation... -switching cpus -info: Entering event queue @ 4479267293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4480267293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4481267293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4482267293500. Starting simulation... -switching cpus -info: Entering event queue @ 4483267165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4484267165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4485267165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4486267165500. Starting simulation... -switching cpus -info: Entering event queue @ 4487267037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4488267037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4489267037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4490267037500. Starting simulation... -switching cpus -info: Entering event queue @ 4491266909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4492266909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4493266909500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4494266909500. Starting simulation... -switching cpus -info: Entering event queue @ 4495266781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4496266781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4497266781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4498266781500. Starting simulation... -switching cpus -info: Entering event queue @ 4499266653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4500266653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4501266653500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4502266653500. Starting simulation... -switching cpus -info: Entering event queue @ 4503266525500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4504266525500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4505266525500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4506266525500. Starting simulation... -switching cpus -info: Entering event queue @ 4507266397500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4508266397500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4509266397500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4510266397500. Starting simulation... -switching cpus -info: Entering event queue @ 4511266269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4512266269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4513266269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4514266269500. Starting simulation... -switching cpus -info: Entering event queue @ 4515266141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4516266141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4517266141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4518266141500. Starting simulation... -switching cpus -info: Entering event queue @ 4519266013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4520266013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4521266013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4522266013500. Starting simulation... -switching cpus -info: Entering event queue @ 4523265885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4524265885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4525265885500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4526265885500. Starting simulation... -switching cpus -info: Entering event queue @ 4527265757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4528265757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4529265757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4530265757500. Starting simulation... -switching cpus -info: Entering event queue @ 4531265629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4532265629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4533265629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4534265629500. Starting simulation... -switching cpus -info: Entering event queue @ 4535265501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4536265501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4537265501500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4538265501500. Starting simulation... -switching cpus -info: Entering event queue @ 4539265373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4540265373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4541265373500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4542265373500. Starting simulation... -switching cpus -info: Entering event queue @ 4543265245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4544265245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4545265245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4546265245500. Starting simulation... -switching cpus -info: Entering event queue @ 4547265117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4548265117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4549265117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4550265117500. Starting simulation... -switching cpus -info: Entering event queue @ 4551264989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4552264989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4553264989500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4554264989500. Starting simulation... -switching cpus -info: Entering event queue @ 4555264861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4556264861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4557264861500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4558264861500. Starting simulation... -switching cpus -info: Entering event queue @ 4559264733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4560264733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4561264733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4562264733500. Starting simulation... -switching cpus -info: Entering event queue @ 4563264605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4564264605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4565264605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4566264605500. Starting simulation... -switching cpus -info: Entering event queue @ 4567264477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4568264477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4569264477500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4570264477500. Starting simulation... -switching cpus -info: Entering event queue @ 4571264349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4572264349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4573264349500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4574264349500. Starting simulation... -switching cpus -info: Entering event queue @ 4575264221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4576264221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4577264221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4578264221500. Starting simulation... -switching cpus -info: Entering event queue @ 4579264093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4580264093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4581264093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4582264093500. Starting simulation... -switching cpus -info: Entering event queue @ 4583263965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4584263965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4585263965500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4586263965500. Starting simulation... -switching cpus -info: Entering event queue @ 4587263837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4588263837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4589263837500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4590263837500. Starting simulation... -switching cpus -info: Entering event queue @ 4591263709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4592263709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4593263709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4594263709500. Starting simulation... -switching cpus -info: Entering event queue @ 4595263581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4596263581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4597263581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4598263581500. Starting simulation... -switching cpus -info: Entering event queue @ 4599263453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4600263453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4601263453500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4602263453500. Starting simulation... -switching cpus -info: Entering event queue @ 4603263325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4604263325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4605263325500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4606263325500. Starting simulation... -switching cpus -info: Entering event queue @ 4607263197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4608263197500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4609263197500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4610263197500. Starting simulation... -switching cpus -info: Entering event queue @ 4611263069500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4612263069500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4613263069500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4614263069500. Starting simulation... -switching cpus -info: Entering event queue @ 4615262941500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4616262941500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4617262941500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4618262941500. Starting simulation... -switching cpus -info: Entering event queue @ 4619262813500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4620262813500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4621262813500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4622262813500. Starting simulation... -switching cpus -info: Entering event queue @ 4623262685500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4624262685500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4625262685500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4626262685500. Starting simulation... -switching cpus -info: Entering event queue @ 4627262557500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4628262557500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4629262557500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4630262557500. Starting simulation... -switching cpus -info: Entering event queue @ 4631262429500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4632262429500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4633262429500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4634262429500. Starting simulation... -switching cpus -info: Entering event queue @ 4635262301500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4636262301500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4637262301500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4638262301500. Starting simulation... -switching cpus -info: Entering event queue @ 4639262173500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4640262173500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4641262173500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4642262173500. Starting simulation... -switching cpus -info: Entering event queue @ 4643262045500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4644262045500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4645262045500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4646262045500. Starting simulation... -switching cpus -info: Entering event queue @ 4647261917500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4648261917500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4649261917500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4650261917500. Starting simulation... -switching cpus -info: Entering event queue @ 4651261789500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4652261789500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4653261789500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4654261789500. Starting simulation... -switching cpus -info: Entering event queue @ 4655261661500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4656261661500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4657261661500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4658261661500. Starting simulation... -switching cpus -info: Entering event queue @ 4659261533500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4660261533500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4661261533500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4662261533500. Starting simulation... -switching cpus -info: Entering event queue @ 4663261405500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4664261405500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4665261405500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4666261405500. Starting simulation... -switching cpus -info: Entering event queue @ 4667261277500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4668261277500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4669261277500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4670261277500. Starting simulation... -switching cpus -info: Entering event queue @ 4671261149500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4672261149500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4673261149500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4674261149500. Starting simulation... -switching cpus -info: Entering event queue @ 4675261021500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4676261021500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4677261021500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4678261021500. Starting simulation... -switching cpus -info: Entering event queue @ 4679260893500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4680260893500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4681260893500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4682260893500. Starting simulation... -switching cpus -info: Entering event queue @ 4683260765500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4684260765500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4685260765500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4686260765500. Starting simulation... -switching cpus -info: Entering event queue @ 4687260637500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4688260637500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4689260637500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4690260637500. Starting simulation... -switching cpus -info: Entering event queue @ 4691260509500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4692260509500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4693260509500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4694260509500. Starting simulation... -switching cpus -info: Entering event queue @ 4695260381500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4696260381500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4697260381500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4698260381500. Starting simulation... -switching cpus -info: Entering event queue @ 4699260253500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4700260253500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4701260253500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4702260253500. Starting simulation... -switching cpus -info: Entering event queue @ 4703260125500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4704260125500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4705260125500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4706260125500. Starting simulation... -switching cpus -info: Entering event queue @ 4707259997500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4708259997500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4709259997500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4710259997500. Starting simulation... -switching cpus -info: Entering event queue @ 4711259869500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4712259869500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4713259869500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4714259869500. Starting simulation... -switching cpus -info: Entering event queue @ 4715259741500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4716259741500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4717259741500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4718259741500. Starting simulation... -switching cpus -info: Entering event queue @ 4719259613500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4720259613500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4721259613500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4722259613500. Starting simulation... -switching cpus -info: Entering event queue @ 4723259485500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4724259485500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4725259485500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4726259485500. Starting simulation... -switching cpus -info: Entering event queue @ 4727259357500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4728259357500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4729259357500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4730259357500. Starting simulation... -switching cpus -info: Entering event queue @ 4731259229500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4732259229500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4733259229500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4734259229500. Starting simulation... -switching cpus -info: Entering event queue @ 4735259101500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4736259101500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4737259101500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4738259101500. Starting simulation... -switching cpus -info: Entering event queue @ 4739258973500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4740258973500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4741258973500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4742258973500. Starting simulation... -switching cpus -info: Entering event queue @ 4743258845500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4744258845500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4745258845500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4746258845500. Starting simulation... -switching cpus -info: Entering event queue @ 4747258717500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4748258717500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4749258717500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4750258717500. Starting simulation... -switching cpus -info: Entering event queue @ 4751258589500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4752258589500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4753258589500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4754258589500. Starting simulation... -switching cpus -info: Entering event queue @ 4755258461500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4756258461500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4757258461500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4758258461500. Starting simulation... -switching cpus -info: Entering event queue @ 4759258333500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4760258333500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4761258333500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4762258333500. Starting simulation... -switching cpus -info: Entering event queue @ 4763258205500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4764258205500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4765258205500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4766258205500. Starting simulation... -switching cpus -info: Entering event queue @ 4767258077500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4768258077500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4769258077500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4770258077500. Starting simulation... -switching cpus -info: Entering event queue @ 4771257949500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4772257949500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4773257949500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4774257949500. Starting simulation... -switching cpus -info: Entering event queue @ 4775257821500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4776257821500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4777257821500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4778257821500. Starting simulation... -switching cpus -info: Entering event queue @ 4779257693500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4780257693500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4781257693500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4782257693500. Starting simulation... -switching cpus -info: Entering event queue @ 4783257565500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4784257565500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4785257565500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4786257565500. Starting simulation... -switching cpus -info: Entering event queue @ 4787257437500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4788257437500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4789257437500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4790257437500. Starting simulation... -switching cpus -info: Entering event queue @ 4791257309500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4792257309500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4793257309500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4794257309500. Starting simulation... -switching cpus -info: Entering event queue @ 4795257181500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4796257181500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4797257181500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4798257181500. Starting simulation... -switching cpus -info: Entering event queue @ 4799257053500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4800257053500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4801257053500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4802257053500. Starting simulation... -switching cpus -info: Entering event queue @ 4803256925500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4804256925500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4805256925500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4806256925500. Starting simulation... -switching cpus -info: Entering event queue @ 4807256797500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4808256797500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4809256797500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4810256797500. Starting simulation... -switching cpus -info: Entering event queue @ 4811256669500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4812256669500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4813256669500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4814256669500. Starting simulation... -switching cpus -info: Entering event queue @ 4815256541500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4816256541500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4817256541500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4818256541500. Starting simulation... -switching cpus -info: Entering event queue @ 4819256413500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4820256413500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4821256413500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4822256413500. Starting simulation... -switching cpus -info: Entering event queue @ 4823256285500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4824256285500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4825256285500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4826256285500. Starting simulation... -switching cpus -info: Entering event queue @ 4827256157500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4828256157500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4829256157500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4830256157500. Starting simulation... -switching cpus -info: Entering event queue @ 4831256029500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4832256029500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4833256029500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4834256029500. Starting simulation... -switching cpus -info: Entering event queue @ 4835255901500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4836255901500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4837255901500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4838255901500. Starting simulation... -switching cpus -info: Entering event queue @ 4839255773500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4840255773500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4841255773500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4842255773500. Starting simulation... -switching cpus -info: Entering event queue @ 4843255645500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4844255645500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4845255645500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4846255645500. Starting simulation... -switching cpus -info: Entering event queue @ 4847255517500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4848255517500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4849255517500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4850255517500. Starting simulation... -switching cpus -info: Entering event queue @ 4851255389500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4852255389500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4853255389500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4854255389500. Starting simulation... -switching cpus -info: Entering event queue @ 4855255261500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4856255261500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4857255261500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4858255261500. Starting simulation... -switching cpus -info: Entering event queue @ 4859255133500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4860255133500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4861255133500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4862255133500. Starting simulation... -switching cpus -info: Entering event queue @ 4863255005500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4864255005500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4865255005500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4866255005500. Starting simulation... -switching cpus -info: Entering event queue @ 4867254877500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4868254877500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4869254877500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4870254877500. Starting simulation... -switching cpus -info: Entering event queue @ 4871254749500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4872254749500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4873254749500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4874254749500. Starting simulation... -switching cpus -info: Entering event queue @ 4875254621500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4876254621500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4877254621500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4878254621500. Starting simulation... -switching cpus -info: Entering event queue @ 4879254493500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4880254493500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4881254493500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4882254493500. Starting simulation... -switching cpus -info: Entering event queue @ 4883254365500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4884254365500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4885254365500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4886254365500. Starting simulation... -switching cpus -info: Entering event queue @ 4887254237500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4888254237500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4889254237500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4890254237500. Starting simulation... -switching cpus -info: Entering event queue @ 4891254109500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4892254109500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4893254109500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4894254109500. Starting simulation... -switching cpus -info: Entering event queue @ 4895253981500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4896253981500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4897253981500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4898253981500. Starting simulation... -switching cpus -info: Entering event queue @ 4899253853500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4900253853500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4901253853500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4902253853500. Starting simulation... -switching cpus -info: Entering event queue @ 4903253725500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4904253725500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4905253725500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4906253725500. Starting simulation... -switching cpus -info: Entering event queue @ 4907253597500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4908253597500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4909253597500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4910253597500. Starting simulation... -switching cpus -info: Entering event queue @ 4911253469500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4912253469500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4913253469500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4914253469500. Starting simulation... -switching cpus -info: Entering event queue @ 4915253341500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4916253341500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4917253341500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4918253341500. Starting simulation... -switching cpus -info: Entering event queue @ 4919253213500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4920253213500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4921253213500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4922253213500. Starting simulation... -switching cpus -info: Entering event queue @ 4923253085500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4924253085500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4925253085500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4926253085500. Starting simulation... -switching cpus -info: Entering event queue @ 4927252957500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4928252957500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4929252957500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4930252957500. Starting simulation... -switching cpus -info: Entering event queue @ 4931252829500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4932252829500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4933252829500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4934252829500. Starting simulation... -switching cpus -info: Entering event queue @ 4935252701500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4936252701500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4937252701500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4938252701500. Starting simulation... -switching cpus -info: Entering event queue @ 4939252573500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4940252573500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4941252573500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4942252573500. Starting simulation... -switching cpus -info: Entering event queue @ 4943252445500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4944252445500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4945252445500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4946252445500. Starting simulation... -switching cpus -info: Entering event queue @ 4947252317500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4948252317500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4949252317500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4950252317500. Starting simulation... -switching cpus -info: Entering event queue @ 4951252189500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4952252189500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4953252189500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4954252189500. Starting simulation... -switching cpus -info: Entering event queue @ 4955252061500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4956252061500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4957252061500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4958252061500. Starting simulation... -switching cpus -info: Entering event queue @ 4959251933500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4960251933500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4961251933500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4962251933500. Starting simulation... -switching cpus -info: Entering event queue @ 4963251805500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4964251805500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4965251805500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4966251805500. Starting simulation... -switching cpus -info: Entering event queue @ 4967251677500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4968251677500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4969251677500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4970251677500. Starting simulation... -switching cpus -info: Entering event queue @ 4971251549500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4972251549500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4973251549500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4974251549500. Starting simulation... -switching cpus -info: Entering event queue @ 4975251421500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4976251421500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4977251421500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4978251421500. Starting simulation... -switching cpus -info: Entering event queue @ 4979251293500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4980251293500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4981251293500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4982251293500. Starting simulation... -switching cpus -info: Entering event queue @ 4983251165500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4984251165500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4985251165500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4986251165500. Starting simulation... -switching cpus -info: Entering event queue @ 4987251037500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4988251037500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4989251037500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4990251037500. Starting simulation... -switching cpus -info: Entering event queue @ 4991250909500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4992250909500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4993250909500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4994250909500. Starting simulation... -switching cpus -info: Entering event queue @ 4995250781500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 4996250781500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 4997250781500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 4998250781500. Starting simulation... -switching cpus -info: Entering event queue @ 4999250653500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5000250653500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5001250653500. Starting simulation... -switching cpus -info: Entering event queue @ 5001250661000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5002250661000. Starting simulation... -switching cpus -info: Entering event queue @ 5002250670500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 5003250670500. Starting simulation... -switching cpus -info: Entering event queue @ 5003250671000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5004250671000. Starting simulation... -switching cpus -info: Entering event queue @ 5004250678500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5005250678500. Starting simulation... -info: Entering event queue @ 5007250332500. Starting simulation... -info: Entering event queue @ 5007250333500. Starting simulation... -switching cpus -info: Entering event queue @ 5007250338000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5008250338000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5009250338000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5010250338000. Starting simulation... -switching cpus -info: Entering event queue @ 5011250269500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5012250269500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5013250269500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5014250269500. Starting simulation... -switching cpus -info: Entering event queue @ 5015250141500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5016250141500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5017250141500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5018250141500. Starting simulation... -switching cpus -info: Entering event queue @ 5019250013500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5020250013500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5021250013500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5022250013500. Starting simulation... -switching cpus -info: Entering event queue @ 5023249885500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5024249885500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5025249885500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5026249885500. Starting simulation... -switching cpus -info: Entering event queue @ 5027249757500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5028249757500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5029249757500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5030249757500. Starting simulation... -switching cpus -info: Entering event queue @ 5031249629500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5032249629500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5033249629500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5034249629500. Starting simulation... -switching cpus -info: Entering event queue @ 5035249501500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5036249501500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5037249501500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5038249501500. Starting simulation... -switching cpus -info: Entering event queue @ 5039249373500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5040249373500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5041249373500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5042249373500. Starting simulation... -switching cpus -info: Entering event queue @ 5043249245500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5044249245500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5045249245500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5046249245500. Starting simulation... -switching cpus -info: Entering event queue @ 5047249117500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5048249117500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5049249117500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5050249117500. Starting simulation... -switching cpus -info: Entering event queue @ 5051248989500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5052248989500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5053248989500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5054248989500. Starting simulation... -switching cpus -info: Entering event queue @ 5055248861500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5056248861500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5057248861500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5058248861500. Starting simulation... -switching cpus -info: Entering event queue @ 5059248733500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5060248733500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5061248733500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5062248733500. Starting simulation... -switching cpus -info: Entering event queue @ 5063248605500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5064248605500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5065248605500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5066248605500. Starting simulation... -switching cpus -info: Entering event queue @ 5067248477500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5068248477500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5069248477500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5070248477500. Starting simulation... -switching cpus -info: Entering event queue @ 5071248349500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5072248349500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5073248349500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5074248349500. Starting simulation... -switching cpus -info: Entering event queue @ 5075248221500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5076248221500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5077248221500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5078248221500. Starting simulation... -switching cpus -info: Entering event queue @ 5079248093500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5080248093500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5081248093500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5082248093500. Starting simulation... -switching cpus -info: Entering event queue @ 5083247965500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5084247965500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5085247965500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5086247965500. Starting simulation... -switching cpus -info: Entering event queue @ 5087247837500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5088247837500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5089247837500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5090247837500. Starting simulation... -switching cpus -info: Entering event queue @ 5091247709500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5092247709500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5093247709500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5094247709500. Starting simulation... -switching cpus -info: Entering event queue @ 5095247581500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5096247581500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5097247581500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5098247581500. Starting simulation... -switching cpus -info: Entering event queue @ 5099247453500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5100247453500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5101247453500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5102247453500. Starting simulation... -switching cpus -info: Entering event queue @ 5103247325500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5104247325500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -switching cpus -info: Entering event queue @ 5105247325500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5106247325500. Starting simulation... -switching cpus -info: Entering event queue @ 5107247197500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5108247197500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5109247197500. Starting simulation... -info: Entering event queue @ 5109247212000. Starting simulation... -switching cpus -info: Entering event queue @ 5109247571250. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5110247571250. Starting simulation... -switching cpus -info: Entering event queue @ 5110247578750. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 5111247578750. Starting simulation... -switching cpus -info: Entering event queue @ 5111247579000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5112247579000. Starting simulation... -switching cpus -info: Entering event queue @ 5112247586500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5113247586500. Starting simulation... -switching cpus -info: Entering event queue @ 5113247604500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5114247604500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5115247604500. Starting simulation... -switching cpus -info: Entering event queue @ 5115247621000. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5116247621000. Starting simulation... -info: Entering event queue @ 5119246748500. Starting simulation... -info: Entering event queue @ 5119246749500. Starting simulation... -switching cpus -info: Entering event queue @ 5119246754000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -switching cpus -info: Entering event queue @ 5120246754000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5121246754000. Starting simulation... -switching cpus -info: Entering event queue @ 5121246761500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5122246761500. Starting simulation... -info: Entering event queue @ 5123246620500. Starting simulation... -info: Entering event queue @ 5123246621500. Starting simulation... -switching cpus -info: Entering event queue @ 5123246626000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 5124246626000. Starting simulation... -switching cpus -info: Entering event queue @ 5124246627000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5125246627000. Starting simulation... -switching cpus -info: Entering event queue @ 5125246634500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5126246634500. Starting simulation... -info: Entering event queue @ 5127246915000. Starting simulation... -info: Entering event queue @ 5127246916000. Starting simulation... -switching cpus -info: Entering event queue @ 5127246920500. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 5128246920500. Starting simulation... -switching cpus -info: Entering event queue @ 5128246922000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5129246922000. Starting simulation... -switching cpus -info: Entering event queue @ 5129246929500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5130246929500. Starting simulation... -info: Entering event queue @ 5131246364500. Starting simulation... -info: Entering event queue @ 5131246365500. Starting simulation... -switching cpus -info: Entering event queue @ 5131246370000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 5132246370000. Starting simulation... -switching cpus -info: Entering event queue @ 5132246371000. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5133246371000. Starting simulation... -switching cpus -info: Entering event queue @ 5133246378500. Starting simulation... -Switching CPUs... -Next CPU: AtomicSimpleCPU -info: Entering event queue @ 5134246378500. Starting simulation... -info: Entering event queue @ 5135246236500. Starting simulation... -info: Entering event queue @ 5135246237500. Starting simulation... -switching cpus -info: Entering event queue @ 5135246242000. Starting simulation... -Switching CPUs... -Next CPU: TimingSimpleCPU -info: Entering event queue @ 5136246242000. Starting simulation... -switching cpus -info: Entering event queue @ 5136246243500. Starting simulation... -Switching CPUs... -Next CPU: DerivO3CPU -info: Entering event queue @ 5137246243500. Starting simulation... -switching cpus -info: Entering event queue @ 5137246251000. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 2b6efde37..e29319304 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -4,13 +4,15 @@ sim_seconds 5.137456 # Nu sim_ticks 5137456264000 # Number of ticks simulated final_tick 5137456264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 176189 # Simulator instruction rate (inst/s) -host_op_rate 350219 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3709429360 # Simulator tick rate (ticks/s) -host_mem_usage 1030148 # Number of bytes of host memory used -host_seconds 1384.97 # Real time elapsed on the host +host_inst_rate 293296 # Simulator instruction rate (inst/s) +host_op_rate 582999 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6174974039 # Simulator tick rate (ticks/s) +host_mem_usage 983548 # Number of bytes of host memory used +host_seconds 831.98 # Real time elapsed on the host sim_insts 244016231 # Number of instructions simulated sim_ops 485043652 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 2422400 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 383808 # Number of bytes read from this memory @@ -444,6 +446,7 @@ system.membus.respLayer2.occupancy 1658568572 # La system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.membus.respLayer4.occupancy 223775499 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.l2c.tags.replacements 103968 # number of replacements system.l2c.tags.tagsinuse 64819.095791 # Cycle average of tags in use system.l2c.tags.total_refs 3669692 # Total number of references to valid blocks. @@ -471,6 +474,15 @@ system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 system.l2c.tags.occ_percent::cpu2.inst 0.020633 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu2.data 0.071328 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.989061 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64275 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3733 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7385 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52859 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.980759 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 33713228 # Number of tag accesses +system.l2c.tags.data_accesses 33713228 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 21716 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 11486 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 326601 # number of ReadReq hits @@ -855,6 +867,11 @@ system.iocache.tags.warmup_cycle 5000213887009 # C system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.092731 # Average occupied blocks per requestor system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005796 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.005796 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428661 # Number of tag accesses +system.iocache.tags.data_accesses 428661 # Number of data accesses system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses @@ -1070,6 +1087,7 @@ system.iobus.respLayer1.occupancy 29747501 # La system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iobus.respLayer2.occupancy 957000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu0.numCycles 1152461068 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -1109,6 +1127,13 @@ system.cpu0.icache.tags.occ_percent::cpu0.inst 0.593342 system.cpu0.icache.tags.occ_percent::cpu1.inst 0.263409 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::cpu2.inst 0.140938 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.997689 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 130343050 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 130343050 # Number of data accesses system.cpu0.icache.ReadReq_hits::cpu0.inst 87032678 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu1.inst 38704601 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::cpu2.inst 2869740 # number of ReadReq hits @@ -1239,6 +1264,13 @@ system.cpu0.dcache.tags.occ_percent::cpu0.data 0.392288 system.cpu0.dcache.tags.occ_percent::cpu1.data 0.594149 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013563 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 226 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 88202622 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88202622 # Number of data accesses system.cpu0.dcache.ReadReq_hits::cpu0.data 5007486 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu1.data 2456211 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::cpu2.data 4066814 # number of ReadReq hits diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini index ab0c1f304..09e0d3e34 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -514,6 +516,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -530,6 +533,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,9 +632,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf +executable=/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout index f7ab26f15..88b266667 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 01:59:02 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:37:28 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ simplex iterations : 2663 flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 26877484000 because target called exit() +Exiting @ tick 26911413000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index a6e3b7d23..f2d38a430 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.026911 # Nu sim_ticks 26911413000 # Number of ticks simulated final_tick 26911413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116759 # Simulator instruction rate (inst/s) -host_op_rate 117598 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 34685583 # Simulator tick rate (ticks/s) -host_mem_usage 427272 # Number of bytes of host memory used -host_seconds 775.87 # Real time elapsed on the host +host_inst_rate 180996 # Simulator instruction rate (inst/s) +host_op_rate 182296 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53768206 # Simulator tick rate (ticks/s) +host_mem_usage 381936 # Number of bytes of host memory used +host_seconds 500.51 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91240351 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 45440 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 947712 # Number of bytes read from this memory system.physmem.bytes_read::total 993152 # Number of bytes read from this memory @@ -303,6 +305,7 @@ system.membus.reqLayer0.occupancy 19253000 # La system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 145189999 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 26686306 # Number of BP lookups system.cpu.branchPred.condPredicted 22003847 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 843168 # Number of conditional branches incorrect @@ -648,6 +651,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 632.612747 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.308893 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.308893 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 732 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 676 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.357422 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 27691521 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27691521 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 13844401 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13844401 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 13844401 # number of demand (read+write) hits @@ -736,6 +747,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.301529 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.018879 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007075 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.327483 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15501 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13618 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.473053 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15189018 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15189018 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 24 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 903618 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 903642 # number of ReadReq hits @@ -893,6 +913,13 @@ system.cpu.dcache.tags.warmup_cycle 8006035000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 3671.733270 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.896419 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.896419 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 448 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3128 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 59988680 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 59988680 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 23603772 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 23603772 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4532846 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini index e8dafcae9..8155e41d5 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,21 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -108,18 +117,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -129,9 +141,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -143,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -160,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -169,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout index a5dbe98d0..35b926dc8 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:18:17 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:39:34 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 397354d07..be3e03048 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.054241 # Nu sim_ticks 54240661000 # Number of ticks simulated final_tick 54240661000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2267620 # Simulator instruction rate (inst/s) -host_op_rate 2283902 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1357548360 # Simulator tick rate (ticks/s) -host_mem_usage 366572 # Number of bytes of host memory used -host_seconds 39.95 # Real time elapsed on the host +host_inst_rate 2327254 # Simulator instruction rate (inst/s) +host_op_rate 2343964 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1393249116 # Simulator tick rate (ticks/s) +host_mem_usage 371180 # Number of bytes of host memory used +host_seconds 38.93 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91252960 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 9960199711 # To system.membus.throughput 9960199711 # Throughput (bytes/s) system.membus.data_through_bus 540247816 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini index 08fdda12e..f9a7d69b3 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,18 +100,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -115,6 +126,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -123,6 +135,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -137,14 +150,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -163,12 +180,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -179,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -187,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -201,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -225,9 +250,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/mcf +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -239,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -256,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -265,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout index c84bc1d04..92da3b737 100755 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:24:43 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:40:24 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index e75e7c0cb..f99edcca6 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.147136 # Nu sim_ticks 147135976000 # Number of ticks simulated final_tick 147135976000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 529408 # Simulator instruction rate (inst/s) -host_op_rate 533204 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 859987474 # Simulator tick rate (ticks/s) -host_mem_usage 373720 # Number of bytes of host memory used -host_seconds 171.09 # Real time elapsed on the host +host_inst_rate 1334589 # Simulator instruction rate (inst/s) +host_op_rate 1344158 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2167949307 # Simulator tick rate (ticks/s) +host_mem_usage 379884 # Number of bytes of host memory used +host_seconds 67.87 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91226312 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory system.physmem.bytes_read::total 981760 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 15340000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 138060000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -116,6 +119,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 510.071144 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.249058 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249058 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 215662141 # Number of tag accesses +system.cpu.icache.tags.data_accesses 215662141 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits @@ -198,6 +209,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.270902 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015110 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.291909 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 95 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1478 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15179780 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits @@ -330,6 +350,14 @@ system.cpu.dcache.tags.warmup_cycle 54472394000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 3565.217259 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.870414 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870414 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1322 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2583 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 55531122 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55531122 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 21649218 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21649218 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 4688372 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini index de11b33de..6f2d20a8e 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,9 +107,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf +eventq_index=0 +executable=/dist/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -111,11 +122,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +141,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +151,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr index 7edd901b2..1a4f96712 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr @@ -1,3 +1 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout index db2db18f1..a8897be0c 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:07:55 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:41:52 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt index 9196a1276..c49cf6b74 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.122216 # Nu sim_ticks 122215823500 # Number of ticks simulated final_tick 122215823500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2226348 # Simulator instruction rate (inst/s) -host_op_rate 2226440 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1115942635 # Simulator tick rate (ticks/s) -host_mem_usage 357000 # Number of bytes of host memory used -host_seconds 109.52 # Real time elapsed on the host +host_inst_rate 3086610 # Simulator instruction rate (inst/s) +host_op_rate 3086737 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1547143112 # Simulator tick rate (ticks/s) +host_mem_usage 361240 # Number of bytes of host memory used +host_seconds 78.99 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 977685992 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 328674008 # Number of bytes read from this memory system.physmem.bytes_read::total 1306360000 # Number of bytes read from this memory @@ -38,6 +40,7 @@ system.physmem.bw_total::total 11438503207 # To system.membus.throughput 11438757576 # Throughput (bytes/s) system.membus.data_through_bus 1397997177 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 244431648 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini index 882273887..95a36ae61 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -147,6 +164,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +173,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +188,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,9 +216,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf +eventq_index=0 +executable=/dist/cpu2000/binaries/sparc/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -207,11 +231,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +250,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +260,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout index 1e103dc44..009ef705f 100755 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:07:47 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:43:22 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 7e2d4c700..a787dee3c 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.361489 # Nu sim_ticks 361488530000 # Number of ticks simulated final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 810264 # Simulator instruction rate (inst/s) -host_op_rate 810297 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1201274596 # Simulator tick rate (ticks/s) -host_mem_usage 365008 # Number of bytes of host memory used -host_seconds 300.92 # Real time elapsed on the host +host_inst_rate 1454320 # Simulator instruction rate (inst/s) +host_op_rate 1454380 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2156135283 # Simulator tick rate (ticks/s) +host_mem_usage 371132 # Number of bytes of host memory used +host_seconds 167.66 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 56256 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 942336 # Number of bytes read from this memory system.physmem.bytes_read::total 998592 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 15603000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls system.cpu.numCycles 722977060 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -74,6 +77,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 781 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.418457 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 488843880 # Number of tag accesses +system.cpu.icache.tags.data_accesses 488843880 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 244420617 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 244420617 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 244420617 # number of demand (read+write) hits @@ -156,6 +167,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004404 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.296955 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15586 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1385 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13986 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.475647 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 15068052 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 15068052 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 892700 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 892703 # number of ReadReq hits @@ -288,6 +308,14 @@ system.cpu.dcache.tags.warmup_cycle 134366265000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini index a7b21f16f..0b4c31c18 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini @@ -165,6 +165,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -181,6 +182,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -520,6 +522,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -536,6 +539,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,9 +632,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf +executable=/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout index 0a86dbd97..c033cc0d9 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:42:09 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 19:53:01 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,12 +16,12 @@ All Rights Reserved. nodes : 500 active arcs : 1905 simplex iterations : 1502 +info: Increasing stack size by one page. flow value : 4990014995 new implicit arcs : 23867 active arcs : 25772 simplex iterations : 2663 -info: Increasing stack size by one page. flow value : 3080014995 checksum : 68389 optimal -Exiting @ tick 65497052500 because target called exit() +Exiting @ tick 65613727000 because target called exit() diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index 999935db6..167e49074 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.065614 # Nu sim_ticks 65613727000 # Number of ticks simulated final_tick 65613727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72100 # Simulator instruction rate (inst/s) -host_op_rate 126957 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 29943715 # Simulator tick rate (ticks/s) -host_mem_usage 436724 # Number of bytes of host memory used -host_seconds 2191.24 # Real time elapsed on the host +host_inst_rate 111661 # Simulator instruction rate (inst/s) +host_op_rate 196618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46373693 # Simulator tick rate (ticks/s) +host_mem_usage 390932 # Number of bytes of host memory used +host_seconds 1414.89 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 63616 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1883136 # Number of bytes read from this memory system.physmem.bytes_read::total 1946752 # Number of bytes read from this memory @@ -300,6 +302,7 @@ system.membus.reqLayer0.occupancy 34950500 # La system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 284209000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 33859770 # Number of BP lookups system.cpu.branchPred.condPredicted 33859770 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 774913 # Number of conditional branches incorrect @@ -309,6 +312,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 99.461636 # BTB Hit Percentage system.cpu.branchPred.usedRAS 5016745 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 5399 # Number of incorrect RAS predictions. +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 131227460 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -599,6 +603,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 819.642194 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.400216 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.400216 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 867 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 51151797 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51151797 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 25574088 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 25574088 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 25574088 # number of demand (read+write) hits @@ -687,6 +699,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.607028 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020463 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.007473 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.634964 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29922 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 773 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1381 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27646 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913147 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33268796 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33268796 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1993866 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1993883 # number of ReadReq hits @@ -821,6 +842,13 @@ system.cpu.dcache.tags.warmup_cycle 20690834250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4069.513707 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993534 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993534 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 593 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3349 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 150351466 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 150351466 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 40071930 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 40071930 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31341693 # number of WriteReq hits diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini index 433f51b0f..6769a8e07 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -76,16 +81,19 @@ icache_port=system.membus.slave[1] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[4] @@ -93,6 +101,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -103,22 +112,26 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -128,9 +141,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -142,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -159,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -168,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout index 98402c27f..ea41249d4 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:43:36 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 20:16:46 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt index d28c1e1a8..17feba7fa 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.168950 # Nu sim_ticks 168950040000 # Number of ticks simulated final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1229454 # Simulator instruction rate (inst/s) -host_op_rate 2164871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1314755229 # Simulator tick rate (ticks/s) -host_mem_usage 378084 # Number of bytes of host memory used -host_seconds 128.50 # Real time elapsed on the host +host_inst_rate 1603557 # Simulator instruction rate (inst/s) +host_op_rate 2823605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1714813271 # Simulator tick rate (ticks/s) +host_mem_usage 379092 # Number of bytes of host memory used +host_seconds 98.52 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 1741569312 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 717246013 # Number of bytes read from this memory system.physmem.bytes_read::total 2458815325 # Number of bytes read from this memory @@ -36,6 +38,8 @@ system.physmem.bw_total::total 15992825110 # To system.membus.throughput 15992825110 # Throughput (bytes/s) system.membus.data_through_bus 2701988442 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 337900081 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini index ffd9b2f5e..9efa1f6d6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -76,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -84,6 +91,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -98,18 +106,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -120,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -128,6 +141,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -142,12 +156,15 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -158,16 +175,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -178,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -186,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -200,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -224,9 +250,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/mcf +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/mcf gid=100 -input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in +input=/dist/cpu2000/data/mcf/smred/input/mcf.in max_stack_size=67108864 output=cout pid=100 @@ -238,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -255,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -264,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout index 033910815..42e3e20b3 100755 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:48:06 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 20:18:36 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index fa71cbd3c..ba75a74b6 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.365989 # Nu sim_ticks 365989065000 # Number of ticks simulated final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 746941 # Simulator instruction rate (inst/s) -host_op_rate 1315244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1730329772 # Simulator tick rate (ticks/s) -host_mem_usage 386536 # Number of bytes of host memory used -host_seconds 211.51 # Real time elapsed on the host +host_inst_rate 696180 # Simulator instruction rate (inst/s) +host_op_rate 1225861 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1612738645 # Simulator tick rate (ticks/s) +host_mem_usage 388852 # Number of bytes of host memory used +host_seconds 226.94 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 51392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1871744 # Number of bytes read from this memory system.physmem.bytes_read::total 1923136 # Number of bytes read from this memory @@ -52,6 +54,8 @@ system.membus.reqLayer0.occupancy 30980000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.numCycles 731978130 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -86,6 +90,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 715 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.382812 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 435393138 # Number of tag accesses +system.cpu.icache.tags.data_accesses 435393138 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 217695357 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 217695357 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 217695357 # number of demand (read+write) hits @@ -168,6 +179,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.004697 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.611630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29708 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27875 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.906616 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33177103 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33177103 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1960498 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1960503 # number of ReadReq hits @@ -302,6 +322,14 @@ system.cpu.dcache.tags.warmup_cycle 126079701000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini index 34784c9a2..d70753e9b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -514,6 +516,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -530,6 +533,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,9 +632,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser +executable=/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr index b4d96e4ea..5d8946ede 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] -hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout index cb7300a3e..0f922bcc1 100755 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:08:48 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:41:42 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -67,4 +67,4 @@ info: Increasing stack size by one page. about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 202349747500 because target called exit() +Exiting @ tick 202741893000 because target called exit() diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index 3188dad03..3185557ef 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.202742 # Nu sim_ticks 202741893000 # Number of ticks simulated final_tick 202741893000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95210 # Simulator instruction rate (inst/s) -host_op_rate 107343 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38205910 # Simulator tick rate (ticks/s) -host_mem_usage 298452 # Number of bytes of host memory used -host_seconds 5306.56 # Real time elapsed on the host +host_inst_rate 148118 # Simulator instruction rate (inst/s) +host_op_rate 166994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59436990 # Simulator tick rate (ticks/s) +host_mem_usage 253144 # Number of bytes of host memory used +host_seconds 3411.04 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 215232 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9270080 # Number of bytes read from this memory system.physmem.bytes_read::total 9485312 # Number of bytes read from this memory @@ -287,6 +289,7 @@ system.membus.reqLayer0.occupancy 1083331500 # La system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) system.membus.respLayer1.occupancy 1398080741 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 182821881 # Number of BP lookups system.cpu.branchPred.condPredicted 143128941 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 7267602 # Number of conditional branches incorrect @@ -631,6 +634,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1095.413038 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.534870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.534870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1849 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 293 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1382 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.902832 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 229105594 # Number of tag accesses +system.cpu.icache.tags.data_accesses 229105594 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 114523215 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 114523215 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 114523215 # number of demand (read+write) hits @@ -719,6 +731,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.702196 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011015 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.113503 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.826713 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31255 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7669 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21321 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953827 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 19093617 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 19093617 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 13491 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 804384 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 817875 # number of ReadReq hits @@ -878,6 +899,14 @@ system.cpu.dcache.tags.warmup_cycle 4256684250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4057.514955 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.990604 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.990604 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2352 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1684 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 391502938 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 391502938 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 136235473 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 136235473 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 50988251 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini index 7b35bd3ad..3b7a89fcb 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,21 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -108,18 +117,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -129,9 +141,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -143,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -160,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -169,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout index b9241b523..edefc9939 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:00:02 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:44:24 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 14e1e1ee2..d2cbe9ffb 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.290499 # Nu sim_ticks 290498967000 # Number of ticks simulated final_tick 290498967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1591705 # Simulator instruction rate (inst/s) -host_op_rate 1794011 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 912762441 # Simulator tick rate (ticks/s) -host_mem_usage 237748 # Number of bytes of host memory used -host_seconds 318.26 # Real time elapsed on the host +host_inst_rate 2346027 # Simulator instruction rate (inst/s) +host_op_rate 2644207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1345327991 # Simulator tick rate (ticks/s) +host_mem_usage 241300 # Number of bytes of host memory used +host_seconds 215.93 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 570968167 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 2066445500 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 422852701 # Number of bytes read from this memory system.physmem.bytes_read::total 2489298201 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 9312824252 # To system.membus.throughput 9312824252 # Throughput (bytes/s) system.membus.data_through_bus 2705365825 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini index d125ef04b..cc298b9ef 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,18 +100,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -115,6 +126,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -123,6 +135,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -137,14 +150,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -163,12 +180,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -179,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -187,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -201,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -225,9 +250,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/parser +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -239,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -256,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -265,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout index 0a37362e8..13fa82ee3 100755 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:48:54 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:45:59 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index 3138d4062..feaf610e8 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.717366 # Nu sim_ticks 717366012000 # Number of ticks simulated final_tick 717366012000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1130634 # Simulator instruction rate (inst/s) -host_op_rate 1274033 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1606137434 # Simulator tick rate (ticks/s) -host_mem_usage 243872 # Number of bytes of host memory used -host_seconds 446.64 # Real time elapsed on the host +host_inst_rate 1243497 # Simulator instruction rate (inst/s) +host_op_rate 1401211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1766466230 # Simulator tick rate (ticks/s) +host_mem_usage 251064 # Number of bytes of host memory used +host_seconds 406.10 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 569034839 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 177280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8952256 # Number of bytes read from this memory system.physmem.bytes_read::total 9129536 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 1006226000 # La system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer1.occupancy 1283841000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -124,6 +127,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 982.663229 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.479816 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.479816 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 257 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1403 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.846191 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1033234273 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1033234273 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 516599855 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 516599855 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 516599855 # number of demand (read+write) hits @@ -206,6 +218,14 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.713558 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008785 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.109054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.831396 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3656 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27181 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951447 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18220084 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18220084 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 8751 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 743573 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 752324 # number of ReadReq hits @@ -340,6 +360,15 @@ system.cpu.dcache.tags.warmup_cycle 11885124000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4065.297446 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992504 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992504 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3546 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 165 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 363052326 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 363052326 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 122957658 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 122957658 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 53883046 # number of WriteReq hits diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini index 6c434f44b..e184df091 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini @@ -165,6 +165,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -181,6 +182,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -520,6 +522,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -536,6 +539,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,9 +632,9 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser +executable=/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout index 5d75453d9..185610e19 100755 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout @@ -1,28 +1,15 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 02:08:50 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 20:22:33 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Reading the dictionary files: *********info: Increasing stack size by one page. -**********************************info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -info: Increasing stack size by one page. -****** +**************************************** 58924 words stored in 3784810 bytes @@ -34,8 +21,18 @@ Processing sentences in batch mode Echoing of input sentence turned on. * as had expected the party to be a success , it was a success +info: Increasing stack size by one page. +info: Increasing stack size by one page. * do you know where John 's * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. +info: Increasing stack size by one page. * how fast the program is it * I am wondering whether to invite to the party * I gave him for his birthday it @@ -75,9 +72,11 @@ Echoing of input sentence turned on. the man with whom I play tennis is here there is a dog in the park this is not the man we know and love +info: Increasing stack size by one page. +info: Increasing stack size by one page. we like to eat at restaurants , usually on weekends what did John say he thought you should do about 2 million people attended the five best costumes got prizes No errors! -Exiting @ tick 458276279000 because target called exit() +Exiting @ tick 459105675500 because target called exit() diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index d5a6aea3b..2e6ae088e 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,106 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.459341 # Number of seconds simulated -sim_ticks 459340600000 # Number of ticks simulated -final_tick 459340600000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.459106 # Number of seconds simulated +sim_ticks 459105675500 # Number of ticks simulated +final_tick 459105675500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 64463 # Simulator instruction rate (inst/s) -host_op_rate 119200 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35810129 # Simulator tick rate (ticks/s) -host_mem_usage 391936 # Number of bytes of host memory used -host_seconds 12827.11 # Real time elapsed on the host +host_inst_rate 97287 # Simulator instruction rate (inst/s) +host_op_rate 179895 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 54016738 # Simulator tick rate (ticks/s) +host_mem_usage 345252 # Number of bytes of host memory used +host_seconds 8499.32 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 203008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24478016 # Number of bytes read from this memory -system.physmem.bytes_read::total 24681024 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 203008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 203008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18788608 # Number of bytes written to this memory -system.physmem.bytes_written::total 18788608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 382469 # Number of read requests responded to by this memory -system.physmem.num_reads::total 385641 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 293572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 293572 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 441955 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53289468 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53731423 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 441955 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 441955 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 40903434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 40903434 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 40903434 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 441955 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53289468 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 94634857 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 385641 # Number of read requests accepted -system.physmem.writeReqs 293572 # Number of write requests accepted -system.physmem.readBursts 385641 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 293572 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24669632 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11392 # Total number of bytes read from write queue -system.physmem.bytesWritten 18788480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24681024 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18788608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 178 # Number of DRAM read bursts serviced by the write queue +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 202240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24471936 # Number of bytes read from this memory +system.physmem.bytes_read::total 24674176 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 202240 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 202240 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18788544 # Number of bytes written to this memory +system.physmem.bytes_written::total 18788544 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 382374 # Number of read requests responded to by this memory +system.physmem.num_reads::total 385534 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293571 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293571 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 440509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53303493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53744001 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 440509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440509 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 40924225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 40924225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 40924225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 440509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53303493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 94668226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 385534 # Number of read requests accepted +system.physmem.writeReqs 293571 # Number of write requests accepted +system.physmem.readBursts 385534 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293571 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24663936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue +system.physmem.bytesWritten 18787328 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24674176 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18788544 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 135253 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24057 # Per bank write bursts -system.physmem.perBankRdBursts::1 26446 # Per bank write bursts -system.physmem.perBankRdBursts::2 24658 # Per bank write bursts -system.physmem.perBankRdBursts::3 24494 # Per bank write bursts -system.physmem.perBankRdBursts::4 23239 # Per bank write bursts -system.physmem.perBankRdBursts::5 23672 # Per bank write bursts -system.physmem.perBankRdBursts::6 24412 # Per bank write bursts -system.physmem.perBankRdBursts::7 24201 # Per bank write bursts -system.physmem.perBankRdBursts::8 23613 # Per bank write bursts -system.physmem.perBankRdBursts::9 23828 # Per bank write bursts -system.physmem.perBankRdBursts::10 24822 # Per bank write bursts -system.physmem.perBankRdBursts::11 24051 # Per bank write bursts -system.physmem.perBankRdBursts::12 23218 # Per bank write bursts -system.physmem.perBankRdBursts::13 22963 # Per bank write bursts -system.physmem.perBankRdBursts::14 23780 # Per bank write bursts -system.physmem.perBankRdBursts::15 24009 # Per bank write bursts -system.physmem.perBankWrBursts::0 18526 # Per bank write bursts -system.physmem.perBankWrBursts::1 19824 # Per bank write bursts -system.physmem.perBankWrBursts::2 18930 # Per bank write bursts -system.physmem.perBankWrBursts::3 18895 # Per bank write bursts -system.physmem.perBankWrBursts::4 18030 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 133980 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24056 # Per bank write bursts +system.physmem.perBankRdBursts::1 26412 # Per bank write bursts +system.physmem.perBankRdBursts::2 24662 # Per bank write bursts +system.physmem.perBankRdBursts::3 24490 # Per bank write bursts +system.physmem.perBankRdBursts::4 23228 # Per bank write bursts +system.physmem.perBankRdBursts::5 23668 # Per bank write bursts +system.physmem.perBankRdBursts::6 24406 # Per bank write bursts +system.physmem.perBankRdBursts::7 24200 # Per bank write bursts +system.physmem.perBankRdBursts::8 23616 # Per bank write bursts +system.physmem.perBankRdBursts::9 23822 # Per bank write bursts +system.physmem.perBankRdBursts::10 24814 # Per bank write bursts +system.physmem.perBankRdBursts::11 24049 # Per bank write bursts +system.physmem.perBankRdBursts::12 23223 # Per bank write bursts +system.physmem.perBankRdBursts::13 22960 # Per bank write bursts +system.physmem.perBankRdBursts::14 23777 # Per bank write bursts +system.physmem.perBankRdBursts::15 23991 # Per bank write bursts +system.physmem.perBankWrBursts::0 18528 # Per bank write bursts +system.physmem.perBankWrBursts::1 19813 # Per bank write bursts +system.physmem.perBankWrBursts::2 18933 # Per bank write bursts +system.physmem.perBankWrBursts::3 18904 # Per bank write bursts +system.physmem.perBankWrBursts::4 18032 # Per bank write bursts system.physmem.perBankWrBursts::5 18409 # Per bank write bursts system.physmem.perBankWrBursts::6 18982 # Per bank write bursts -system.physmem.perBankWrBursts::7 18942 # Per bank write bursts -system.physmem.perBankWrBursts::8 18537 # Per bank write bursts -system.physmem.perBankWrBursts::9 18120 # Per bank write bursts -system.physmem.perBankWrBursts::10 18829 # Per bank write bursts -system.physmem.perBankWrBursts::11 17702 # Per bank write bursts -system.physmem.perBankWrBursts::12 17342 # Per bank write bursts -system.physmem.perBankWrBursts::13 16954 # Per bank write bursts -system.physmem.perBankWrBursts::14 17718 # Per bank write bursts -system.physmem.perBankWrBursts::15 17830 # Per bank write bursts +system.physmem.perBankWrBursts::7 18937 # Per bank write bursts +system.physmem.perBankWrBursts::8 18536 # Per bank write bursts +system.physmem.perBankWrBursts::9 18110 # Per bank write bursts +system.physmem.perBankWrBursts::10 18825 # Per bank write bursts +system.physmem.perBankWrBursts::11 17714 # Per bank write bursts +system.physmem.perBankWrBursts::12 17347 # Per bank write bursts +system.physmem.perBankWrBursts::13 16962 # Per bank write bursts +system.physmem.perBankWrBursts::14 17712 # Per bank write bursts +system.physmem.perBankWrBursts::15 17808 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 459340574000 # Total gap between requests +system.physmem.totGap 459105568000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 385641 # Read request sizes (log2) +system.physmem.readPktSize::6 385534 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 293572 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 380895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293571 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 380726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -127,31 +129,31 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 13203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 13289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 13319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 13330 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 13323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 13318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 13380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 13367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 13383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 13400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 13202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 13293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 13312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 13323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 13320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 13374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 13373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 13375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 13406 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 13420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 13351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 13361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 13365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 13348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 13319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 13359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 13363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 13367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 13343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 13321 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 13314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 13324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 13314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 13479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 13330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 13311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 13494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 13282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see @@ -159,292 +161,295 @@ system.physmem.wrQLenPdf::28 8 # Wh system.physmem.wrQLenPdf::29 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147621 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.388468 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 155.710774 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 443.499186 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64 63823 43.23% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128 27954 18.94% 62.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192 12395 8.40% 70.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256 7134 4.83% 75.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320 4845 3.28% 78.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384 3604 2.44% 81.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448 2701 1.83% 82.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512 2191 1.48% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576 1897 1.29% 85.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640 1561 1.06% 86.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704 2008 1.36% 88.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768 1215 0.82% 88.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832 1176 0.80% 89.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896 1069 0.72% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960 885 0.60% 91.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024 912 0.62% 91.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088 1043 0.71% 92.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152 1161 0.79% 93.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216 1134 0.77% 93.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280 871 0.59% 94.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344 771 0.52% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408 5235 3.55% 98.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472 297 0.20% 98.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536 223 0.15% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600 174 0.12% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664 140 0.09% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728 99 0.07% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792 107 0.07% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856 67 0.05% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920 49 0.03% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984 50 0.03% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048 49 0.03% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112 40 0.03% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176 28 0.02% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240 31 0.02% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304 21 0.01% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368 22 0.01% 99.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432 31 0.02% 99.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496 30 0.02% 99.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560 18 0.01% 99.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624 24 0.02% 99.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688 16 0.01% 99.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752 18 0.01% 99.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816 20 0.01% 99.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880 17 0.01% 99.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944 18 0.01% 99.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008 17 0.01% 99.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072 21 0.01% 99.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136 13 0.01% 99.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200 13 0.01% 99.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264 16 0.01% 99.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328 15 0.01% 99.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392 9 0.01% 99.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456 14 0.01% 99.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520 12 0.01% 99.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584 17 0.01% 99.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648 16 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712 8 0.01% 99.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776 10 0.01% 99.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840 9 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904 11 0.01% 99.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968 6 0.00% 99.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032 17 0.01% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096 7 0.00% 99.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160 17 0.01% 99.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224 18 0.01% 99.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288 37 0.03% 99.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416 5 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480 6 0.00% 99.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544 5 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608 4 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 147523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.532839 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 155.815987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 442.359788 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64 63790 43.24% 43.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128 27848 18.88% 62.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192 12415 8.42% 70.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256 7114 4.82% 75.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320 4845 3.28% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384 3608 2.45% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448 2677 1.81% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512 2233 1.51% 84.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576 1891 1.28% 85.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640 1571 1.06% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704 1991 1.35% 88.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768 1204 0.82% 88.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832 1205 0.82% 89.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896 1076 0.73% 90.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960 955 0.65% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024 927 0.63% 91.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088 1004 0.68% 92.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152 1138 0.77% 93.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216 1120 0.76% 93.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280 845 0.57% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344 784 0.53% 95.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408 5236 3.55% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472 318 0.22% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536 229 0.16% 98.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600 157 0.11% 99.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664 117 0.08% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728 103 0.07% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792 91 0.06% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856 87 0.06% 99.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920 53 0.04% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984 53 0.04% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048 37 0.03% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112 48 0.03% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176 24 0.02% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240 28 0.02% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304 24 0.02% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368 28 0.02% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432 24 0.02% 99.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496 15 0.01% 99.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560 23 0.02% 99.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624 31 0.02% 99.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688 20 0.01% 99.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752 27 0.02% 99.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816 23 0.02% 99.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880 23 0.02% 99.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944 20 0.01% 99.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008 23 0.02% 99.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072 23 0.02% 99.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136 19 0.01% 99.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200 14 0.01% 99.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264 18 0.01% 99.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328 16 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392 9 0.01% 99.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456 13 0.01% 99.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520 16 0.01% 99.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584 16 0.01% 99.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648 15 0.01% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712 8 0.01% 99.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776 10 0.01% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840 5 0.00% 99.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904 11 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968 8 0.01% 99.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032 10 0.01% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096 6 0.00% 99.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160 14 0.01% 99.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224 17 0.01% 99.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288 34 0.02% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352 3 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416 7 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480 2 0.00% 99.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544 6 0.00% 99.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608 2 0.00% 99.92% # Bytes accessed per row activation system.physmem.bytesPerActivate::4672 3 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736 4 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800 1 0.00% 99.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864 3 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928 5 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992 2 0.00% 99.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056 8 0.01% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120 4 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248 3 0.00% 99.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312 6 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736 5 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800 6 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864 1 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928 6 0.00% 99.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992 5 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056 6 0.00% 99.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120 5 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248 2 0.00% 99.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312 4 0.00% 99.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::5376 3 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440 5 0.00% 99.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504 5 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568 4 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696 4 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440 6 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504 3 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568 1 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632 3 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696 2 0.00% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760 4 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824 4 0.00% 99.97% # Bytes accessed per row activation system.physmem.bytesPerActivate::5888 6 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952 3 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016 14 0.01% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080 3 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952 4 0.00% 99.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016 7 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080 4 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208 2 0.00% 99.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::6272 19 0.01% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336 3 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336 2 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::6528 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147621 # Bytes accessed per row activation -system.physmem.totQLat 3824316500 # Total ticks spent queuing -system.physmem.totMemAccLat 12085472750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1927315000 # Total ticks spent in databus transfers -system.physmem.totBankLat 6333841250 # Total ticks spent accessing banks -system.physmem.avgQLat 9921.36 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 16431.77 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::7104 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147523 # Bytes accessed per row activation +system.physmem.totQLat 3823508500 # Total ticks spent queuing +system.physmem.totMemAccLat 12080026000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1926870000 # Total ticks spent in databus transfers +system.physmem.totBankLat 6329647500 # Total ticks spent accessing banks +system.physmem.avgQLat 9921.55 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 16424.69 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31353.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 53.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 40.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.73 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 40.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31346.24 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 53.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 40.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 53.74 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 40.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.74 # Data bus utilization in percentage system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 9.23 # Average write queue length when enqueuing -system.physmem.readRowHits 326993 # Number of row buffer hits during reads -system.physmem.writeRowHits 204419 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.83 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 69.63 # Row buffer hit rate for writes -system.physmem.avgGap 676283.54 # Average gap between requests -system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 5.85 # Percentage of time for which DRAM has all the banks in precharge state -system.membus.throughput 94634857 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 178796 # Transaction distribution -system.membus.trans_dist::ReadResp 178796 # Transaction distribution -system.membus.trans_dist::Writeback 293572 # Transaction distribution -system.membus.trans_dist::UpgradeReq 135253 # Transaction distribution -system.membus.trans_dist::UpgradeResp 135253 # Transaction distribution -system.membus.trans_dist::ReadExReq 206845 # Transaction distribution -system.membus.trans_dist::ReadExResp 206845 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1335360 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1335360 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1335360 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43469632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43469632 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 43469632 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 43469632 # Total data (bytes) +system.physmem.avgWrQLen 9.75 # Average write queue length when enqueuing +system.physmem.readRowHits 326967 # Number of row buffer hits during reads +system.physmem.writeRowHits 204436 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 69.64 # Row buffer hit rate for writes +system.physmem.avgGap 676045.04 # Average gap between requests +system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 5.78 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 94668226 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 178706 # Transaction distribution +system.membus.trans_dist::ReadResp 178706 # Transaction distribution +system.membus.trans_dist::Writeback 293571 # Transaction distribution +system.membus.trans_dist::UpgradeReq 133980 # Transaction distribution +system.membus.trans_dist::UpgradeResp 133980 # Transaction distribution +system.membus.trans_dist::ReadExReq 206828 # Transaction distribution +system.membus.trans_dist::ReadExResp 206828 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1332599 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1332599 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1332599 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43462720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 43462720 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 43462720 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 43462720 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 3391724500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3389205500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 3901051256 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3898787780 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.8 # Layer utilization (%) -system.cpu.branchPred.lookups 205617807 # Number of BP lookups -system.cpu.branchPred.condPredicted 205617807 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9908418 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 117215133 # Number of BTB lookups -system.cpu.branchPred.BTBHits 114724662 # Number of BTB hits +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.branchPred.lookups 205604659 # Number of BP lookups +system.cpu.branchPred.condPredicted 205604659 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9906655 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 117175952 # Number of BTB lookups +system.cpu.branchPred.BTBHits 114700451 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.875299 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25059559 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1805276 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.887364 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25061463 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1805826 # Number of incorrect RAS predictions. +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 918840117 # number of cpu cycles simulated +system.cpu.numCycles 918372988 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 167454161 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1131890109 # Number of instructions fetch has processed -system.cpu.fetch.Branches 205617807 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 139784221 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 352321921 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 71123589 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 305412308 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 47848 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 248697 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 51 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 162055223 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2523762 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 886447009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.375660 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.323512 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 167405307 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1131731622 # Number of instructions fetch has processed +system.cpu.fetch.Branches 205604659 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 139761914 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 352276692 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 71095438 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 305025706 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 47339 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 248116 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 162029256 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2531741 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 885941657 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.376715 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.323883 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 538196407 60.71% 60.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 23398337 2.64% 63.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 25267875 2.85% 66.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 27893164 3.15% 69.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 17745237 2.00% 71.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 22915160 2.59% 73.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 29437572 3.32% 77.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 26645476 3.01% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 174947781 19.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 537736172 60.70% 60.70% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 23397075 2.64% 63.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 25259789 2.85% 66.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 27891024 3.15% 69.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 17747651 2.00% 71.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 22912562 2.59% 73.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 29424314 3.32% 77.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 26642726 3.01% 80.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 174930344 19.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 886447009 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.223780 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.231868 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 222604172 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 260544811 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 295377211 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 46958792 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 60962023 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2071584997 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 60962023 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 256124443 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 115849529 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 18111 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 306710232 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 146782671 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2035392094 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 19900 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 24933273 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 106586441 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 2138335278 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5151319538 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3273897775 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39701 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 885941657 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.223879 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.232322 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 222573687 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 260132185 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 295357990 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 46939340 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 60938455 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2071381091 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 5 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 60938455 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 256079146 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 115670707 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 18358 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 306659021 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 146575970 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2035220367 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 19921 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 24919931 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 106353414 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 2138170371 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5150798156 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3273538468 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 41295 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 524294424 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1242 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1171 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 346564705 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 495938130 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 194456766 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 195343621 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 54992684 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1975627132 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 13244 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1772183771 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 484863 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 441729805 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 735457697 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 12692 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 886447009 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.999199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.882883 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 524129517 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1246 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1179 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 346542949 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 495881862 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 194416479 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 195473768 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54732552 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1975446731 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13521 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1772053501 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 482535 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 441556981 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 735252947 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12969 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 885941657 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.000192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.883038 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 269548828 30.41% 30.41% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 152175288 17.17% 47.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 137113127 15.47% 63.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 132050060 14.90% 77.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91550725 10.33% 88.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 55998430 6.32% 94.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 34403840 3.88% 98.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11839729 1.34% 99.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1766982 0.20% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 269231258 30.39% 30.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 151900240 17.15% 47.53% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 137366514 15.51% 63.04% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 131748871 14.87% 77.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91701810 10.35% 88.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 55961984 6.32% 94.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 34425337 3.89% 98.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 11840706 1.34% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1764937 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 886447009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 885941657 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4936288 32.45% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 7665302 50.39% 82.85% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2609145 17.15% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4931859 32.39% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.39% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 7680982 50.45% 82.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2612006 17.16% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2622898 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1165798232 65.78% 65.93% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 353842 0.02% 65.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3880856 0.22% 66.17% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2622482 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1165712605 65.78% 65.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 353084 0.02% 65.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3880807 0.22% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.17% # Type of FU issued @@ -471,84 +476,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.17% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.17% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.17% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 429305841 24.22% 90.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 170222097 9.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 429261253 24.22% 90.39% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 170223265 9.61% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1772183771 # Type of FU issued -system.cpu.iq.rate 1.928718 # Inst issue rate -system.cpu.iq.fu_busy_cnt 15210735 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008583 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4446495646 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2417577635 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1744952561 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 14503 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 50594 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 3428 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1784764794 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 6814 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 172654482 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1772053501 # Type of FU issued +system.cpu.iq.rate 1.929558 # Inst issue rate +system.cpu.iq.fu_busy_cnt 15224847 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008592 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4445741046 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2417220510 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1744818779 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 14995 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 52000 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 3560 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1784648801 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 7065 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 172668148 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 111836934 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 389891 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 330016 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 45296580 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 111780722 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 387016 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 326982 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 45256293 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 14646 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.rescheduledLoads 15018 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 570 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 60962023 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 68066484 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 7196875 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1975640376 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 789853 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 495939091 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 194456766 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 3282 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4474777 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 82775 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 330016 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5907886 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4422310 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10330196 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1753064930 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 424170565 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 19118841 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 60938455 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 67998417 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7163340 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1975460252 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 795198 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 495882879 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 194416479 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 3400 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4461902 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 83950 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 326982 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5904539 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4423611 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10328150 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1752928715 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 424128579 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 19124786 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 590955910 # number of memory reference insts executed -system.cpu.iew.exec_branches 167475793 # Number of branches executed -system.cpu.iew.exec_stores 166785345 # Number of stores executed -system.cpu.iew.exec_rate 1.907911 # Inst execution rate -system.cpu.iew.wb_sent 1749812928 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1744955989 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1325071537 # num instructions producing a value -system.cpu.iew.wb_consumers 1945900521 # num instructions consuming a value +system.cpu.iew.exec_refs 590915769 # number of memory reference insts executed +system.cpu.iew.exec_branches 167467646 # Number of branches executed +system.cpu.iew.exec_stores 166787190 # Number of stores executed +system.cpu.iew.exec_rate 1.908733 # Inst execution rate +system.cpu.iew.wb_sent 1749675549 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1744822339 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1324948168 # num instructions producing a value +system.cpu.iew.wb_consumers 1945614075 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.899086 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.680955 # average fanout of values written-back +system.cpu.iew.wb_rate 1.899906 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.680992 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 446680078 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 446501460 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9936737 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 825484986 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.852231 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.435254 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9934679 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 825003202 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.853312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.435859 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 333347760 40.38% 40.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193315332 23.42% 63.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 63291763 7.67% 71.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 92551196 11.21% 82.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 24974559 3.03% 85.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27516320 3.33% 89.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9293108 1.13% 90.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 11361813 1.38% 91.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 69833135 8.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 333018307 40.37% 40.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 193164035 23.41% 63.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 63275385 7.67% 71.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 92552193 11.22% 82.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 24927805 3.02% 85.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27507260 3.33% 89.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9364368 1.14% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 11367203 1.38% 91.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69826646 8.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 825484986 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 825003202 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,228 +564,245 @@ system.cpu.commit.branches 149758583 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 1526605509 # Number of committed integer instructions. system.cpu.commit.function_calls 17673145 # Number of function calls committed. -system.cpu.commit.bw_lim_events 69833135 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69826646 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2731320630 # The number of ROB reads -system.cpu.rob.rob_writes 4012461124 # The number of ROB writes -system.cpu.timesIdled 3340699 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32393108 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2730666717 # The number of ROB reads +system.cpu.rob.rob_writes 4012080782 # The number of ROB writes +system.cpu.timesIdled 3354849 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 32431331 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 826877109 # Number of Instructions Simulated -system.cpu.cpi 1.111217 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.111217 # CPI: Total CPI of All Threads -system.cpu.ipc 0.899914 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.899914 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2716389897 # number of integer regfile reads -system.cpu.int_regfile_writes 1420532102 # number of integer regfile writes -system.cpu.fp_regfile_reads 3421 # number of floating regfile reads -system.cpu.fp_regfile_writes 19 # number of floating regfile writes -system.cpu.cc_regfile_reads 597244921 # number of cc regfile reads -system.cpu.cc_regfile_writes 405448259 # number of cc regfile writes -system.cpu.misc_regfile_reads 964724023 # number of misc regfile reads +system.cpu.cpi 1.110652 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.110652 # CPI: Total CPI of All Threads +system.cpu.ipc 0.900372 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.900372 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2716202384 # number of integer regfile reads +system.cpu.int_regfile_writes 1420402354 # number of integer regfile writes +system.cpu.fp_regfile_reads 3547 # number of floating regfile reads +system.cpu.fp_regfile_writes 23 # number of floating regfile writes +system.cpu.cc_regfile_reads 597198676 # number of cc regfile reads +system.cpu.cc_regfile_writes 405403172 # number of cc regfile writes +system.cpu.misc_regfile_reads 964659775 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.toL2Bus.throughput 697845146 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 1906044 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1906043 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2330771 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 136656 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 136656 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771758 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 150484 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7672451 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7822935 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 439424 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311357120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 311796544 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 311796544 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 8752064 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4906973310 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 697995780 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 1904573 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1904572 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2330749 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 135378 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 135378 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771770 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771770 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 149099 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7669617 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7818716 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 435968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311347520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size::total 311783488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 311783488 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 8670336 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 4905098758 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 215891495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 213898487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3953569925 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3952694158 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.tags.replacements 5335 # number of replacements -system.cpu.icache.tags.tagsinuse 1037.583647 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 161907582 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 6916 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 23410.581550 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5304 # number of replacements +system.cpu.icache.tags.tagsinuse 1036.579952 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 161882998 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 6874 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 23550.043352 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1037.583647 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.506633 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.506633 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 161909622 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 161909622 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 161909622 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 161909622 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 161909622 # number of overall hits -system.cpu.icache.overall_hits::total 161909622 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 145600 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 145600 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 145600 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 145600 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 145600 # number of overall misses -system.cpu.icache.overall_misses::total 145600 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 941474740 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 941474740 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 941474740 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 941474740 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 941474740 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 941474740 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 162055222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 162055222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 162055222 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 162055222 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 162055222 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 162055222 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000898 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000898 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000898 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000898 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000898 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000898 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6466.172665 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6466.172665 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6466.172665 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6466.172665 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6466.172665 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6466.172665 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 250 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 170 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 41.666667 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 170 # average number of cycles each access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1036.579952 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.506143 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.506143 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1570 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 248 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1211 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.766602 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 324200798 # Number of tag accesses +system.cpu.icache.tags.data_accesses 324200798 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 161884991 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 161884991 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 161884991 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 161884991 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 161884991 # number of overall hits +system.cpu.icache.overall_hits::total 161884991 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 144265 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 144265 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 144265 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 144265 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 144265 # number of overall misses +system.cpu.icache.overall_misses::total 144265 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 939571727 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 939571727 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 939571727 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 939571727 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 939571727 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 939571727 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 162029256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 162029256 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 162029256 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 162029256 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 162029256 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 162029256 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000890 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000890 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000890 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000890 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000890 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000890 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6512.818265 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6512.818265 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6512.818265 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6512.818265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6512.818265 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6512.818265 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 329 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 8 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 41.125000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1982 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1982 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1982 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1982 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1982 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1982 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 143618 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 143618 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 143618 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 143618 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 143618 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 143618 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 562974254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 562974254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 562974254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 562974254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 562974254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 562974254 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000886 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000886 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000886 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000886 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3919.942166 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3919.942166 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3919.942166 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3919.942166 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3919.942166 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1978 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1978 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1978 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1978 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1978 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1978 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 142287 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 142287 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 142287 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 142287 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 142287 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 142287 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 558890013 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 558890013 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 558890013 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 558890013 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 558890013 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 558890013 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000878 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000878 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000878 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000878 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000878 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000878 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3927.906365 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3927.906365 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3927.906365 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 3927.906365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3927.906365 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 3927.906365 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 352959 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29669.713018 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3697218 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 385325 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.595064 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 352852 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29667.815296 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3696724 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 385211 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.596621 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 199249645000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21121.996968 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 224.213504 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8323.502546 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644592 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.006842 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.254013 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905448 # Average percentage of cache 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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2530088 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.247279 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 395994774 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2534184 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 156.261256 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 2529960 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.243311 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 395939715 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2534056 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 156.247421 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 1794365000 # Cycle when the warmup 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+system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 739 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3316 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 801001196 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 801001196 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 247190433 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 247190433 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148236290 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148236290 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 395426723 # number of demand (read+write) hits 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system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 399287488 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 399287488 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 399287488 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 399287488 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011523 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011523 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006203 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006203 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009536 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009536 # miss rate for demand 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+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120394 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1120394 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 17019 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 17019 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1137413 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1137413 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1137413 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1137413 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1762541 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1762541 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 906893 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 906893 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2669434 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2669434 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2669434 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2669434 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30851541255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 30851541255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 24700633087 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 24700633087 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55552174342 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55552174342 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55552174342 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55552174342 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007048 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007048 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006080 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006080 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006686 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006686 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006686 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.013385 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17504.013385 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27236.546193 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27236.546193 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20810.469314 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20810.469314 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20810.469314 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20810.469314 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini index 397d5a34d..bcd42cfa4 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -76,16 +81,19 @@ icache_port=system.membus.slave[1] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[4] @@ -93,6 +101,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -103,22 +112,26 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -128,9 +141,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -142,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -159,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -168,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout index abce0a0d4..cbb107c47 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:44:23 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 20:48:32 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt index 87dac48c4..4df869dc7 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.885229 # Nu sim_ticks 885229328000 # Number of ticks simulated final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1293065 # Simulator instruction rate (inst/s) -host_op_rate 2391022 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1384315331 # Simulator tick rate (ticks/s) -host_mem_usage 251216 # Number of bytes of host memory used -host_seconds 639.47 # Real time elapsed on the host +host_inst_rate 1633857 # Simulator instruction rate (inst/s) +host_op_rate 3021184 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1749156833 # Simulator tick rate (ticks/s) +host_mem_usage 252248 # Number of bytes of host memory used +host_seconds 506.09 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 8546776520 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 2285655658 # Number of bytes read from this memory system.physmem.bytes_read::total 10832432178 # Number of bytes read from this memory @@ -36,6 +38,8 @@ system.physmem.bw_total::total 13357308966 # To system.membus.throughput 13357308966 # Throughput (bytes/s) system.membus.data_through_bus 11824281640 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 1770458657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini index 3a3bc324c..bd4e435a1 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -76,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -84,6 +91,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -98,18 +106,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -120,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -128,6 +141,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -142,12 +156,15 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -158,16 +175,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -178,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -186,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -200,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -224,9 +250,10 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/parser +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/parser gid=100 -input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in +input=/dist/cpu2000/data/parser/mdred/input/parser.in max_stack_size=67108864 output=cout pid=100 @@ -238,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -255,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -264,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout index 59b399b0b..530ac97a0 100755 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:41:23 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 20:57:08 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 43f2a7587..c65900aab 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.647873 # Nu sim_ticks 1647872849000 # Number of ticks simulated final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 788676 # Simulator instruction rate (inst/s) -host_op_rate 1458350 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1571742015 # Simulator tick rate (ticks/s) -host_mem_usage 258676 # Number of bytes of host memory used -host_seconds 1048.44 # Real time elapsed on the host +host_inst_rate 782951 # Simulator instruction rate (inst/s) +host_op_rate 1447764 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1560332529 # Simulator tick rate (ticks/s) +host_mem_usage 260992 # Number of bytes of host memory used +host_seconds 1056.10 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 120704 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 24272448 # Number of bytes read from this memory system.physmem.bytes_read::total 24393152 # Number of bytes read from this memory @@ -52,6 +54,8 @@ system.membus.reqLayer0.occupancy 3011737000 # La system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.numCycles 3295745698 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -86,6 +90,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1507 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.762207 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 2136696946 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2136696946 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1068344252 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1068344252 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1068344252 # number of demand (read+write) hits @@ -168,6 +181,14 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.893750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32355 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8220 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 24069 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987396 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 39930218 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 39930218 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 928 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1554848 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1555776 # number of ReadReq hits @@ -302,6 +323,15 @@ system.cpu.dcache.tags.warmup_cycle 8211724000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini index a92131062..c27165d1c 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -56,6 +60,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fetchBuffSize=4 function_trace=false function_trace_start=0 @@ -90,6 +95,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -105,6 +111,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -113,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -127,11 +135,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -140,6 +151,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -148,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -162,17 +175,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -181,6 +200,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -189,6 +209,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -203,12 +224,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -218,6 +242,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -227,7 +252,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -241,11 +267,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -265,6 +293,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -276,17 +305,21 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr index 860580eeb..abe1622a9 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr @@ -49,4 +49,3 @@ Writing to chair.cook.ppm 13 8 14 14 8 14 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout index 3f1389dac..8e653912b 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:53:14 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:48:27 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -11,4 +11,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 139916242500 because target called exit() +Exiting @ tick 139926186500 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt index 0feb1e331..eb5995295 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.139926 # Nu sim_ticks 139926186500 # Number of ticks simulated final_tick 139926186500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122800 # Simulator instruction rate (inst/s) -host_op_rate 122800 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43101138 # Simulator tick rate (ticks/s) -host_mem_usage 261428 # Number of bytes of host memory used -host_seconds 3246.46 # Real time elapsed on the host +host_inst_rate 138827 # Simulator instruction rate (inst/s) +host_op_rate 138827 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 48726388 # Simulator tick rate (ticks/s) +host_mem_usage 236592 # Number of bytes of host memory used +host_seconds 2871.67 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory system.physmem.bytes_read::total 468992 # Number of bytes read from this memory @@ -257,6 +259,7 @@ system.membus.reqLayer0.occupancy 8743500 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 68145750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 53489673 # Number of BP lookups system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect @@ -368,6 +371,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939408 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894013 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894013 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1366 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 97226551 # Number of tag accesses +system.cpu.icache.tags.data_accesses 97226551 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 48606790 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 48606790 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 48606790 # number of demand (read+write) hits @@ -476,6 +488,14 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.119227 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4717 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 564 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3928 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.143951 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 77554 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 77554 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 544 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits @@ -608,6 +628,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 3284.890275 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.801975 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.801975 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3109 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336554588 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336554588 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 94753181 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753181 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73501074 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini index 427d7de3e..0f18e6f39 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,6 +533,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -550,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -566,6 +572,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -592,7 +599,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon +executable=/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr index 860580eeb..abe1622a9 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr @@ -49,4 +49,3 @@ Writing to chair.cook.ppm 13 8 14 14 8 14 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout index 58c019f98..987d9ef76 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:48:27 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -11,4 +11,4 @@ info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.066667 -Exiting @ tick 77521581000 because target called exit() +Exiting @ tick 77516381000 because target called exit() diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 68636d517..39e558e65 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.077516 # Nu sim_ticks 77516381000 # Number of ticks simulated final_tick 77516381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154118 # Simulator instruction rate (inst/s) -host_op_rate 154118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 31808931 # Simulator tick rate (ticks/s) -host_mem_usage 282024 # Number of bytes of host memory used -host_seconds 2436.94 # Real time elapsed on the host +host_inst_rate 222910 # Simulator instruction rate (inst/s) +host_op_rate 222910 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46007212 # Simulator tick rate (ticks/s) +host_mem_usage 236600 # Number of bytes of host memory used +host_seconds 1684.87 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 221184 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 255424 # Number of bytes read from this memory system.physmem.bytes_read::total 476608 # Number of bytes read from this memory @@ -250,6 +252,7 @@ system.membus.reqLayer0.occupancy 9290500 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 69562000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 50307155 # Number of BP lookups system.cpu.branchPred.condPredicted 29267262 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1212205 # Number of conditional branches incorrect @@ -582,6 +585,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1831.580097 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.894326 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.894326 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 336 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1334 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 100598535 # Number of tag accesses +system.cpu.icache.tags.data_accesses 100598535 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 50291612 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 50291612 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 50291612 # number of demand (read+write) hits @@ -670,6 +681,14 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.011362 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.090728 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.020184 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.122275 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4855 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 579 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4031 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148163 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 79325 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 79325 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 613 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 131 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 744 # number of ReadReq hits @@ -802,6 +821,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 3295.992263 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.804686 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.804686 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3402 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3117 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.830566 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 320069754 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 320069754 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 86510267 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 86510267 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73500882 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini index 9894abc48..edbb4f97d 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,26 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +108,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -111,11 +123,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +142,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +152,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr index 28eb1122e..abe1622a9 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr @@ -1,4 +1,3 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything @@ -50,4 +49,3 @@ Writing to chair.cook.ppm 13 8 14 14 8 14 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout index b09a5533b..e4df23735 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:53:14 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:48:27 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt index 721e957fa..2fdd2b1a5 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.199332 # Nu sim_ticks 199332411500 # Number of ticks simulated final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1715563 # Simulator instruction rate (inst/s) -host_op_rate 1715563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 857781835 # Simulator tick rate (ticks/s) -host_mem_usage 222488 # Number of bytes of host memory used -host_seconds 232.38 # Real time elapsed on the host +host_inst_rate 3310187 # Simulator instruction rate (inst/s) +host_op_rate 3310187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1655094150 # Simulator tick rate (ticks/s) +host_mem_usage 226700 # Number of bytes of host memory used +host_seconds 120.44 # Real time elapsed on the host sim_insts 398664595 # Number of instructions simulated sim_ops 398664595 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 1594658604 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 662449271 # Number of bytes read from this memory system.physmem.bytes_read::total 2257107875 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 13793364824 # To system.membus.throughput 13793364824 # Throughput (bytes/s) system.membus.data_through_bus 2749464673 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini index 17feee0a3..b264a599b 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -147,6 +165,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +174,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +189,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +217,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 @@ -207,11 +232,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +251,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +261,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr index 860580eeb..abe1622a9 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr @@ -49,4 +49,3 @@ Writing to chair.cook.ppm 13 8 14 14 8 14 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout index b94ac7377..ab67caf1c 100755 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:53:14 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:48:27 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 3ed6163c0..143a0b323 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.567335 # Nu sim_ticks 567335093000 # Number of ticks simulated final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1598767 # Simulator instruction rate (inst/s) -host_op_rate 1598767 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2275187152 # Simulator tick rate (ticks/s) -host_mem_usage 229960 # Number of bytes of host memory used -host_seconds 249.36 # Real time elapsed on the host +host_inst_rate 1478735 # Simulator instruction rate (inst/s) +host_op_rate 1478735 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2104370306 # Simulator tick rate (ticks/s) +host_mem_usage 235572 # Number of bytes of host memory used +host_seconds 269.60 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 205120 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory system.physmem.bytes_read::total 459136 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 7174000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -106,6 +109,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 85 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 251 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1375 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.929688 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 797333005 # Number of tag accesses +system.cpu.icache.tags.data_accesses 797333005 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits @@ -188,6 +200,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.115127 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4566 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 75 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 497 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3787 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.139343 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 75560 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 75560 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 468 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 591 # number of ReadReq hits @@ -320,6 +341,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini index 8cc45b24c..9e26a822b 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -514,6 +516,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -530,6 +533,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,7 +632,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon +executable=/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr index e8096c4c9..cce4a65d9 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr @@ -46,4 +46,3 @@ Writing to chair.cook.ppm 12 8 14 13 8 14 14 8 14 -hack: be nice to actually delete the event here diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout index d3e872fc3..704a64531 100755 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:05:47 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:48:11 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. info: Increasing stack size by one page. OO-style eon Time= 0.060000 -Exiting @ tick 68375005500 because target called exit() +Exiting @ tick 68509635500 because target called exit() diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 356503ef7..d1e8937b6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.068510 # Nu sim_ticks 68509635500 # Number of ticks simulated final_tick 68509635500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105106 # Simulator instruction rate (inst/s) -host_op_rate 134373 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26372946 # Simulator tick rate (ticks/s) -host_mem_usage 303620 # Number of bytes of host memory used -host_seconds 2597.72 # Real time elapsed on the host +host_inst_rate 157844 # Simulator instruction rate (inst/s) +host_op_rate 201796 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 39605771 # Simulator tick rate (ticks/s) +host_mem_usage 257252 # Number of bytes of host memory used +host_seconds 1729.79 # Real time elapsed on the host sim_insts 273036725 # Number of instructions simulated sim_ops 349064449 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 194560 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 272384 # Number of bytes read from this memory system.physmem.bytes_read::total 466944 # Number of bytes read from this memory @@ -257,6 +259,7 @@ system.membus.reqLayer0.occupancy 8937500 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 67899498 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 35425567 # Number of BP lookups system.cpu.branchPred.condPredicted 21222314 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1660593 # Number of conditional branches incorrect @@ -602,6 +605,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1848.251388 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.902466 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.902466 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1890 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 206 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1526 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.922852 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 75234453 # Number of tag accesses +system.cpu.icache.tags.data_accesses 75234453 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 37591948 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 37591948 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 37591948 # number of demand (read+write) hits @@ -690,6 +702,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.011566 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.085036 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.023692 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.120294 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5394 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 71 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1235 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4014 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.164612 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 180292 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 180292 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 12803 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 301 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13104 # number of ReadReq hits @@ -845,6 +866,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 3102.941006 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.757554 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.757554 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3197 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 684 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2446 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.780518 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 342019754 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 342019754 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 88929043 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 88929043 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82031381 # number of WriteReq hits diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini index 1c8f49cef..098c10a60 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,21 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -108,18 +117,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -129,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -143,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -160,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -169,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr index bf930ad43..a25196116 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr @@ -45,4 +45,3 @@ Writing to chair.cook.ppm 12 8 14 13 8 14 14 8 14 -hack: be nice to actually delete the event here diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout index 9c8ccea96..b3ebb4d02 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:21:07 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:52:31 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 590c33ff6..02fd51087 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.212344 # Nu sim_ticks 212344043000 # Number of ticks simulated final_tick 212344043000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1381175 # Simulator instruction rate (inst/s) -host_op_rate 1765765 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1074152891 # Simulator tick rate (ticks/s) -host_mem_usage 241892 # Number of bytes of host memory used -host_seconds 197.69 # Real time elapsed on the host +host_inst_rate 1679583 # Simulator instruction rate (inst/s) +host_op_rate 2147266 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1306228104 # Simulator tick rate (ticks/s) +host_mem_usage 246496 # Number of bytes of host memory used +host_seconds 162.56 # Real time elapsed on the host sim_insts 273037663 # Number of instructions simulated sim_ops 349065399 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 1394641404 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 480709268 # Number of bytes read from this memory system.physmem.bytes_read::total 1875350672 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 10715621794 # To system.membus.throughput 10715621794 # Throughput (bytes/s) system.membus.data_through_bus 2275398455 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini index f3f7cd9b4..aa5380744 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,18 +100,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -115,6 +126,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -123,6 +135,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -137,14 +150,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -163,12 +180,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -179,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -187,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -201,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -225,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/eon +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/eon gid=100 input=cin max_stack_size=67108864 @@ -239,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -256,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -265,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr index bf930ad43..a25196116 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr @@ -45,4 +45,3 @@ Writing to chair.cook.ppm 12 8 14 13 8 14 14 8 14 -hack: be nice to actually delete the event here diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout index b54aa45d0..32b55c30c 100755 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:19:15 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:52:55 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index 313988369..5bfa9270c 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.525834 # Nu sim_ticks 525834342000 # Number of ticks simulated final_tick 525834342000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 414348 # Simulator instruction rate (inst/s) -host_op_rate 529728 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 798851724 # Simulator tick rate (ticks/s) -host_mem_usage 248008 # Number of bytes of host memory used -host_seconds 658.24 # Real time elapsed on the host +host_inst_rate 870200 # Simulator instruction rate (inst/s) +host_op_rate 1112519 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1677723175 # Simulator tick rate (ticks/s) +host_mem_usage 255236 # Number of bytes of host memory used +host_seconds 313.42 # Real time elapsed on the host sim_insts 272739283 # Number of instructions simulated sim_ops 348687122 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 166976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 270272 # Number of bytes read from this memory system.physmem.bytes_read::total 437248 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 6832000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 61488000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -116,6 +119,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1765.993223 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862301 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862301 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1524 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.882324 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 697336303 # Number of tag accesses +system.cpu.icache.tags.data_accesses 697336303 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 348644747 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 348644747 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 348644747 # number of demand (read+write) hits @@ -198,6 +210,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.010425 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.106437 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4882 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1232 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3543 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148987 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 176386 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 176386 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 12994 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 13233 # number of ReadReq hits @@ -330,6 +351,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 3078.412981 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751566 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751566 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 677 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2428 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.768066 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 353296632 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 353296632 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 94570004 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 94570004 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 82049805 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini index 3613fc19c..328cf1d6a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,6 +533,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -550,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -566,6 +572,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -592,7 +599,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr index ca52b457d..b38cab2f9 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr @@ -4,4 +4,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(0, 1, ...) warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout index 091ca3b5c..722b9bf34 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 15 2013 18:56:50 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:50:38 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1387,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 631883288500 because target called exit() +Exiting @ tick 631518097500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 2a6478fe5..130b22828 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.631518 # Nu sim_ticks 631518097500 # Number of ticks simulated final_tick 631518097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 116160 # Simulator instruction rate (inst/s) -host_op_rate 116160 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40238771 # Simulator tick rate (ticks/s) -host_mem_usage 286040 # Number of bytes of host memory used -host_seconds 15694.27 # Real time elapsed on the host +host_inst_rate 171044 # Simulator instruction rate (inst/s) +host_op_rate 171044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59250964 # Simulator tick rate (ticks/s) +host_mem_usage 240608 # Number of bytes of host memory used +host_seconds 10658.36 # Real time elapsed on the host sim_insts 1823043370 # Number of instructions simulated sim_ops 1823043370 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 176128 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 30295488 # Number of bytes read from this memory system.physmem.bytes_read::total 30471616 # Number of bytes read from this memory @@ -314,6 +316,7 @@ system.membus.reqLayer0.occupancy 1230652000 # La system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 4488013500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 388926557 # Number of BP lookups system.cpu.branchPred.condPredicted 255987580 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 25808786 # Number of conditional branches incorrect @@ -646,6 +649,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1658.001589 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.809571 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.809571 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1713 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1567 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.836426 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 789856696 # Number of tag accesses +system.cpu.icache.tags.data_accesses 789856696 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 394910393 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 394910393 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 394910393 # number of demand (read+write) hits @@ -734,6 +745,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.040675 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001074 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.955840 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997589 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 188 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 505 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5021 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26866 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13650820 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13650820 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 7273 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1053738 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1061011 # number of ReadReq hits @@ -868,6 +888,15 @@ system.cpu.dcache.tags.warmup_cycle 408904250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4094.588575 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999655 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999655 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 284 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2365 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 392 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1343398986 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1343398986 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 458212871 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 458212871 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 209732941 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini index d4071b647..3b24ee769 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,26 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +108,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -111,11 +123,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +142,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +152,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr index 1c6544a2e..b38cab2f9 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr @@ -1,8 +1,6 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(0, 1, ...) warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout index 0011f9cf8..385d89721 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:53:14 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 17:53:08 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt index e66382473..65e54342a 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.004711 # Nu sim_ticks 1004710587000 # Number of ticks simulated final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3493388 # Simulator instruction rate (inst/s) -host_op_rate 3493388 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1747070946 # Simulator tick rate (ticks/s) -host_mem_usage 225488 # Number of bytes of host memory used -host_seconds 575.08 # Real time elapsed on the host +host_inst_rate 3768106 # Simulator instruction rate (inst/s) +host_op_rate 3768106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1884459398 # Simulator tick rate (ticks/s) +host_mem_usage 229696 # Number of bytes of host memory used +host_seconds 533.16 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 8037684280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 3569416716 # Number of bytes read from this memory system.physmem.bytes_read::total 11607100996 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 13131370496 # To system.membus.throughput 13131370496 # Throughput (bytes/s) system.membus.data_through_bus 13193226959 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini index d6223b426..34c972fc4 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -147,6 +165,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +174,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +189,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +217,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -207,11 +232,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +251,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +261,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr index ca52b457d..b38cab2f9 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr @@ -4,4 +4,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(0, 1, ...) warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout index a19734d3d..f48beb892 100755 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:53:14 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:02:12 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 421623453..068ca2e0b 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.769740 # Nu sim_ticks 2769739533000 # Number of ticks simulated final_tick 2769739533000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 892879 # Simulator instruction rate (inst/s) -host_op_rate 892879 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1230989339 # Simulator tick rate (ticks/s) -host_mem_usage 233984 # Number of bytes of host memory used -host_seconds 2250.01 # Real time elapsed on the host +host_inst_rate 1540787 # Simulator instruction rate (inst/s) +host_op_rate 1540787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2124243508 # Simulator tick rate (ticks/s) +host_mem_usage 238596 # Number of bytes of host memory used +host_seconds 1303.87 # Real time elapsed on the host sim_insts 2008987605 # Number of instructions simulated sim_ops 2008987605 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 137792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 30284544 # Number of bytes read from this memory system.physmem.bytes_read::total 30422336 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 1077521000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 4278141000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -114,6 +117,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1478.418050 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.721884 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.721884 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1428 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.756836 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4018852738 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4018852738 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 2009410475 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 2009410475 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 2009410475 # number of demand (read+write) hits @@ -196,6 +207,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.039688 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000809 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.957636 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.998134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32732 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1143 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31199 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.998901 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13642206 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13642206 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 8443 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1051869 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1060312 # number of ReadReq hits @@ -330,6 +350,15 @@ system.cpu.dcache.tags.warmup_cycle 1041395000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4095.197836 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 160 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 999 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2416 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1445259988 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1445259988 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 509611834 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 509611834 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 210722944 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini index cbb921be0..116b954da 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -514,6 +516,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -530,6 +533,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,7 +632,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk +executable=/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr index cba73e085..2de5e2759 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections warn: fcntl64(3, 2) passed through to host -hack: be nice to actually delete the event here diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout index 3ba2de45d..f17e243b1 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:40:46 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:55:24 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1385,4 +1385,4 @@ info: Increasing stack size by one page. 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 640648369500 because target called exit() +Exiting @ tick 629535413500 because target called exit() diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 6310afb8f..f4aa63ff2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.629535 # Nu sim_ticks 629535413500 # Number of ticks simulated final_tick 629535413500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71307 # Simulator instruction rate (inst/s) -host_op_rate 97111 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32426577 # Simulator tick rate (ticks/s) -host_mem_usage 303200 # Number of bytes of host memory used -host_seconds 19414.18 # Real time elapsed on the host +host_inst_rate 111054 # Simulator instruction rate (inst/s) +host_op_rate 151240 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 50501117 # Simulator tick rate (ticks/s) +host_mem_usage 257896 # Number of bytes of host memory used +host_seconds 12465.77 # Real time elapsed on the host sim_insts 1384370590 # Number of instructions simulated sim_ops 1885325342 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 155136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 30242496 # Number of bytes read from this memory system.physmem.bytes_read::total 30397632 # Number of bytes read from this memory @@ -305,6 +307,7 @@ system.membus.reqLayer0.occupancy 1215450500 # La system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 4442867738 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 438247561 # Number of BP lookups system.cpu.branchPred.condPredicted 350864310 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 30620817 # Number of conditional branches incorrect @@ -650,6 +653,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1641.273486 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.801403 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.801403 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1685 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1551 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.822754 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 669498564 # Number of tag accesses +system.cpu.icache.tags.data_accesses 669498564 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 334702534 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 334702534 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 334702534 # number of demand (read+write) hits @@ -738,6 +750,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.040208 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001578 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.955470 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997256 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32748 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 154 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 507 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5020 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26968 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999390 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13848752 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13848752 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 22592 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1058063 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1080655 # number of ReadReq hits @@ -897,6 +918,15 @@ system.cpu.dcache.tags.warmup_cycle 400505250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4094.376677 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999604 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999604 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 977 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 402 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1949922006 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1949922006 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 695282689 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 695282689 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276093049 # number of WriteReq hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini index 583a974bb..879581bbb 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,21 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -108,18 +117,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -129,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -143,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -160,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -169,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr index cba73e085..2de5e2759 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections warn: fcntl64(3, 2) passed through to host -hack: be nice to actually delete the event here diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout index 2dca8a365..6d065fef8 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:31:40 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 22:58:19 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index ae323b307..982d92f29 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.945613 # Nu sim_ticks 945613126000 # Number of ticks simulated final_tick 945613126000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1181509 # Simulator instruction rate (inst/s) -host_op_rate 1609052 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 807039161 # Simulator tick rate (ticks/s) -host_mem_usage 242488 # Number of bytes of host memory used -host_seconds 1171.71 # Real time elapsed on the host +host_inst_rate 1817390 # Simulator instruction rate (inst/s) +host_op_rate 2475033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1241382789 # Simulator tick rate (ticks/s) +host_mem_usage 247108 # Number of bytes of host memory used +host_seconds 761.74 # Real time elapsed on the host sim_insts 1384381606 # Number of instructions simulated sim_ops 1885336358 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 5561086004 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 2464405274 # Number of bytes read from this memory system.physmem.bytes_read::total 8025491278 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 9675679644 # To system.membus.throughput 9675679644 # Throughput (bytes/s) system.membus.data_through_bus 9149449674 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini index e7d15bd7c..0bdfc6610 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,18 +100,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -115,6 +126,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -123,6 +135,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -137,14 +150,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -163,12 +180,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -179,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -187,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -201,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -225,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/perlbmk gid=100 input=cin max_stack_size=67108864 @@ -239,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -256,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -265,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr index cba73e085..2de5e2759 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections warn: fcntl64(3, 2) passed through to host -hack: be nice to actually delete the event here diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout index 15b548e96..973b4e1bf 100755 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:11:37 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:11:12 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index 65ea4c6ca..ecd5fda89 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.326119 # Nu sim_ticks 2326118592000 # Number of ticks simulated final_tick 2326118592000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 481372 # Simulator instruction rate (inst/s) -host_op_rate 653016 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 810455855 # Simulator tick rate (ticks/s) -host_mem_usage 248632 # Number of bytes of host memory used -host_seconds 2870.14 # Real time elapsed on the host +host_inst_rate 968971 # Simulator instruction rate (inst/s) +host_op_rate 1314478 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1631393565 # Simulator tick rate (ticks/s) +host_mem_usage 255816 # Number of bytes of host memory used +host_seconds 1425.85 # Real time elapsed on the host sim_insts 1381604339 # Number of instructions simulated sim_ops 1874244941 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 113472 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 30232512 # Number of bytes read from this memory system.physmem.bytes_read::total 30345984 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 1069047000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 4267404000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -124,6 +127,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1392.317060 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679842 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679842 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1339 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.702637 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 2780562807 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2780562807 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1390251699 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1390251699 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1390251699 # number of demand (read+write) hits @@ -206,6 +216,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.039616 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000923 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.957169 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.997708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32743 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1387 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 31024 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999237 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 13744605 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 13744605 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 18030 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1054583 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1072613 # number of ReadReq hits @@ -340,6 +359,15 @@ system.cpu.dcache.tags.warmup_cycle 991199000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4094.947189 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999743 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 568 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1040 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2341 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1796115775 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1796115775 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 618874540 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 618874540 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 276862898 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index d10bd65d5..20b5204d0 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -120,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -136,6 +137,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -158,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -174,6 +177,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -183,6 +187,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -204,6 +209,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -220,6 +226,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -246,7 +253,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout index f56fe9b31..46359a0c9 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 09:55:43 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:16:43 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 43769191000 because target called exit() +Exiting @ tick 43690025000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index fc01eaffa..391c7c37b 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.043690 # Nu sim_ticks 43690025000 # Number of ticks simulated final_tick 43690025000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 91247 # Simulator instruction rate (inst/s) -host_op_rate 91247 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 45127446 # Simulator tick rate (ticks/s) -host_mem_usage 283120 # Number of bytes of host memory used -host_seconds 968.15 # Real time elapsed on the host +host_inst_rate 133116 # Simulator instruction rate (inst/s) +host_op_rate 133116 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65834414 # Simulator tick rate (ticks/s) +host_mem_usage 238716 # Number of bytes of host memory used +host_seconds 663.64 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory system.physmem.bytes_read::total 10592960 # Number of bytes read from this memory @@ -331,6 +333,7 @@ system.membus.reqLayer0.occupancy 1218631000 # La system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) system.membus.respLayer1.occupancy 1521663500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 18742723 # Number of BP lookups system.cpu.branchPred.condPredicted 12318363 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect @@ -442,6 +445,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1906.431852 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.930875 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.930875 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2046 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1090 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 24821911 # Number of tag accesses +system.cpu.icache.tags.data_accesses 24821911 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 12250505 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 12250505 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 12250505 # number of demand (read+write) hits @@ -550,6 +561,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.826966 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061272 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.054475 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.942712 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32060 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 137 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17071 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13589 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 108 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978394 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3980332 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3980332 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33055 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 112369 # number of ReadReq hits @@ -684,6 +704,13 @@ system.cpu.dcache.tags.warmup_cycle 297515000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4076.382661 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995211 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995211 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 922 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3118 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 69984376 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984376 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 20180292 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20180292 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13574591 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini index 08705e6b8..f15dfa96f 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,6 +533,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -550,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -566,6 +572,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -592,7 +599,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout index d12ffcc4f..86191115c 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:24:06 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 24977022500 because target called exit() +Exiting @ tick 24876941500 because target called exit() diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 63551bce4..629fb2f13 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.024877 # Nu sim_ticks 24876941500 # Number of ticks simulated final_tick 24876941500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131928 # Simulator instruction rate (inst/s) -host_op_rate 131928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41235030 # Simulator tick rate (ticks/s) -host_mem_usage 285168 # Number of bytes of host memory used -host_seconds 603.30 # Real time elapsed on the host +host_inst_rate 202143 # Simulator instruction rate (inst/s) +host_op_rate 202143 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63181048 # Simulator tick rate (ticks/s) +host_mem_usage 239772 # Number of bytes of host memory used +host_seconds 393.74 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 490624 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10154752 # Number of bytes read from this memory system.physmem.bytes_read::total 10645376 # Number of bytes read from this memory @@ -324,6 +326,7 @@ system.membus.reqLayer0.occupancy 1242193000 # La system.membus.reqLayer0.utilization 5.0 # Layer utilization (%) system.membus.respLayer1.occupancy 1539567000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 6.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 16535475 # Number of BP lookups system.cpu.branchPred.condPredicted 10680150 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 413128 # Number of conditional branches incorrect @@ -656,6 +659,15 @@ system.cpu.icache.tags.warmup_cycle 20019697250 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1926.124790 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.940491 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.940491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1531 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 359 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 27896466 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27896466 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 13794941 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 13794941 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 13794941 # number of demand (read+write) hits @@ -744,6 +756,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.803864 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064255 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.068608 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.936727 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32069 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1443 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 18046 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12352 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 61 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978668 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4053036 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4053036 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 86004 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 34262 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 120266 # number of ReadReq hits @@ -878,6 +899,13 @@ system.cpu.dcache.tags.warmup_cycle 220306250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4074.011744 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.994632 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.994632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1078 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2940 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 71186914 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71186914 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 20609776 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20609776 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 13574069 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini index c0c8f0dec..16ac17b8d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,26 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +108,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -111,11 +123,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +142,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +152,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr index 1ed796979..506aa6e28 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr @@ -1,7 +1,5 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout index 6c7ff5465..faff61794 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:03:40 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:27:58 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt index db9503e0b..35c792878 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.044221 # Nu sim_ticks 44221003000 # Number of ticks simulated final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2564036 # Simulator instruction rate (inst/s) -host_op_rate 2564035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1283487470 # Simulator tick rate (ticks/s) -host_mem_usage 224620 # Number of bytes of host memory used -host_seconds 34.45 # Real time elapsed on the host +host_inst_rate 3596409 # Simulator instruction rate (inst/s) +host_op_rate 3596407 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1800265277 # Simulator tick rate (ticks/s) +host_mem_usage 228820 # Number of bytes of host memory used +host_seconds 24.56 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 353752292 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 126702647 # Number of bytes read from this memory system.physmem.bytes_read::total 480454939 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 12937468537 # To system.membus.throughput 12937468537 # Throughput (bytes/s) system.membus.data_through_bus 572107835 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini index b1fb247dd..927fb8fa4 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -147,6 +165,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +174,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +189,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +217,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 @@ -207,11 +232,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +251,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +261,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout index f89175182..b6a75fdf5 100755 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:04:18 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:28:33 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index bac018361..dd1fcd980 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.133635 # Nu sim_ticks 133634727000 # Number of ticks simulated final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 775893 # Simulator instruction rate (inst/s) -host_op_rate 775893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1173708198 # Simulator tick rate (ticks/s) -host_mem_usage 233104 # Number of bytes of host memory used -host_seconds 113.86 # Real time elapsed on the host +host_inst_rate 1534458 # Simulator instruction rate (inst/s) +host_op_rate 1534458 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2321204993 # Simulator tick rate (ticks/s) +host_mem_usage 237688 # Number of bytes of host memory used +host_seconds 57.57 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 1190991000 # La system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -114,6 +117,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 176952584 # Number of tag accesses +system.cpu.icache.tags.data_accesses 176952584 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 88361638 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 88361638 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 88361638 # number of demand (read+write) hits @@ -196,6 +207,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9976 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3900109 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33258 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 102930 # number of ReadReq hits @@ -330,6 +350,13 @@ system.cpu.dcache.tags.warmup_cycle 936463000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini index 9b769867b..3a6f7de14 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -514,6 +516,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -530,6 +533,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,7 +632,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex +executable=/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout index 946783e23..51d96dffd 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:08:44 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:17:11 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 26765004500 because target called exit() +Exiting @ tick 26810051000 because target called exit() diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index df6074257..044953ad0 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.026810 # Nu sim_ticks 26810051000 # Number of ticks simulated final_tick 26810051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 86453 # Simulator instruction rate (inst/s) -host_op_rate 122688 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32687774 # Simulator tick rate (ticks/s) -host_mem_usage 303000 # Number of bytes of host memory used -host_seconds 820.19 # Real time elapsed on the host +host_inst_rate 140336 # Simulator instruction rate (inst/s) +host_op_rate 199155 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53060871 # Simulator tick rate (ticks/s) +host_mem_usage 257660 # Number of bytes of host memory used +host_seconds 505.27 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 100626876 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 299136 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7943232 # Number of bytes read from this memory system.physmem.bytes_read::total 8242368 # Number of bytes read from this memory @@ -333,6 +335,7 @@ system.membus.reqLayer0.occupancy 934752500 # La system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) system.membus.respLayer1.occupancy 1203686693 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.5 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 16646392 # Number of BP lookups system.cpu.branchPred.condPredicted 12773976 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 607235 # Number of conditional branches incorrect @@ -678,6 +681,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1808.840382 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.883223 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.883223 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2039 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1260 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 677 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 23425177 # Number of tag accesses +system.cpu.icache.tags.data_accesses 23425177 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 11662047 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 11662047 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 11662047 # number of demand (read+write) hits @@ -766,6 +777,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.813945 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041899 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.056290 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.912134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31104 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1849 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 20230 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 8498 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 395 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2814320 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2814320 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 25996 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 33476 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 59472 # number of ReadReq hits @@ -929,6 +949,13 @@ system.cpu.dcache.tags.warmup_cycle 363282250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4068.859504 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.993374 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.993374 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1767 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2268 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 92301717 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 92301717 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 26063246 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 26063246 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18266759 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini index 6172e5c1a..b4899830a 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,21 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -108,18 +117,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -129,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -143,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -160,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -169,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout index cdf0f47ec..fd88c13a1 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:45:30 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:25:48 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 9f4bab8c0..130b6bb56 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.053932 # Nu sim_ticks 53932157000 # Number of ticks simulated final_tick 53932157000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2080365 # Simulator instruction rate (inst/s) -host_op_rate 2952231 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1582195312 # Simulator tick rate (ticks/s) -host_mem_usage 241268 # Number of bytes of host memory used -host_seconds 34.09 # Real time elapsed on the host +host_inst_rate 1940189 # Simulator instruction rate (inst/s) +host_op_rate 2753308 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1475586020 # Simulator tick rate (ticks/s) +host_mem_usage 245844 # Number of bytes of host memory used +host_seconds 36.55 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 100632428 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory system.physmem.bytes_read::total 419153617 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 9230371187 # To system.membus.throughput 9230371187 # Throughput (bytes/s) system.membus.data_through_bus 497813828 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini index 5e9534bc1..8802837e9 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,18 +100,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -115,6 +126,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -123,6 +135,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -137,14 +150,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -163,12 +180,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -179,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -187,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -201,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -225,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/vortex +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -239,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -256,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -265,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout index 67309511e..89bb0e0aa 100755 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:31:35 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:26:35 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 178d6c7df..7d6b41b45 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.132689 # Nu sim_ticks 132689045000 # Number of ticks simulated final_tick 132689045000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 525201 # Simulator instruction rate (inst/s) -host_op_rate 744748 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 990262559 # Simulator tick rate (ticks/s) -host_mem_usage 247408 # Number of bytes of host memory used -host_seconds 133.99 # Real time elapsed on the host +host_inst_rate 1019812 # Simulator instruction rate (inst/s) +host_op_rate 1446120 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1922848599 # Simulator tick rate (ticks/s) +host_mem_usage 254584 # Number of bytes of host memory used +host_seconds 69.01 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 99791654 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 882993000 # La system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) system.membus.respLayer1.occupancy 1150308000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -124,6 +127,14 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1736.497265 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.847899 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.847899 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1755 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 156309046 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156309046 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits @@ -206,6 +217,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.846737 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035218 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.044809 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.926764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 428 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 10156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19788 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 616 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2689980 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits @@ -340,6 +360,13 @@ system.cpu.dcache.tags.warmup_cycle 1072595000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4076.954355 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995350 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995350 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 443 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3604 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 94204142 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 94204142 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 27087367 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27087367 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini index 0f57053cc..abfb7932e 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +eventq_index=0 +executable=/dist/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -111,11 +122,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +141,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +151,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr index 401e0da87..f7abb9a35 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr @@ -1,4 +1,3 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: ignoring syscall time(4026528248, 4026527848, ...) warn: ignoring syscall time(1375098, 4026527400, ...) @@ -561,4 +560,3 @@ warn: ignoring syscall time(4026526436, 4026525968, ...) warn: ignoring syscall time(7004192, 4026526056, ...) warn: ignoring syscall time(4, 4026527512, ...) warn: ignoring syscall time(0, 4026525760, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout index c44643a8d..9c35a9a4f 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:07:56 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:46:20 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt index 0c3e0f3fc..f2f248de4 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.068149 # Nu sim_ticks 68148672000 # Number of ticks simulated final_tick 68148672000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2813738 # Simulator instruction rate (inst/s) -host_op_rate 2850169 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1426739476 # Simulator tick rate (ticks/s) -host_mem_usage 233072 # Number of bytes of host memory used -host_seconds 47.77 # Real time elapsed on the host +host_inst_rate 3132375 # Simulator instruction rate (inst/s) +host_op_rate 3172933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1588309038 # Simulator tick rate (ticks/s) +host_mem_usage 237324 # Number of bytes of host memory used +host_seconds 42.91 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 538214280 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 147559360 # Number of bytes read from this memory system.physmem.bytes_read::total 685773640 # Number of bytes read from this memory @@ -38,6 +40,7 @@ system.physmem.bw_total::total 11381829862 # To system.membus.throughput 11383698247 # Throughput (bytes/s) system.membus.data_through_bus 775783918 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 136297345 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini index e7e0ce2f8..937ce3e41 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -147,6 +164,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +173,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +188,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +216,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex +eventq_index=0 +executable=/dist/cpu2000/binaries/sparc/linux/vortex gid=100 input=cin max_stack_size=67108864 @@ -207,11 +231,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +250,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +260,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr index bb51748c6..f7abb9a35 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr @@ -560,4 +560,3 @@ warn: ignoring syscall time(4026526436, 4026525968, ...) warn: ignoring syscall time(7004192, 4026526056, ...) warn: ignoring syscall time(4, 4026527512, ...) warn: ignoring syscall time(0, 4026525760, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout index 7747f2ffd..2ff984591 100755 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:10:51 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:47:13 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index b5bc877a9..7fe81f58a 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.202242 # Nu sim_ticks 202242260000 # Number of ticks simulated final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 788005 # Simulator instruction rate (inst/s) -host_op_rate 798208 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1185781953 # Simulator tick rate (ticks/s) -host_mem_usage 240044 # Number of bytes of host memory used -host_seconds 170.56 # Real time elapsed on the host +host_inst_rate 1441010 # Simulator instruction rate (inst/s) +host_op_rate 1459668 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2168416558 # Simulator tick rate (ticks/s) +host_mem_usage 246160 # Number of bytes of host memory used +host_seconds 93.27 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 877345000 # La system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls system.cpu.numCycles 404484520 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -82,6 +85,15 @@ system.cpu.icache.tags.warmup_cycle 143972294000 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 269294166 # Number of tag accesses +system.cpu.icache.tags.data_accesses 269294166 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 134366547 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 134366547 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 134366547 # number of demand (read+write) hits @@ -164,6 +176,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 30994 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 533 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12212 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17536 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 585 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945862 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3928089 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3928089 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits @@ -298,6 +319,13 @@ system.cpu.dcache.tags.warmup_cycle 769040000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini index cd7da392b..317ef3f76 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini @@ -120,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -136,6 +137,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -158,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -174,6 +177,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -183,6 +187,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -204,6 +209,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -220,6 +226,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -246,7 +253,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout index 037bfdea9..45898c91d 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:05:17 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:29:41 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -23,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 1017016979500 because target called exit() +Exiting @ tick 1009838214500 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt index 864d4a591..01fe4f841 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 1.009838 # Nu sim_ticks 1009838214500 # Number of ticks simulated final_tick 1009838214500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87394 # Simulator instruction rate (inst/s) -host_op_rate 87394 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 48496748 # Simulator tick rate (ticks/s) -host_mem_usage 275936 # Number of bytes of host memory used -host_seconds 20822.81 # Real time elapsed on the host +host_inst_rate 128161 # Simulator instruction rate (inst/s) +host_op_rate 128161 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 71119760 # Simulator tick rate (ticks/s) +host_mem_usage 230508 # Number of bytes of host memory used +host_seconds 14199.12 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125365056 # Number of bytes read from this memory system.physmem.bytes_read::total 125420032 # Number of bytes read from this memory @@ -325,6 +327,7 @@ system.membus.reqLayer0.occupancy 11785228500 # La system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) system.membus.respLayer1.occupancy 18364778000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 326538257 # Number of BP lookups system.cpu.branchPred.condPredicted 252572868 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 138234365 # Number of conditional branches incorrect @@ -436,6 +439,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 668.332859 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.326334 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.326334 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 858 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 785 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.418945 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 463858599 # Number of tag accesses +system.cpu.icache.tags.data_accesses 463858599 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 231927731 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 231927731 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 231927731 # number of demand (read+write) hits @@ -544,6 +553,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.455687 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.486850 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.943594 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29793 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 613 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 725 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12815 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15482 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909210 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 106291061 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106291061 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.data 6044291 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044291 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693280 # number of Writeback hits @@ -675,6 +693,14 @@ system.cpu.dcache.tags.warmup_cycle 12709353000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4082.357931 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.996669 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996669 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 590 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2876 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 593 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1219759777 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219759777 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 437268777 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437268777 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 156014425 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini index 3e178e75c..20db05a32 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,6 +533,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -550,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -566,6 +572,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -592,7 +599,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout index 3d7fe8a25..b7f8b903e 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout -Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 15 2013 19:07:40 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:30:51 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -25,4 +23,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 694171131000 because target called exit() +Exiting @ tick 685386545000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 29e4de429..09d12ecba 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.685387 # Nu sim_ticks 685386545000 # Number of ticks simulated final_tick 685386545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 111182 # Simulator instruction rate (inst/s) -host_op_rate 111182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 43894428 # Simulator tick rate (ticks/s) -host_mem_usage 276060 # Number of bytes of host memory used -host_seconds 15614.43 # Real time elapsed on the host +host_inst_rate 166100 # Simulator instruction rate (inst/s) +host_op_rate 166100 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 65575812 # Simulator tick rate (ticks/s) +host_mem_usage 231660 # Number of bytes of host memory used +host_seconds 10451.82 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 61760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125792064 # Number of bytes read from this memory system.physmem.bytes_read::total 125853824 # Number of bytes read from this memory @@ -326,6 +328,7 @@ system.membus.reqLayer0.occupancy 11873404000 # La system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) system.membus.respLayer1.occupancy 18493738500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 381642976 # Number of BP lookups system.cpu.branchPred.condPredicted 296606399 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 16082111 # Number of conditional branches incorrect @@ -657,6 +660,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 773.100738 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.377491 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.377491 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 782110757 # Number of tag accesses +system.cpu.icache.tags.data_accesses 782110757 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 391053395 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 391053395 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 391053395 # number of demand (read+write) hits @@ -745,6 +755,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.445145 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.513002 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.958966 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29778 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 594 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17297 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10763 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908752 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107098856 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107098856 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.data 6106330 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6106330 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3725230 # number of Writeback hits @@ -876,6 +895,14 @@ system.cpu.dcache.tags.warmup_cycle 5178034250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4087.561673 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997940 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997940 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 690 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2994 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 408 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1430860164 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1430860164 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 538716411 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 538716411 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 155539725 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini index 86a7050c2..6cbd45db6 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,26 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +108,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -111,11 +123,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +142,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +152,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr index 1ed796979..506aa6e28 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr @@ -1,7 +1,5 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout index 33b8f7ad8..1dfd46cbe 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:09:10 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:36:30 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt index 87abf8a8a..8ad24bba9 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.913189 # Nu sim_ticks 913189263000 # Number of ticks simulated final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4050769 # Simulator instruction rate (inst/s) -host_op_rate 4050768 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2032728095 # Simulator tick rate (ticks/s) -host_mem_usage 217548 # Number of bytes of host memory used -host_seconds 449.24 # Real time elapsed on the host +host_inst_rate 3833053 # Simulator instruction rate (inst/s) +host_op_rate 3833053 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1923475514 # Simulator tick rate (ticks/s) +host_mem_usage 220744 # Number of bytes of host memory used +host_seconds 474.76 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 7305514036 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1974795935 # Number of bytes read from this memory system.physmem.bytes_read::total 9280309971 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 11068994882 # To system.membus.throughput 11068994882 # Throughput (bytes/s) system.membus.data_through_bus 10108087278 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini index 482b126d1..2cb068091 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -147,6 +165,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +174,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +189,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +217,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -207,11 +232,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +251,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +261,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout index 154161af5..43eef16e9 100755 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:14:34 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 18:44:35 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 27c712d4a..894d37cbc 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.623386 # Nu sim_ticks 2623386226000 # Number of ticks simulated final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1731328 # Simulator instruction rate (inst/s) -host_op_rate 1731328 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2495874089 # Simulator tick rate (ticks/s) -host_mem_usage 225024 # Number of bytes of host memory used -host_seconds 1051.09 # Real time elapsed on the host +host_inst_rate 1625838 # Simulator instruction rate (inst/s) +host_op_rate 1625838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2343799751 # Simulator tick rate (ticks/s) +host_mem_usage 229480 # Number of bytes of host memory used +host_seconds 1119.29 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 51328 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125367104 # Number of bytes read from this memory system.physmem.bytes_read::total 125418432 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 11122356000 # La system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -114,6 +117,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 730 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.391113 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 3652757822 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3652757822 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1826377708 # number of demand (read+write) hits @@ -196,6 +205,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1059 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27303 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 106294313 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106294313 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.data 6044854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6044854 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3693497 # number of Writeback hits @@ -327,6 +345,15 @@ system.cpu.dcache.tags.warmup_cycle 40977439000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1238 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini index d4b45072d..c32ff375e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -514,6 +516,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -530,6 +533,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,7 +632,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 +executable=/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr index b4d96e4ea..5d8946ede 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr @@ -1,3 +1,2 @@ warn: Sockets disabled, not accepting gdb connections warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4] -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout index 7f1aa9216..aa09d1777 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:37:44 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:27:54 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -24,4 +24,4 @@ Uncompressing Data Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 541686426500 because target called exit() +Exiting @ tick 533797009000 because target called exit() diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 19d70b574..5e5db11e7 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.533797 # Nu sim_ticks 533797009000 # Number of ticks simulated final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102910 # Simulator instruction rate (inst/s) -host_op_rate 114803 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35565366 # Simulator tick rate (ticks/s) -host_mem_usage 295220 # Number of bytes of host memory used -host_seconds 15008.90 # Real time elapsed on the host +host_inst_rate 163502 # Simulator instruction rate (inst/s) +host_op_rate 182399 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56505895 # Simulator tick rate (ticks/s) +host_mem_usage 249880 # Number of bytes of host memory used +host_seconds 9446.75 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1723073835 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory @@ -327,6 +329,7 @@ system.membus.reqLayer0.occupancy 12926153000 # La system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 303451211 # Number of BP lookups system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect @@ -668,6 +671,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 754 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 726 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.368164 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 579143830 # Number of tag accesses +system.cpu.icache.tags.data_accesses 579143830 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits @@ -756,6 +766,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.436471 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000618 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.525223 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.962312 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29773 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1896 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23750 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3957 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908600 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 111203780 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 111203780 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 6288761 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6288789 # number of ReadReq hits @@ -899,6 +918,14 @@ system.cpu.dcache.tags.warmup_cycle 3547188250 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041920 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 642 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2397 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1056 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1355914350 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1355914350 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini index 4c52e043e..1a911e7c2 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,21 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -108,18 +117,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -129,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -143,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -160,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -169,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout index 836ec0832..922328096 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:33:02 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:35:09 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index c05db510c..de1eec5b4 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.861538 # Nu sim_ticks 861538200000 # Number of ticks simulated final_tick 861538200000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2812355 # Simulator instruction rate (inst/s) -host_op_rate 3137389 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1568696760 # Simulator tick rate (ticks/s) -host_mem_usage 234512 # Number of bytes of host memory used -host_seconds 549.21 # Real time elapsed on the host +host_inst_rate 2414882 # Simulator instruction rate (inst/s) +host_op_rate 2693979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1346991470 # Simulator tick rate (ticks/s) +host_mem_usage 238968 # Number of bytes of host memory used +host_seconds 639.60 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1723073853 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 9731209155 # To system.membus.throughput 9731209155 # Throughput (bytes/s) system.membus.data_through_bus 8383808419 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini index 0b3714a01..05924440e 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,18 +100,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -115,6 +126,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -123,6 +135,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -137,14 +150,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -163,12 +180,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -179,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -187,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -201,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -225,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -239,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -256,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -265,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout index 8e102e919..684ae1ce5 100755 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:46:27 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:38:44 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 0ee21876c..3ce47f2c9 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.391205 # Nu sim_ticks 2391205115000 # Number of ticks simulated final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 594937 # Simulator instruction rate (inst/s) -host_op_rate 663956 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 924522029 # Simulator tick rate (ticks/s) -host_mem_usage 240640 # Number of bytes of host memory used -host_seconds 2586.42 # Real time elapsed on the host +host_inst_rate 1202285 # Simulator instruction rate (inst/s) +host_op_rate 1341761 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1868329144 # Simulator tick rate (ticks/s) +host_mem_usage 247832 # Number of bytes of host memory used +host_seconds 1279.86 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1717270334 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory @@ -50,6 +52,7 @@ system.membus.reqLayer0.occupancy 11113556000 # La system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -124,6 +127,13 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses +system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits @@ -206,6 +216,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits @@ -340,6 +359,15 @@ system.cpu.dcache.tags.warmup_cycle 25914401000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini index 593d636da..40d9825c1 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -76,16 +81,19 @@ icache_port=system.membus.slave[1] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[4] @@ -93,6 +101,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -103,22 +112,26 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -128,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -142,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -159,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -168,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout index 5a2f2668d..ff491d90e 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:38:48 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 21:14:55 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt index 256e15dc9..5fca1ed49 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 2.846007 # Nu sim_ticks 2846007227500 # Number of ticks simulated final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1357896 # Simulator instruction rate (inst/s) -host_op_rate 2115724 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1284732870 # Simulator tick rate (ticks/s) -host_mem_usage 240864 # Number of bytes of host memory used -host_seconds 2215.25 # Real time elapsed on the host +host_inst_rate 1743046 # Simulator instruction rate (inst/s) +host_op_rate 2715824 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1649131867 # Simulator tick rate (ticks/s) +host_mem_usage 242928 # Number of bytes of host memory used +host_seconds 1725.76 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 32105863056 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5023868345 # Number of bytes read from this memory system.physmem.bytes_read::total 37129731401 # Number of bytes read from this memory @@ -36,6 +38,8 @@ system.physmem.bw_total::total 13588998587 # To system.membus.throughput 13588998587 # Throughput (bytes/s) system.membus.data_through_bus 38674388193 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 5692014456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini index 8de21ec08..5c76444e5 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -76,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -84,6 +91,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -98,18 +106,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -120,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -128,6 +141,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -142,12 +156,15 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -158,16 +175,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -178,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -186,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -200,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -224,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2 +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/bzip2 gid=100 input=cin max_stack_size=67108864 @@ -238,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -255,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -264,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout index 2a7659f1c..d2167f766 100755 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:55:52 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 21:25:13 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index f740c02c8..49729ff93 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 5.882581 # Nu sim_ticks 5882580526000 # Number of ticks simulated final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 876676 # Simulator instruction rate (inst/s) -host_op_rate 1365940 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1714420225 # Simulator tick rate (ticks/s) -host_mem_usage 249312 # Number of bytes of host memory used -host_seconds 3431.24 # Real time elapsed on the host +host_inst_rate 833754 # Simulator instruction rate (inst/s) +host_op_rate 1299064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1630482633 # Simulator tick rate (ticks/s) +host_mem_usage 251632 # Number of bytes of host memory used +host_seconds 3607.88 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 43200 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125326976 # Number of bytes read from this memory system.physmem.bytes_read::total 125370176 # Number of bytes read from this memory @@ -52,6 +54,8 @@ system.membus.reqLayer0.occupancy 11124698000 # La system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls system.cpu.numCycles 11765161052 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -86,6 +90,12 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 555.705054 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.271340 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.271340 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 665 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.324707 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 8026466441 # Number of tag accesses +system.cpu.icache.tags.data_accesses 8026466441 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 4013232208 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 4013232208 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 4013232208 # number of demand (read+write) hits @@ -168,6 +178,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.950203 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29783 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 996 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 743 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27921 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908905 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 106336271 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106336271 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.data 6045911 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6045911 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 3697956 # number of Writeback hits @@ -299,6 +318,15 @@ system.cpu.dcache.tags.warmup_cycle 58853922000 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index 8a347565f..1a6e862fe 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -120,6 +120,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -136,6 +137,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -158,6 +160,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -174,6 +177,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -183,6 +187,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -204,6 +209,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -220,6 +226,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -246,7 +253,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout index 27c876af5..66d60adf3 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:18:38 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:03:25 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 41671895000 because target called exit() +122 123 124 Exiting @ tick 41680207000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 5f89f07e5..3f6e9d455 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.041680 # Nu sim_ticks 41680207000 # Number of ticks simulated final_tick 41680207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 93645 # Simulator instruction rate (inst/s) -host_op_rate 93645 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42470141 # Simulator tick rate (ticks/s) -host_mem_usage 279708 # Number of bytes of host memory used -host_seconds 981.40 # Real time elapsed on the host +host_inst_rate 131207 # Simulator instruction rate (inst/s) +host_op_rate 131207 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59505524 # Simulator tick rate (ticks/s) +host_mem_usage 234284 # Number of bytes of host memory used +host_seconds 700.44 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory system.physmem.bytes_read::total 316032 # Number of bytes read from this memory @@ -243,6 +245,7 @@ system.membus.reqLayer0.occupancy 5775000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 45973500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 13412627 # Number of BP lookups system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect @@ -354,6 +357,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1492.182806 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.728605 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.728605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 959 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 19923420 # Number of tag accesses +system.cpu.icache.tags.data_accesses 19923420 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits @@ -462,6 +474,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055565 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3282 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 168 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2213 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.100159 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 99830 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 99830 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits @@ -594,6 +615,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1441.367780 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351896 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351896 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 211 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 403 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 19995621 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995621 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6492829 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini index 201e62f46..78509c3e8 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -504,6 +506,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -520,6 +523,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -529,6 +533,7 @@ eventq_index=0 [system.cpu.isa] type=AlphaISA eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB @@ -550,6 +555,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -566,6 +572,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -592,7 +599,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout index 2fe61da2d..c12c73ccb 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 15 2013 18:24:51 -gem5 started Oct 16 2013 01:34:33 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:15:16 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -21,4 +23,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 23492267500 because target called exit() +122 123 124 Exiting @ tick 23461709500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index 445692444..b0acaf58e 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.023462 # Nu sim_ticks 23461709500 # Number of ticks simulated final_tick 23461709500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 127245 # Simulator instruction rate (inst/s) -host_op_rate 127245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 35464472 # Simulator tick rate (ticks/s) -host_mem_usage 280732 # Number of bytes of host memory used -host_seconds 661.56 # Real time elapsed on the host +host_inst_rate 186682 # Simulator instruction rate (inst/s) +host_op_rate 186682 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 52030153 # Simulator tick rate (ticks/s) +host_mem_usage 235304 # Number of bytes of host memory used +host_seconds 450.93 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 195968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 138624 # Number of bytes read from this memory system.physmem.bytes_read::total 334592 # Number of bytes read from this memory @@ -244,6 +246,7 @@ system.membus.reqLayer0.occupancy 6831000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 49012250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 14847721 # Number of BP lookups system.cpu.branchPred.condPredicted 10774921 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 922205 # Number of conditional branches incorrect @@ -576,6 +579,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1596.482984 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.779533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.779533 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1934 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 766 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 924 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.944336 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 29479830 # Number of tag accesses +system.cpu.icache.tags.data_accesses 29479830 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 14719872 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 14719872 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 14719872 # number of demand (read+write) hits @@ -664,6 +676,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061354 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.011641 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.073535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3590 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 910 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2431 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109558 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 116249 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 116249 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 8448 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8503 # number of ReadReq hits @@ -796,6 +817,14 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1459.152638 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.356238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.356238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 56179001 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 56179001 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 21586035 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 21586035 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6492869 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini index 04249e1da..b06f5d885 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,26 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +108,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -111,11 +123,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +142,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +152,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr index 1ed796979..506aa6e28 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr @@ -1,7 +1,5 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout index 508377532..53155afb5 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:32:22 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:22:57 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 31612b0d4..69d43d9de 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3944537 # Simulator instruction rate (inst/s) -host_op_rate 3944535 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1972268010 # Simulator tick rate (ticks/s) -host_mem_usage 220188 # Number of bytes of host memory used -host_seconds 23.30 # Real time elapsed on the host +host_inst_rate 2604589 # Simulator instruction rate (inst/s) +host_op_rate 2604587 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1302294342 # Simulator tick rate (ticks/s) +host_mem_usage 224388 # Number of bytes of host memory used +host_seconds 35.29 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 11030545389 # To system.membus.throughput 11030545389 # Throughput (bytes/s) system.membus.data_through_bus 506870851 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini index 2ef8f2342..3fa897910 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=AlphaTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,23 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=AlphaInterrupts +eventq_index=0 [system.cpu.isa] type=AlphaISA +eventq_index=0 +system=system [system.cpu.itb] type=AlphaTLB +eventq_index=0 size=48 [system.cpu.l2cache] @@ -147,6 +165,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +174,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +189,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +207,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +217,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 @@ -207,11 +232,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +251,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +261,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr index 1b49765a7..506aa6e28 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr @@ -3,4 +3,3 @@ warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: Prefetch instructions in Alpha do not do anything warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout index b809995e1..078852d80 100755 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 24 2013 03:08:53 -gem5 started Sep 28 2013 10:32:58 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 16:27:55 +gem5 started Jan 22 2014 19:23:43 +gem5 executing on u200540-lin command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav +Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index be0605d18..d8a9ee89f 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.118729 # Nu sim_ticks 118729316000 # Number of ticks simulated final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2022504 # Simulator instruction rate (inst/s) -host_op_rate 2022504 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2612866318 # Simulator tick rate (ticks/s) -host_mem_usage 228676 # Number of bytes of host memory used -host_seconds 45.44 # Real time elapsed on the host +host_inst_rate 1382014 # Simulator instruction rate (inst/s) +host_op_rate 1382013 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1785419086 # Simulator tick rate (ticks/s) +host_mem_usage 233256 # Number of bytes of host memory used +host_seconds 66.50 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory system.physmem.bytes_read::total 304960 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 4765000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv @@ -106,6 +109,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 585 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 953 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses +system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -188,6 +200,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.063296 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3109 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 703 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 91577 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 91577 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 5889 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5942 # number of ReadReq hits @@ -320,6 +341,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini index 90382fb26..69c7d8edb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini @@ -159,6 +159,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -175,6 +176,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -514,6 +516,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -530,6 +533,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,7 +632,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf +executable=/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout index 5ce7704c2..6ec033969 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:36:42 -gem5 started Oct 16 2013 02:15:41 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 22 2014 23:45:59 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav +Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -21,4 +23,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 74201024500 because target called exit() +122 123 124 Exiting @ tick 74219948500 because target called exit() diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index ac21abc99..3723ab1c1 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.074220 # Nu sim_ticks 74219948500 # Number of ticks simulated final_tick 74219948500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84730 # Simulator instruction rate (inst/s) -host_op_rate 92772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 36497737 # Simulator tick rate (ticks/s) -host_mem_usage 298520 # Number of bytes of host memory used -host_seconds 2033.55 # Real time elapsed on the host +host_inst_rate 133200 # Simulator instruction rate (inst/s) +host_op_rate 145842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57376166 # Simulator tick rate (ticks/s) +host_mem_usage 253176 # Number of bytes of host memory used +host_seconds 1293.57 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 188656503 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 131072 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 111680 # Number of bytes read from this memory system.physmem.bytes_read::total 242752 # Number of bytes read from this memory @@ -237,6 +239,7 @@ system.membus.reqLayer0.occupancy 4682500 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 35532750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 94784274 # Number of BP lookups system.cpu.branchPred.condPredicted 74784006 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 6281562 # Number of conditional branches incorrect @@ -581,6 +584,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1347.740549 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.658076 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.658076 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1731 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 544 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 27 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1037 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.845215 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 73705913 # Number of tag accesses +system.cpu.icache.tags.data_accesses 73705913 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 36845557 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 36845557 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 36845557 # number of demand (read+write) hits @@ -669,6 +681,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000152 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043505 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.016384 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.060042 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2732 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 604 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1970 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.083374 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 51779 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 51779 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2073 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2161 # number of ReadReq hits @@ -810,6 +831,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1406.103135 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.343287 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.343287 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1795 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 353 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1378 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.438232 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 93593418 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 93593418 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 34384711 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 34384711 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12356564 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini index 46e3b79d7..0b27d47af 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -75,21 +80,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[4] [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -108,18 +117,21 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -129,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -143,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -160,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -169,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout index debc9398c..3a7a72087 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simout -Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 08:16:29 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 23 2014 00:00:14 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 24cdef337..c33d29231 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.103107 # Nu sim_ticks 103106766000 # Number of ticks simulated final_tick 103106766000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2813934 # Simulator instruction rate (inst/s) -host_op_rate 3080985 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1683727447 # Simulator tick rate (ticks/s) -host_mem_usage 236772 # Number of bytes of host memory used -host_seconds 61.24 # Real time elapsed on the host +host_inst_rate 2018881 # Simulator instruction rate (inst/s) +host_op_rate 2210479 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1208004529 # Simulator tick rate (ticks/s) +host_mem_usage 241364 # Number of bytes of host memory used +host_seconds 85.35 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 188670891 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory system.physmem.bytes_read::total 869973865 # Number of bytes read from this memory @@ -36,6 +38,7 @@ system.physmem.bw_total::total 8876496088 # To system.membus.throughput 8876496088 # Throughput (bytes/s) system.membus.data_through_bus 915226805 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini index beab37699..a68b7deda 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,18 +100,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -115,6 +126,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -123,6 +135,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -137,14 +150,18 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -163,12 +180,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -179,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -187,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -201,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -216,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -225,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/arm/linux/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/arm/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -239,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -256,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -265,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout index 559353937..50f61b81e 100755 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simout -Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 07:58:15 -gem5 started Sep 22 2013 09:33:12 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:24:06 +gem5 started Jan 23 2014 00:01:50 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 3a3e9e512..daccb0e4d 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.232072 # Nu sim_ticks 232072304000 # Number of ticks simulated final_tick 232072304000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 705973 # Simulator instruction rate (inst/s) -host_op_rate 773116 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 953412259 # Simulator tick rate (ticks/s) -host_mem_usage 242928 # Number of bytes of host memory used -host_seconds 243.41 # Real time elapsed on the host +host_inst_rate 1248624 # Simulator instruction rate (inst/s) +host_op_rate 1367377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1686259354 # Simulator tick rate (ticks/s) +host_mem_usage 250108 # Number of bytes of host memory used +host_seconds 137.63 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 188185920 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory system.physmem.bytes_read::total 220992 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 3453000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 31077000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -116,6 +119,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1147.986161 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.560540 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560540 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 379723155 # Number of tag accesses +system.cpu.icache.tags.data_accesses 379723155 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits @@ -198,6 +210,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 42317 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 42317 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1322 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 57 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1379 # number of ReadReq hits @@ -330,6 +351,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1363.611259 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332913 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332913 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 84020083 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84020083 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 29599357 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 29599357 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini index 450711784..ead3fce75 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -74,20 +79,25 @@ icache_port=system.membus.slave[1] [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -97,7 +107,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -111,11 +122,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -128,6 +141,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -137,5 +151,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr index 7edd901b2..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr @@ -1,3 +1 @@ -warn: CoherentBus system.membus has no snooping ports attached! warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout index 1f1c88e44..522507bd6 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:10:38 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:48:57 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 806cadbfa..b414e1534 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 3763101 # Simulator instruction rate (inst/s) -host_op_rate 3763105 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1881563141 # Simulator tick rate (ticks/s) -host_mem_usage 229516 # Number of bytes of host memory used -host_seconds 51.41 # Real time elapsed on the host +host_inst_rate 2588672 # Simulator instruction rate (inst/s) +host_op_rate 2588674 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1294344494 # Simulator tick rate (ticks/s) +host_mem_usage 233760 # Number of bytes of host memory used +host_seconds 74.73 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory @@ -38,6 +40,7 @@ system.physmem.bw_total::total 11055401229 # To system.membus.throughput 11057254439 # Throughput (bytes/s) system.membus.data_through_bus 1069490213 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 193445891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini index bac902cb5..5f60b5786 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -71,6 +76,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -79,6 +85,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -93,11 +100,14 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.icache] @@ -106,6 +116,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -114,6 +125,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -128,17 +140,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=SparcInterrupts +eventq_index=0 [system.cpu.isa] type=SparcISA +eventq_index=0 [system.cpu.itb] type=SparcTLB +eventq_index=0 size=64 [system.cpu.l2cache] @@ -147,6 +164,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -155,6 +173,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -169,12 +188,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -184,6 +206,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -193,7 +216,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/sparc/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -207,11 +231,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -224,6 +250,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -233,5 +260,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout index 139366506..cbae3bd7a 100755 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simout -Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 22 2013 06:07:13 -gem5 started Sep 22 2013 06:08:55 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:04:27 +gem5 started Jan 22 2014 19:50:23 +gem5 executing on u200540-lin command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav Couldn't unlink build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2 diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 471075dde..4c0f0b47e 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.270563 # Nu sim_ticks 270563082000 # Number of ticks simulated final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 872463 # Simulator instruction rate (inst/s) -host_op_rate 872464 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1220278409 # Simulator tick rate (ticks/s) -host_mem_usage 236504 # Number of bytes of host memory used -host_seconds 221.72 # Real time elapsed on the host +host_inst_rate 1313314 # Simulator instruction rate (inst/s) +host_op_rate 1313315 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1836878526 # Simulator tick rate (ticks/s) +host_mem_usage 242660 # Number of bytes of host memory used +host_seconds 147.30 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory system.physmem.bytes_read::total 331072 # Number of bytes read from this memory @@ -42,6 +44,7 @@ system.membus.reqLayer0.occupancy 5173000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls system.cpu.numCycles 541126164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -74,6 +77,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 624 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 514 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 687 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses +system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -156,6 +168,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.081736 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4097 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 625 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 116103 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 116103 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 8691 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 8691 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 2 # number of Writeback hits @@ -283,6 +304,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini index 210f89c36..e8d7fb666 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini @@ -165,6 +165,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -181,6 +182,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] @@ -520,6 +522,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -536,6 +539,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] @@ -584,6 +588,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -600,6 +605,7 @@ block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] @@ -626,7 +632,7 @@ env= errout=cerr euid=100 eventq_index=0 -executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf +executable=/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout index 607420641..1e66bd991 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:39:37 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 21:43:52 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -22,4 +24,4 @@ info: Increasing stack size by one page. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 144337151000 because target called exit() +122 123 124 Exiting @ tick 144463317000 because target called exit() diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 3f8722e89..1427887bb 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.144463 # Nu sim_ticks 144463317000 # Number of ticks simulated final_tick 144463317000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55445 # Simulator instruction rate (inst/s) -host_op_rate 92931 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60647702 # Simulator tick rate (ticks/s) -host_mem_usage 328672 # Number of bytes of host memory used -host_seconds 2382.01 # Real time elapsed on the host +host_inst_rate 81167 # Simulator instruction rate (inst/s) +host_op_rate 136043 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88782348 # Simulator tick rate (ticks/s) +host_mem_usage 282908 # Number of bytes of host memory used +host_seconds 1627.16 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 217088 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 125568 # Number of bytes read from this memory system.physmem.bytes_read::total 342656 # Number of bytes read from this memory @@ -251,6 +253,7 @@ system.membus.reqLayer0.occupancy 6950000 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 50662837 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 18648233 # Number of BP lookups system.cpu.branchPred.condPredicted 18648233 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1490176 # Number of conditional branches incorrect @@ -260,6 +263,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 94.591126 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1320367 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 22841 # Number of incorrect RAS predictions. +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 289221873 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -552,6 +556,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1619.938452 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.790986 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.790986 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1967 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 185 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 767 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.960449 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 44713203 # Number of tag accesses +system.cpu.icache.tags.data_accesses 44713203 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 22344300 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 22344300 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 22344300 # number of demand (read+write) hits @@ -640,6 +653,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000053 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.068064 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.009517 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.077634 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3826 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 876 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 145 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2560 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.116760 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 75773 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 75773 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 3227 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 36 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3263 # number of ReadReq hits @@ -786,6 +808,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1438.861304 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.351284 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.351284 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1947 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1395 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.475342 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 132211530 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 132211530 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 45588097 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 45588097 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514029 # number of WriteReq hits diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini index a8660b22e..4ce0c4345 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -76,16 +81,19 @@ icache_port=system.membus.slave[1] type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[4] @@ -93,6 +101,7 @@ port=system.membus.slave[4] [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -103,22 +112,26 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.membus.slave[3] [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -128,7 +141,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -142,11 +156,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -159,6 +175,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -168,5 +185,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout index 61953e3fc..45d32ca68 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:46:06 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 22:11:10 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index 30630542a..bc7c5407d 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1210449 # Simulator instruction rate (inst/s) -host_op_rate 2028822 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1204235272 # Simulator tick rate (ticks/s) -host_mem_usage 265804 # Number of bytes of host memory used -host_seconds 109.11 # Real time elapsed on the host +host_inst_rate 1414135 # Simulator instruction rate (inst/s) +host_op_rate 2370219 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1406875667 # Simulator tick rate (ticks/s) +host_mem_usage 267896 # Number of bytes of host memory used +host_seconds 93.39 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory @@ -36,6 +38,8 @@ system.physmem.bw_total::total 13685638205 # To system.membus.throughput 13685638205 # Throughput (bytes/s) system.membus.data_through_bus 1798200879 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 262786559 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini index 00a43a175..b3c95dee1 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=false +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -12,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain boot_osflags=a cache_line_size=64 clk_domain=system.clk_domain +eventq_index=0 init_param=0 kernel= load_addr_mask=1099511627775 @@ -33,6 +36,7 @@ system_port=system.membus.slave[0] [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -45,6 +49,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts @@ -69,6 +74,7 @@ icache_port=system.cpu.icache.cpu_side type=DerivedClockDomain clk_divider=16 clk_domain=system.cpu_clk_domain +eventq_index=0 [system.cpu.dcache] type=BaseCache @@ -76,6 +82,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -84,6 +91,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=262144 system=system tags=system.cpu.dcache.tags @@ -98,18 +106,22 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=262144 [system.cpu.dtb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[3] @@ -120,6 +132,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -128,6 +141,7 @@ mshrs=4 prefetch_on_access=false prefetcher=Null response_latency=2 +sequential_access=false size=131072 system=system tags=system.cpu.icache.tags @@ -142,12 +156,15 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 +sequential_access=false size=131072 [system.cpu.interrupts] type=X86LocalApic clk_domain=system.cpu.apic_clk_domain +eventq_index=0 int_latency=1000 pio_addr=2305843009213693952 pio_latency=100000 @@ -158,16 +175,19 @@ pio=system.membus.master[1] [system.cpu.isa] type=X86ISA +eventq_index=0 [system.cpu.itb] type=X86TLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=X86PagetableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=4 system=system port=system.cpu.toL2Bus.slave[2] @@ -178,6 +198,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -186,6 +207,7 @@ mshrs=20 prefetch_on_access=false prefetcher=Null response_latency=20 +sequential_access=false size=2097152 system=system tags=system.cpu.l2cache.tags @@ -200,12 +222,15 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 +sequential_access=false size=2097152 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -215,6 +240,7 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu.workload] type=LiveProcess @@ -224,7 +250,8 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/cpu2000/binaries/x86/linux/twolf +eventq_index=0 +executable=/dist/cpu2000/binaries/x86/linux/twolf gid=100 input=cin max_stack_size=67108864 @@ -238,11 +265,13 @@ uid=100 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.membus] type=CoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -255,6 +284,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=true +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -264,5 +294,6 @@ port=system.membus.master[0] [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr index e45cd058f..1a4f96712 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr @@ -1,2 +1 @@ warn: Sockets disabled, not accepting gdb connections -hack: be nice to actually delete the event here diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout index b436e7f9e..cc37865c7 100755 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout @@ -1,10 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 16 2013 01:35:57 -gem5 started Oct 16 2013 01:51:48 -gem5 executing on zizzer +gem5 compiled Jan 22 2014 17:10:34 +gem5 started Jan 22 2014 22:12:53 +gem5 executing on u200540-lin command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav +Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index 9cfd1bb27..2eac3bbbe 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,13 +4,15 @@ sim_seconds 0.250954 # Nu sim_ticks 250953957000 # Number of ticks simulated final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 789102 # Simulator instruction rate (inst/s) -host_op_rate 1322606 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1499404446 # Simulator tick rate (ticks/s) -host_mem_usage 274284 # Number of bytes of host memory used -host_seconds 167.37 # Real time elapsed on the host +host_inst_rate 770398 # Simulator instruction rate (inst/s) +host_op_rate 1291257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1463865173 # Simulator tick rate (ticks/s) +host_mem_usage 276604 # Number of bytes of host memory used +host_seconds 171.43 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory system.physmem.bytes_read::total 303040 # Number of bytes read from this memory @@ -44,6 +46,8 @@ system.membus.reqLayer0.occupancy 4753500 # La system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.numCycles 501907914 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -78,6 +82,15 @@ system.cpu.icache.tags.warmup_cycle 0 # Cy system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 498 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 394 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 869 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 346993430 # Number of tag accesses +system.cpu.icache.tags.data_accesses 346993430 # Number of data accesses system.cpu.icache.ReadReq_hits::cpu.inst 173489674 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489674 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489674 # number of demand (read+write) hits @@ -160,6 +173,15 @@ system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.062811 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3164 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 513 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 516 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 57590 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 57590 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1854 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 7 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1861 # number of ReadReq hits @@ -292,6 +314,15 @@ system.cpu.dcache.tags.warmup_cycle 0 # Cy system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits |