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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-10 06:46:20 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-10 06:46:20 -0500 |
| commit | 247e4e9ab41bafcfcbde725bb40e6a7b5628f1de (patch) | |
| tree | b4312f540772ef437b5b962cc1fff4bb54d90ce4 /tests/long | |
| parent | d32ee94231251b8d07bb811142f6759f8655962b (diff) | |
| download | gem5-247e4e9ab41bafcfcbde725bb40e6a7b5628f1de.tar.xz | |
stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
Diffstat (limited to 'tests/long')
4 files changed, 1258 insertions, 1361 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats index ab98339a8..e65bdafa7 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats @@ -1,26 +1,24 @@ -Real time: May/15/2013 12:08:23 +Real time: Jun/08/2013 21:48:44 Profiler Stats -------------- -Elapsed_time_in_seconds: 796 -Elapsed_time_in_minutes: 13.2667 -Elapsed_time_in_hours: 0.221111 -Elapsed_time_in_days: 0.00921296 +Elapsed_time_in_seconds: 452 +Elapsed_time_in_minutes: 7.53333 +Elapsed_time_in_hours: 0.125556 +Elapsed_time_in_days: 0.00523148 -Virtual_time_in_seconds: 792.33 -Virtual_time_in_minutes: 13.2055 -Virtual_time_in_hours: 0.220092 -Virtual_time_in_days: 0.00917049 +Virtual_time_in_seconds: 451.44 +Virtual_time_in_minutes: 7.524 +Virtual_time_in_hours: 0.1254 +Virtual_time_in_days: 0.005225 -Ruby_current_time: 10410297758 +Ruby_current_time: 10410298653 Ruby_start_time: 0 -Ruby_cycles: 10410297758 +Ruby_cycles: 10410298653 -mbytes_resident: 606.461 -mbytes_total: 851.852 -resident_ratio: 0.711942 - -ruby_cycles_executed: [ 10410297759 10410297759 ] +mbytes_resident: 603.562 +mbytes_total: 845.523 +resident_ratio: 0.713842 Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 @@ -30,18 +28,18 @@ DMA-0:0 Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151886718 average: 1.00011 | standard deviation: 0.0104983 | 0 151869977 16741 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151894334 average: 1.00011 | standard deviation: 0.010498 | 0 151877593 16741 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 270 count: 151886717 average: 3.45795 | standard deviation: 5.18215 | 0 149232339 0 0 0 0 0 0 0 967168 602 1434707 493 54299 574 16370 170 112 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3741 6150 8984 10304 51755 196 509 88 111 143 4 23 9 11 17 5 17 5 8 27 4 15 2 9 6 9 472 4506 10321 18243 13984 43613 883 877 2441 340 822 17 25 50 17 23 15 17 60 7 30 13 21 47 21 27 9 21 24 90 134 133 147 269 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_LD: [binsize: 2 max: 216 count: 14872957 average: 5.10751 | standard deviation: 8.69983 | 0 13484012 0 0 0 0 0 0 0 129492 97 1200237 320 19353 366 4823 123 70 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 919 791 3671 3477 2370 72 98 38 42 34 2 3 2 5 2 3 1 0 2 0 1 4 1 3 1 5 6 1421 2829 4534 6423 5889 348 264 260 122 133 10 9 4 7 1 7 4 5 1 6 6 4 4 8 6 4 10 4 25 22 57 48 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST: [binsize: 2 max: 270 count: 9468113 average: 5.20871 | standard deviation: 15.524 | 0 9118662 0 0 0 0 0 0 0 27223 26 178592 96 14286 118 1530 29 18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 770 3337 3846 6346 49267 90 393 32 59 105 1 20 4 2 15 2 13 3 2 21 2 9 0 4 4 3 465 1055 3041 9490 7168 37336 375 495 2067 204 683 2 13 45 6 20 6 10 50 5 24 6 14 40 6 18 3 9 17 31 81 62 93 235 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH: [binsize: 2 max: 214 count: 126376928 average: 3.11849 | standard deviation: 2.02507 | 0 125564891 0 0 0 0 0 0 0 794588 449 385 48 51 21 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1937 1912 1006 41 48 20 17 14 2 3 1 0 2 3 0 0 3 2 2 6 1 2 1 1 0 1 1 2014 4386 4163 214 182 154 101 111 7 3 5 3 1 4 2 2 3 5 1 0 1 3 3 7 3 1 2 3 33 29 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_RMW_Read: [binsize: 2 max: 215 count: 490895 average: 6.04017 | standard deviation: 9.43848 | 0 425774 0 0 0 0 0 0 0 10405 25 32646 14 12062 22 8519 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86 87 389 392 44 14 0 4 7 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 9 45 16 122 165 3 12 1 6 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 338912 average: 5.45579 | standard deviation: 7.80876 | 0 300088 0 0 0 0 0 0 0 5460 5 22847 15 8547 47 1498 13 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 23 72 48 26 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 7 20 40 57 41 3 5 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338912 average: 3 | standard deviation: 0 | 0 0 0 338912 ] -miss_latency_NULL: [binsize: 2 max: 270 count: 151886717 average: 3.45795 | standard deviation: 5.18215 | 0 149232339 0 0 0 0 0 0 0 967168 602 1434707 493 54299 574 16370 170 112 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3741 6150 8984 10304 51755 196 509 88 111 143 4 23 9 11 17 5 17 5 8 27 4 15 2 9 6 9 472 4506 10321 18243 13984 43613 883 877 2441 340 822 17 25 50 17 23 15 17 60 7 30 13 21 47 21 27 9 21 24 90 134 133 147 269 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 273 count: 151894333 average: 3.45796 | standard deviation: 5.18178 | 0 149239567 0 0 0 0 0 0 0 967464 591 1434698 471 54488 562 16355 155 88 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3746 6141 8990 10313 51758 198 522 84 112 132 6 26 8 7 13 3 10 5 5 28 6 18 2 7 7 8 479 4505 10311 18263 13957 43735 864 879 2392 323 819 20 28 57 18 19 14 12 60 8 31 14 18 43 23 32 13 29 21 85 141 121 139 253 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 220 count: 14873782 average: 5.10749 | standard deviation: 8.69963 | 0 13484760 0 0 0 0 0 0 0 129532 100 1200232 299 19462 338 4825 113 55 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 925 785 3670 3475 2363 76 103 37 42 35 3 4 3 3 1 2 1 0 2 1 2 3 1 3 1 4 8 1414 2823 4592 6409 5895 325 281 248 108 123 9 10 5 12 3 3 0 6 2 7 7 2 8 9 8 8 12 4 27 22 46 51 30 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 273 count: 9469041 average: 5.2084 | standard deviation: 15.5209 | 0 9119543 0 0 0 0 0 0 0 27234 17 178584 110 14328 126 1523 26 15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 767 3342 3842 6354 49276 86 397 33 58 94 2 21 3 2 12 1 7 2 2 22 3 13 1 3 4 2 469 1037 3063 9469 7160 37435 384 483 2032 204 689 4 12 49 6 14 8 11 46 5 22 5 10 34 5 21 4 14 12 24 82 60 85 221 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 212 count: 126382608 average: 3.11852 | standard deviation: 2.02576 | 0 125570339 0 0 0 0 0 0 0 794822 440 412 31 47 16 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1944 1905 1015 43 50 21 20 11 2 1 1 0 1 2 0 0 2 3 0 5 1 2 0 0 1 2 2 2037 4356 4144 206 200 153 98 109 4 5 6 5 3 0 2 3 1 8 1 2 2 6 1 9 3 1 3 5 34 36 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_RMW_Read: [binsize: 2 max: 215 count: 490938 average: 6.04036 | standard deviation: 9.43363 | 0 425802 0 0 0 0 0 0 0 10414 26 32627 15 12080 33 8513 8 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 85 391 391 44 15 1 3 9 2 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 8 49 16 125 166 0 12 1 6 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 338982 average: 5.45592 | standard deviation: 7.80247 | 0 300141 0 0 0 0 0 0 0 5462 8 22843 16 8571 49 1494 8 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 24 72 50 25 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 9 20 42 57 39 2 5 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338982 average: 3 | standard deviation: 0 | 0 0 0 338982 ] +miss_latency_NULL: [binsize: 2 max: 273 count: 151894333 average: 3.45796 | standard deviation: 5.18178 | 0 149239567 0 0 0 0 0 0 0 967464 591 1434698 471 54488 562 16355 155 88 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3746 6141 8990 10313 51758 198 522 84 112 132 6 26 8 7 13 3 10 5 5 28 6 18 2 7 7 8 479 4505 10311 18263 13957 43735 864 879 2392 323 819 20 28 57 18 19 14 12 60 8 31 14 18 43 23 32 13 29 21 85 141 121 139 253 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -52,12 +50,12 @@ miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: N miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] imcomplete_dir_Times: 0 -miss_latency_LD_NULL: [binsize: 2 max: 216 count: 14872957 average: 5.10751 | standard deviation: 8.69983 | 0 13484012 0 0 0 0 0 0 0 129492 97 1200237 320 19353 366 4823 123 70 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 919 791 3671 3477 2370 72 98 38 42 34 2 3 2 5 2 3 1 0 2 0 1 4 1 3 1 5 6 1421 2829 4534 6423 5889 348 264 260 122 133 10 9 4 7 1 7 4 5 1 6 6 4 4 8 6 4 10 4 25 22 57 48 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_ST_NULL: [binsize: 2 max: 270 count: 9468113 average: 5.20871 | standard deviation: 15.524 | 0 9118662 0 0 0 0 0 0 0 27223 26 178592 96 14286 118 1530 29 18 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 770 3337 3846 6346 49267 90 393 32 59 105 1 20 4 2 15 2 13 3 2 21 2 9 0 4 4 3 465 1055 3041 9490 7168 37336 375 495 2067 204 683 2 13 45 6 20 6 10 50 5 24 6 14 40 6 18 3 9 17 31 81 62 93 235 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_IFETCH_NULL: [binsize: 2 max: 214 count: 126376928 average: 3.11849 | standard deviation: 2.02507 | 0 125564891 0 0 0 0 0 0 0 794588 449 385 48 51 21 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1937 1912 1006 41 48 20 17 14 2 3 1 0 2 3 0 0 3 2 2 6 1 2 1 1 0 1 1 2014 4386 4163 214 182 154 101 111 7 3 5 3 1 4 2 2 3 5 1 0 1 3 3 7 3 1 2 3 33 29 13 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_RMW_Read_NULL: [binsize: 2 max: 215 count: 490895 average: 6.04017 | standard deviation: 9.43848 | 0 425774 0 0 0 0 0 0 0 10405 25 32646 14 12062 22 8519 5 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 86 87 389 392 44 14 0 4 7 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 9 45 16 122 165 3 12 1 6 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 338912 average: 5.45579 | standard deviation: 7.80876 | 0 300088 0 0 0 0 0 0 0 5460 5 22847 15 8547 47 1498 13 7 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 29 23 72 48 26 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 7 20 40 57 41 3 5 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338912 average: 3 | standard deviation: 0 | 0 0 0 338912 ] +miss_latency_LD_NULL: [binsize: 2 max: 220 count: 14873782 average: 5.10749 | standard deviation: 8.69963 | 0 13484760 0 0 0 0 0 0 0 129532 100 1200232 299 19462 338 4825 113 55 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 925 785 3670 3475 2363 76 103 37 42 35 3 4 3 3 1 2 1 0 2 1 2 3 1 3 1 4 8 1414 2823 4592 6409 5895 325 281 248 108 123 9 10 5 12 3 3 0 6 2 7 7 2 8 9 8 8 12 4 27 22 46 51 30 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 273 count: 9469041 average: 5.2084 | standard deviation: 15.5209 | 0 9119543 0 0 0 0 0 0 0 27234 17 178584 110 14328 126 1523 26 15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 767 3342 3842 6354 49276 86 397 33 58 94 2 21 3 2 12 1 7 2 2 22 3 13 1 3 4 2 469 1037 3063 9469 7160 37435 384 483 2032 204 689 4 12 49 6 14 8 11 46 5 22 5 10 34 5 21 4 14 12 24 82 60 85 221 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_NULL: [binsize: 2 max: 212 count: 126382608 average: 3.11852 | standard deviation: 2.02576 | 0 125570339 0 0 0 0 0 0 0 794822 440 412 31 47 16 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1944 1905 1015 43 50 21 20 11 2 1 1 0 1 2 0 0 2 3 0 5 1 2 0 0 1 2 2 2037 4356 4144 206 200 153 98 109 4 5 6 5 3 0 2 3 1 8 1 2 2 6 1 9 3 1 3 5 34 36 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_RMW_Read_NULL: [binsize: 2 max: 215 count: 490938 average: 6.04036 | standard deviation: 9.43363 | 0 425802 0 0 0 0 0 0 0 10414 26 32627 15 12080 33 8513 8 4 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 85 391 391 44 15 1 3 9 2 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 8 49 16 125 166 0 12 1 6 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 338982 average: 5.45592 | standard deviation: 7.80247 | 0 300141 0 0 0 0 0 0 0 5462 8 22843 16 8571 49 1494 8 5 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 27 24 72 50 25 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 9 20 42 57 39 2 5 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338982 average: 3 | standard deviation: 0 | 0 0 0 338982 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -67,14 +65,13 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 1 max: 13 count: 10870925 average: 0.594928 | standard deviation: 1.42414 | 9253812 1012 651 887 1612847 1000 118 100 122 292 7 8 8 61 ] - virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6098339 average: 1.04364 | standard deviation: 1.75794 | 4507669 499 240 245 1588105 876 117 99 116 289 7 8 8 61 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4691441 average: 0.0216927 | standard deviation: 0.292466 | 4665403 421 342 554 24629 83 1 0 6 2 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 81145 average: 0.0143817 | standard deviation: 0.224975 | 80740 92 69 88 113 41 0 1 0 1 ] +Total_delay_cycles: [binsize: 1 max: 13 count: 10872111 average: 0.594835 | standard deviation: 1.42402 | 9255080 1027 577 868 1612870 996 93 113 108 307 2 12 11 47 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6098873 average: 1.04349 | standard deviation: 1.75782 | 4508308 488 183 246 1588097 865 93 112 105 304 2 12 11 47 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4691974 average: 0.021726 | standard deviation: 0.292754 | 4665904 440 309 530 24688 96 0 1 3 3 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 5 count: 81264 average: 0.0130439 | standard deviation: 0.207207 | 80868 99 85 92 85 35 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -86,82 +83,82 @@ Total_delay_cycles: [binsize: 1 max: 13 count: 10870925 average: 0.594928 | stan Resource Usage -------------- page_size: 4096 -user_time: 791 +user_time: 450 system_time: 0 -page_reclaims: 146348 -page_faults: 22 +page_reclaims: 147544 +page_faults: 18 swaps: 0 -block_inputs: 28560 -block_outputs: 552 +block_inputs: 16000 +block_outputs: 528 Network Stats ------------- -total_msg_count_Control: 8502765 68022120 -total_msg_count_Request_Control: 241699 1933592 -total_msg_count_Response_Data: 8804706 633938832 -total_msg_count_Response_Control: 10887918 87103344 -total_msg_count_Writeback_Data: 4768101 343303272 -total_msg_count_Writeback_Control: 288537 2308296 -total_msgs: 33493726 total_bytes: 1136609456 +total_msg_count_Control: 8503962 68031696 +total_msg_count_Request_Control: 242054 1936432 +total_msg_count_Response_Data: 8805918 634026096 +total_msg_count_Response_Control: 10888710 87109680 +total_msg_count_Writeback_Data: 4768131 343305432 +total_msg_count_Writeback_Control: 288573 2308584 +total_msgs: 33497348 total_bytes: 1136717920 switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.0345328 - links_utilized_percent_switch_0_link_0: 0.0411595 bw: 16000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.0279062 bw: 16000 base_latency: 1 - - outgoing_messages_switch_0_link_0_Request_Control: 42248 337984 [ 42248 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 890958 64148976 [ 0 890958 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 508775 4070200 [ 0 508775 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 902852 7222816 [ 902852 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 39576 2849472 [ 0 39576 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 538021 4304168 [ 0 16306 521715 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 441060 31756320 [ 440947 113 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 43642 349136 [ 43642 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_0: 0.0345415 + links_utilized_percent_switch_0_link_0: 0.041172 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.0279109 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Request_Control: 42325 338600 [ 42325 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 891237 64169064 [ 0 891237 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 508805 4070440 [ 0 508805 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 903142 7225136 [ 903142 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 39642 2854224 [ 0 39642 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 538120 4304960 [ 0 16344 521776 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 441059 31756248 [ 440946 113 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 43648 349184 [ 43648 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0735425 - links_utilized_percent_switch_1_link_0: 0.0813498 bw: 16000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.0657351 bw: 16000 base_latency: 1 - - outgoing_messages_switch_1_link_0_Request_Control: 38897 311176 [ 38897 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 1741967 125421624 [ 0 1741967 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 1220914 9767312 [ 0 1220914 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 1751526 14012208 [ 1751526 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 32667 2352024 [ 0 32667 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 1253613 10028904 [ 0 16665 1236948 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 1148307 82678104 [ 1148172 135 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 52537 420296 [ 52537 0 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_1: 0.0735457 + links_utilized_percent_switch_1_link_0: 0.0813533 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.0657382 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Request_Control: 38939 311512 [ 38939 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 1742034 125426448 [ 0 1742034 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1220994 9767952 [ 0 1220994 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 1751624 14012992 [ 1751624 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 32707 2354904 [ 0 32707 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1253695 10029560 [ 0 16684 1237011 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 1148318 82678896 [ 1148183 135 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 52543 420344 [ 52543 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.112637 - links_utilized_percent_switch_2_link_0: 0.0997841 bw: 16000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.125489 bw: 16000 base_latency: 1 - - outgoing_messages_switch_2_link_0_Control: 2654378 21235024 [ 2654378 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 204194 14701968 [ 0 204194 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 1883048 15064384 [ 0 124385 1758663 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 1589367 114434424 [ 1589119 248 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 96179 769432 [ 96179 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 79409 635272 [ 79409 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 2682782 193160304 [ 0 2682782 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 1723320 13786560 [ 0 1723320 0 0 0 0 0 0 0 0 ] base_latency: 1 +links_utilized_percent_switch_2: 0.112646 + links_utilized_percent_switch_2_link_0: 0.0997896 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.125503 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 2654766 21238128 [ 2654766 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 204249 14705928 [ 0 204249 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 1883194 15065552 [ 0 124407 1758787 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 1589377 114435144 [ 1589129 248 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 96191 769528 [ 96191 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 179888 1439104 [ 179888 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 79526 636208 [ 79526 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 2683069 193180968 [ 0 2683069 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1723392 13787136 [ 0 1723392 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.0067475 - links_utilized_percent_switch_3_link_0: 0.00517033 bw: 16000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.00832467 bw: 16000 base_latency: 1 +links_utilized_percent_switch_3: 0.00674787 + links_utilized_percent_switch_3_link_0: 0.00517055 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.00832519 bw: 16000 base_latency: 1 - outgoing_messages_switch_3_link_0_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 97783 7040376 [ 0 97783 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 16569 132552 [ 0 16569 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 179877 12951144 [ 0 179877 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 114352 914816 [ 0 114352 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Control: 179888 1439104 [ 179888 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 97786 7040592 [ 0 97786 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 16577 132616 [ 0 16577 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 179888 12951936 [ 0 179888 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 114363 914904 [ 0 114363 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 @@ -172,495 +169,25 @@ links_utilized_percent_switch_4: 0 switch_5_inlinks: 5 switch_5_outlinks: 5 -links_utilized_percent_switch_5: 0.0454927 - links_utilized_percent_switch_5_link_0: 0.0411595 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.0813498 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_2: 0.0997841 bw: 16000 base_latency: 1 - links_utilized_percent_switch_5_link_3: 0.00517033 bw: 16000 base_latency: 1 +links_utilized_percent_switch_5: 0.0454971 + links_utilized_percent_switch_5_link_0: 0.041172 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.0813533 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_2: 0.0997896 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_3: 0.00517055 bw: 16000 base_latency: 1 links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1 - outgoing_messages_switch_5_link_0_Request_Control: 42248 337984 [ 42248 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 890958 64148976 [ 0 890958 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 508775 4070200 [ 0 508775 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 38897 311176 [ 38897 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 1741967 125421624 [ 0 1741967 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 1220914 9767312 [ 0 1220914 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Control: 2654378 21235024 [ 2654378 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Response_Data: 204194 14701968 [ 0 204194 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Response_Control: 1883048 15064384 [ 0 124385 1758663 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Writeback_Data: 1589367 114434424 [ 1589119 248 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_2_Writeback_Control: 96179 769432 [ 96179 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Control: 179877 1439016 [ 179877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Response_Data: 97783 7040376 [ 0 97783 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_3_Response_Control: 16569 132552 [ 0 16569 0 0 0 0 0 0 0 0 ] base_latency: 1 - - --- L1Cache --- - - Event Counts - -Load [6569518 8303439 ] 14872957 -Ifetch [70368031 56008906 ] 126376937 -Store [5484765 5152067 ] 10636832 -Inv [16419 16800 ] 33219 -L1_Replacement [875917 1724584 ] 2600501 -Fwd_GETX [12082 11527 ] 23609 -Fwd_GETS [13743 10570 ] 24313 -Fwd_GET_INSTR [4 0 ] 4 -Data [398 1087 ] 1485 -Data_Exclusive [267040 1013910 ] 1280950 -DataS_fromL1 [10570 13747 ] 24317 -Data_all_Acks [612950 713223 ] 1326173 -Ack [11894 9559 ] 21453 -Ack_all [12292 10646 ] 22938 -WB_Ack [484589 1200709 ] 1685298 -PF_Load [0 0 ] 0 -PF_Ifetch [0 0 ] 0 -PF_Store [0 0 ] 0 - - - Transitions - -NP Load [298305 1072264 ] 1370569 -NP Ifetch [352056 459391 ] 811447 -NP Store [226579 193953 ] 420532 -NP Inv [5722 3873 ] 9595 -NP L1_Replacement [0 0 ] 0 -NP PF_Load [0 0 ] 0 -NP PF_Ifetch [0 0 ] 0 -NP PF_Store [0 0 ] 0 - -I Load [8252 10124 ] 18376 -I Ifetch [134 456 ] 590 -I Store [5632 5779 ] 11411 -I Inv [0 0 ] 0 -I L1_Replacement [8759 7985 ] 16744 -I PF_Load [0 0 ] 0 -I PF_Ifetch [0 0 ] 0 -I PF_Store [0 0 ] 0 - -S Load [574695 455064 ] 1029759 -S Ifetch [70015833 55549058 ] 125564891 -S Store [11894 9559 ] 21453 -S Inv [10461 12745 ] 23206 -S L1_Replacement [382569 515890 ] 898459 -S PF_Load [0 0 ] 0 -S PF_Store [0 0 ] 0 - -E Load [1245572 2614603 ] 3860175 -E Ifetch [0 0 ] 0 -E Store [84229 82251 ] 166480 -E Inv [123 47 ] 170 -E L1_Replacement [181344 930396 ] 1111740 -E Fwd_GETX [229 170 ] 399 -E Fwd_GETS [930 990 ] 1920 -E Fwd_GET_INSTR [0 0 ] 0 -E PF_Load [0 0 ] 0 -E PF_Store [0 0 ] 0 - -M Load [4442694 4151384 ] 8594078 -M Ifetch [0 0 ] 0 -M Store [5156431 4860525 ] 10016956 -M Inv [113 135 ] 248 -M L1_Replacement [303245 270313 ] 573558 -M Fwd_GETX [11853 11357 ] 23210 -M Fwd_GETS [12813 9580 ] 22393 -M Fwd_GET_INSTR [4 0 ] 4 -M PF_Load [0 0 ] 0 -M PF_Store [0 0 ] 0 - -IS Load [0 0 ] 0 -IS Ifetch [0 0 ] 0 -IS Store [0 0 ] 0 -IS Inv [0 0 ] 0 -IS L1_Replacement [0 0 ] 0 -IS Data_Exclusive [267040 1013910 ] 1280950 -IS DataS_fromL1 [10570 13747 ] 24317 -IS Data_all_Acks [381137 514578 ] 895715 -IS PF_Load [0 0 ] 0 -IS PF_Store [0 0 ] 0 - -IM Load [0 0 ] 0 -IM Ifetch [0 0 ] 0 -IM Store [0 0 ] 0 -IM Inv [0 0 ] 0 -IM L1_Replacement [0 0 ] 0 -IM Data [398 1087 ] 1485 -IM Data_all_Acks [231813 198645 ] 430458 -IM Ack [0 0 ] 0 -IM PF_Load [0 0 ] 0 -IM PF_Store [0 0 ] 0 - -SM Load [0 0 ] 0 -SM Ifetch [0 0 ] 0 -SM Store [0 0 ] 0 -SM Inv [0 0 ] 0 -SM L1_Replacement [0 0 ] 0 -SM Ack [11894 9559 ] 21453 -SM Ack_all [12292 10646 ] 22938 -SM PF_Load [0 0 ] 0 -SM PF_Store [0 0 ] 0 - -IS_I Load [0 0 ] 0 -IS_I Ifetch [0 0 ] 0 -IS_I Store [0 0 ] 0 -IS_I Inv [0 0 ] 0 -IS_I L1_Replacement [0 0 ] 0 -IS_I Data_Exclusive [0 0 ] 0 -IS_I DataS_fromL1 [0 0 ] 0 -IS_I Data_all_Acks [0 0 ] 0 -IS_I PF_Load [0 0 ] 0 -IS_I PF_Store [0 0 ] 0 - -M_I Load [0 0 ] 0 -M_I Ifetch [8 1 ] 9 -M_I Store [0 0 ] 0 -M_I Inv [0 0 ] 0 -M_I L1_Replacement [0 0 ] 0 -M_I Fwd_GETX [0 0 ] 0 -M_I Fwd_GETS [0 0 ] 0 -M_I Fwd_GET_INSTR [0 0 ] 0 -M_I WB_Ack [484589 1200709 ] 1685298 -M_I PF_Load [0 0 ] 0 -M_I PF_Store [0 0 ] 0 - -SINK_WB_ACK Load [0 0 ] 0 -SINK_WB_ACK Ifetch [0 0 ] 0 -SINK_WB_ACK Store [0 0 ] 0 -SINK_WB_ACK Inv [0 0 ] 0 -SINK_WB_ACK L1_Replacement [0 0 ] 0 -SINK_WB_ACK WB_Ack [0 0 ] 0 -SINK_WB_ACK PF_Load [0 0 ] 0 -SINK_WB_ACK PF_Store [0 0 ] 0 - -PF_IS Load [0 0 ] 0 -PF_IS Ifetch [0 0 ] 0 -PF_IS Store [0 0 ] 0 -PF_IS Inv [0 0 ] 0 -PF_IS L1_Replacement [0 0 ] 0 -PF_IS Data_Exclusive [0 0 ] 0 -PF_IS DataS_fromL1 [0 0 ] 0 -PF_IS Data_all_Acks [0 0 ] 0 -PF_IS PF_Load [0 0 ] 0 -PF_IS PF_Store [0 0 ] 0 - -PF_IM Load [0 0 ] 0 -PF_IM Ifetch [0 0 ] 0 -PF_IM Store [0 0 ] 0 -PF_IM Inv [0 0 ] 0 -PF_IM L1_Replacement [0 0 ] 0 -PF_IM Data [0 0 ] 0 -PF_IM Data_all_Acks [0 0 ] 0 -PF_IM Ack [0 0 ] 0 -PF_IM PF_Load [0 0 ] 0 -PF_IM PF_Store [0 0 ] 0 - -PF_SM Load [0 0 ] 0 -PF_SM Ifetch [0 0 ] 0 -PF_SM Store [0 0 ] 0 -PF_SM Inv [0 0 ] 0 -PF_SM L1_Replacement [0 0 ] 0 -PF_SM Ack [0 0 ] 0 -PF_SM Ack_all [0 0 ] 0 - -PF_IS_I Load [0 0 ] 0 -PF_IS_I Store [0 0 ] 0 -PF_IS_I Inv [0 0 ] 0 -PF_IS_I L1_Replacement [0 0 ] 0 -PF_IS_I Data_Exclusive [0 0 ] 0 -PF_IS_I DataS_fromL1 [0 0 ] 0 -PF_IS_I Data_all_Acks [0 0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GET_INSTR [812037 ] 812037 -L1_GETS [1389190 ] 1389190 -L1_GETX [431946 ] 431946 -L1_UPGRADE [21453 ] 21453 -L1_PUTX [1685298 ] 1685298 -L1_PUTX_old [0 ] 0 -Fwd_L1_GETX [0 ] 0 -Fwd_L1_GETS [0 ] 0 -Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [97649 ] 97649 -L2_Replacement_clean [16703 ] 16703 -Mem_Data [179877 ] 179877 -Mem_Ack [114352 ] 114352 -WB_Data [24047 ] 24047 -WB_Data_clean [518 ] 518 -Ack [1736 ] 1736 -Ack_all [8297 ] 8297 -Unblock [24317 ] 24317 -Unblock_Cancel [0 ] 0 -Exclusive_Unblock [1734346 ] 1734346 -MEM_Inv [0 ] 0 - - - Transitions - -NP L1_GET_INSTR [16486 ] 16486 -NP L1_GETS [34061 ] 34061 -NP L1_GETX [129330 ] 129330 -NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [0 ] 0 - -SS L1_GET_INSTR [795239 ] 795239 -SS L1_GETS [83682 ] 83682 -SS L1_GETX [1684 ] 1684 -SS L1_UPGRADE [21453 ] 21453 -SS L1_PUTX [0 ] 0 -SS L1_PUTX_old [0 ] 0 -SS L2_Replacement [262 ] 262 -SS L2_Replacement_clean [7865 ] 7865 -SS MEM_Inv [0 ] 0 - -M L1_GET_INSTR [308 ] 308 -M L1_GETS [1246889 ] 1246889 -M L1_GETX [277320 ] 277320 -M L1_PUTX [0 ] 0 -M L1_PUTX_old [0 ] 0 -M L2_Replacement [97222 ] 97222 -M L2_Replacement_clean [8585 ] 8585 -M MEM_Inv [0 ] 0 - -MT L1_GET_INSTR [4 ] 4 -MT L1_GETS [24313 ] 24313 -MT L1_GETX [23609 ] 23609 -MT L1_PUTX [1685298 ] 1685298 -MT L1_PUTX_old [0 ] 0 -MT L2_Replacement [165 ] 165 -MT L2_Replacement_clean [253 ] 253 -MT MEM_Inv [0 ] 0 - -M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [0 ] 0 -M_I L1_GETX [0 ] 0 -M_I L1_UPGRADE [0 ] 0 -M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [0 ] 0 -M_I Mem_Ack [114352 ] 114352 -M_I MEM_Inv [0 ] 0 - -MT_I L1_GET_INSTR [0 ] 0 -MT_I L1_GETS [0 ] 0 -MT_I L1_GETX [0 ] 0 -MT_I L1_UPGRADE [0 ] 0 -MT_I L1_PUTX [0 ] 0 -MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [114 ] 114 -MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [51 ] 51 -MT_I MEM_Inv [0 ] 0 - -MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [0 ] 0 -MCT_I L1_GETX [0 ] 0 -MCT_I L1_UPGRADE [0 ] 0 -MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [0 ] 0 -MCT_I WB_Data [134 ] 134 -MCT_I WB_Data_clean [0 ] 0 -MCT_I Ack_all [119 ] 119 - -I_I L1_GET_INSTR [0 ] 0 -I_I L1_GETS [0 ] 0 -I_I L1_GETX [0 ] 0 -I_I L1_UPGRADE [0 ] 0 -I_I L1_PUTX [0 ] 0 -I_I L1_PUTX_old [0 ] 0 -I_I Ack [1475 ] 1475 -I_I Ack_all [7865 ] 7865 - -S_I L1_GET_INSTR [0 ] 0 -S_I L1_GETS [0 ] 0 -S_I L1_GETX [0 ] 0 -S_I L1_UPGRADE [0 ] 0 -S_I L1_PUTX [0 ] 0 -S_I L1_PUTX_old [0 ] 0 -S_I Ack [261 ] 261 -S_I Ack_all [262 ] 262 -S_I MEM_Inv [0 ] 0 - -ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [0 ] 0 -ISS L1_GETX [0 ] 0 -ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [0 ] 0 -ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [0 ] 0 -ISS Mem_Data [34061 ] 34061 -ISS MEM_Inv [0 ] 0 - -IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [0 ] 0 -IS L1_GETX [0 ] 0 -IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [0 ] 0 -IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [0 ] 0 -IS Mem_Data [16486 ] 16486 -IS MEM_Inv [0 ] 0 - -IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [0 ] 0 -IM L1_GETX [0 ] 0 -IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [0 ] 0 -IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [0 ] 0 -IM Mem_Data [129330 ] 129330 -IM MEM_Inv [0 ] 0 - -SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [183 ] 183 -SS_MB L1_GETX [1 ] 1 -SS_MB L1_UPGRADE [0 ] 0 -SS_MB L1_PUTX [0 ] 0 -SS_MB L1_PUTX_old [0 ] 0 -SS_MB L2_Replacement [0 ] 0 -SS_MB L2_Replacement_clean [0 ] 0 -SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [23137 ] 23137 -SS_MB MEM_Inv [0 ] 0 - -MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [62 ] 62 -MT_MB L1_GETX [2 ] 2 -MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [0 ] 0 -MT_MB L1_PUTX_old [0 ] 0 -MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [0 ] 0 -MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [1711209 ] 1711209 -MT_MB MEM_Inv [0 ] 0 - -MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [0 ] 0 -MT_IIB L1_GETX [0 ] 0 -MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [0 ] 0 -MT_IIB L1_PUTX_old [0 ] 0 -MT_IIB L2_Replacement [0 ] 0 -MT_IIB L2_Replacement_clean [0 ] 0 -MT_IIB WB_Data [23791 ] 23791 -MT_IIB WB_Data_clean [518 ] 518 -MT_IIB Unblock [8 ] 8 -MT_IIB MEM_Inv [0 ] 0 - -MT_IB L1_GET_INSTR [0 ] 0 -MT_IB L1_GETS [0 ] 0 -MT_IB L1_GETX [0 ] 0 -MT_IB L1_UPGRADE [0 ] 0 -MT_IB L1_PUTX [0 ] 0 -MT_IB L1_PUTX_old [0 ] 0 -MT_IB L2_Replacement [0 ] 0 -MT_IB L2_Replacement_clean [0 ] 0 -MT_IB WB_Data [8 ] 8 -MT_IB WB_Data_clean [0 ] 0 -MT_IB Unblock_Cancel [0 ] 0 -MT_IB MEM_Inv [0 ] 0 - -MT_SB L1_GET_INSTR [0 ] 0 -MT_SB L1_GETS [0 ] 0 -MT_SB L1_GETX [0 ] 0 -MT_SB L1_UPGRADE [0 ] 0 -MT_SB L1_PUTX [0 ] 0 -MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [0 ] 0 -MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [24309 ] 24309 -MT_SB MEM_Inv [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 277660 - memory_reads: 179877 - memory_writes: 97783 - memory_refreshes: 595612 - memory_total_request_delays: 1053031 - memory_delays_per_request: 3.79252 - memory_delays_in_input_queue: 41105 - memory_delays_behind_head_of_bank_queue: 8032 - memory_delays_stalled_at_head_of_bank_queue: 1003894 - memory_stalls_for_bank_busy: 993997 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 2275 - memory_stalls_for_bus: 7591 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 24 - memory_stalls_for_read_read_turnaround: 7 - accesses_per_bank: 9197 9271 8435 8566 9408 8743 9113 8368 8530 8379 8370 8376 8453 8237 8220 7443 8424 8515 8423 8429 8600 8511 8363 8339 8693 8492 8814 9468 9371 9231 10342 8536 - - --- Directory --- - - Event Counts - -Fetch [179877 ] 179877 -Data [97783 ] 97783 -Memory_Data [179877 ] 179877 -Memory_Ack [97783 ] 97783 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -CleanReplacement [16569 ] 16569 - - - Transitions - -I Fetch [179877 ] 179877 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -ID Fetch [0 ] 0 -ID Data [0 ] 0 -ID Memory_Data [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 - -ID_W Fetch [0 ] 0 -ID_W Data [0 ] 0 -ID_W Memory_Ack [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 - -M Data [97783 ] 97783 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 -M CleanReplacement [16569 ] 16569 - -IM Fetch [0 ] 0 -IM Data [0 ] 0 -IM Memory_Data [179877 ] 179877 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 - -MI Fetch [0 ] 0 -MI Data [0 ] 0 -MI Memory_Ack [97783 ] 97783 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -M_DRD Data [0 ] 0 -M_DRD DMA_READ [0 ] 0 -M_DRD DMA_WRITE [0 ] 0 - -M_DRDI Fetch [0 ] 0 -M_DRDI Data [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 -M_DRDI DMA_READ [0 ] 0 -M_DRDI DMA_WRITE [0 ] 0 - -M_DWR Data [0 ] 0 -M_DWR DMA_READ [0 ] 0 -M_DWR DMA_WRITE [0 ] 0 - -M_DWRI Fetch [0 ] 0 -M_DWRI Data [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 -M_DWRI DMA_READ [0 ] 0 -M_DWRI DMA_WRITE [0 ] 0 - - --- DMA --- - - Event Counts - -ReadRequest [0 ] 0 -WriteRequest [0 ] 0 -Data [0 ] 0 -Ack [0 ] 0 - - - Transitions - -READY ReadRequest [0 ] 0 -READY WriteRequest [0 ] 0 - -BUSY_RD Data [0 ] 0 - -BUSY_WR Ack [0 ] 0 + outgoing_messages_switch_5_link_0_Request_Control: 42325 338600 [ 42325 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 891237 64169064 [ 0 891237 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 508805 4070440 [ 0 508805 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 38939 311512 [ 38939 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 1742034 125426448 [ 0 1742034 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 1220994 9767952 [ 0 1220994 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Control: 2654766 21238128 [ 2654766 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Data: 204249 14705928 [ 0 204249 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Control: 1883194 15065552 [ 0 124407 1758787 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Data: 1589377 114435144 [ 1589129 248 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Control: 96191 769528 [ 96191 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Control: 179888 1439104 [ 179888 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Data: 97786 7040592 [ 0 97786 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Control: 16577 132616 [ 0 16577 0 0 0 0 0 0 0 0 ] base_latency: 1 diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt index 11c0ff3fa..1e123cf28 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.205149 # Nu sim_ticks 5205149326500 # Number of ticks simulated final_tick 5205149326500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 156279 # Simulator instruction rate (inst/s) -host_op_rate 299599 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7625516175 # Simulator tick rate (ticks/s) -host_mem_usage 825184 # Number of bytes of host memory used -host_seconds 682.60 # Real time elapsed on the host +host_inst_rate 236082 # Simulator instruction rate (inst/s) +host_op_rate 452590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11519487202 # Simulator tick rate (ticks/s) +host_mem_usage 865820 # Number of bytes of host memory used +host_seconds 451.86 # Real time elapsed on the host sim_insts 106675228 # Number of instructions simulated sim_ops 204505420 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 35240 # Number of bytes read from this memory @@ -499,6 +499,23 @@ system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 system.ruby.l2_cntrl0.L2cache.demand_hits 2426890 # Number of cache demand hits system.ruby.l2_cntrl0.L2cache.demand_misses 227876 # Number of cache demand misses system.ruby.l2_cntrl0.L2cache.demand_accesses 2654766 # Number of cache demand accesses +system.ruby.dir_cntrl0.memBuffer.memReq 277674 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 179888 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 97786 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 595732 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 1003550 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 41112 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 8109 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 1052771 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 3.791392 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 993723 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 7525 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 17 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 4 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 2281 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 9206 3.32% 3.32% | 9271 3.34% 6.65% | 8439 3.04% 9.69% | 8570 3.09% 12.78% | 9408 3.39% 16.17% | 8743 3.15% 19.32% | 9113 3.28% 22.60% | 8368 3.01% 25.61% | 8530 3.07% 28.68% | 8379 3.02% 31.70% | 8370 3.01% 34.72% | 8376 3.02% 37.73% | 8453 3.04% 40.78% | 8237 2.97% 43.74% | 8220 2.96% 46.70% | 7443 2.68% 49.38% | 8424 3.03% 52.42% | 8514 3.07% 55.48% | 8423 3.03% 58.52% | 8429 3.04% 61.55% | 8600 3.10% 64.65% | 8511 3.07% 67.72% | 8363 3.01% 70.73% | 8339 3.00% 73.73% | 8693 3.13% 76.86% | 8492 3.06% 79.92% | 8814 3.17% 83.09% | 9464 3.41% 86.50% | 9373 3.38% 89.88% | 9231 3.32% 93.20% | 10342 3.72% 96.93% | 8536 3.07% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 277674 # Number of accesses per bank + system.cpu0.numCycles 10410298653 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -547,5 +564,223 @@ system.cpu1.not_idle_fraction 0.031349 # Pe system.cpu1.idle_fraction 0.968651 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.ruby.l1_cntrl0.Load | 6571015 44.18% 44.18% | 8302767 55.82% 100.00% +system.ruby.l1_cntrl0.Load::total 14873782 + +system.ruby.l1_cntrl0.Ifetch | 70375931 55.68% 55.68% | 56006686 44.32% 100.00% +system.ruby.l1_cntrl0.Ifetch::total 126382617 + +system.ruby.l1_cntrl0.Store | 5485961 51.57% 51.57% | 5151982 48.43% 100.00% +system.ruby.l1_cntrl0.Store::total 10637943 + +system.ruby.l1_cntrl0.Inv | 16457 49.46% 49.46% | 16819 50.54% 100.00% +system.ruby.l1_cntrl0.Inv::total 33276 + +system.ruby.l1_cntrl0.L1_Replacement | 876181 33.69% 33.69% | 1724616 66.31% 100.00% +system.ruby.l1_cntrl0.L1_Replacement::total 2600797 + +system.ruby.l1_cntrl0.Fwd_GETX | 12094 51.19% 51.19% | 11533 48.81% 100.00% +system.ruby.l1_cntrl0.Fwd_GETX::total 23627 + +system.ruby.l1_cntrl0.Fwd_GETS | 13770 56.53% 56.53% | 10587 43.47% 100.00% +system.ruby.l1_cntrl0.Fwd_GETS::total 24357 + +system.ruby.l1_cntrl0.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.l1_cntrl0.Fwd_GET_INSTR::total 4 + +system.ruby.l1_cntrl0.Data | 401 26.93% 26.93% | 1088 73.07% 100.00% +system.ruby.l1_cntrl0.Data::total 1489 + +system.ruby.l1_cntrl0.Data_Exclusive | 267049 20.85% 20.85% | 1013902 79.15% 100.00% +system.ruby.l1_cntrl0.Data_Exclusive::total 1280951 + +system.ruby.l1_cntrl0.DataS_fromL1 | 10587 43.46% 43.46% | 13774 56.54% 100.00% +system.ruby.l1_cntrl0.DataS_fromL1::total 24361 + +system.ruby.l1_cntrl0.Data_all_Acks | 613200 46.23% 46.23% | 713270 53.77% 100.00% +system.ruby.l1_cntrl0.Data_all_Acks::total 1326470 + +system.ruby.l1_cntrl0.Ack | 11905 55.38% 55.38% | 9590 44.62% 100.00% +system.ruby.l1_cntrl0.Ack::total 21495 + +system.ruby.l1_cntrl0.Ack_all | 12306 53.54% 53.54% | 10678 46.46% 100.00% +system.ruby.l1_cntrl0.Ack_all::total 22984 + +system.ruby.l1_cntrl0.WB_Ack | 484594 28.75% 28.75% | 1200726 71.25% 100.00% +system.ruby.l1_cntrl0.WB_Ack::total 1685320 + +system.ruby.l1_cntrl0.NP.Load | 298337 21.77% 21.77% | 1072276 78.23% 100.00% +system.ruby.l1_cntrl0.NP.Load::total 1370613 + +system.ruby.l1_cntrl0.NP.Ifetch | 352269 43.40% 43.40% | 459412 56.60% 100.00% +system.ruby.l1_cntrl0.NP.Ifetch::total 811681 + +system.ruby.l1_cntrl0.NP.Store | 226598 53.88% 53.88% | 193952 46.12% 100.00% +system.ruby.l1_cntrl0.NP.Store::total 420550 + +system.ruby.l1_cntrl0.NP.Inv | 5731 59.66% 59.66% | 3875 40.34% 100.00% +system.ruby.l1_cntrl0.NP.Inv::total 9606 + +system.ruby.l1_cntrl0.I.Load | 8263 44.89% 44.89% | 10146 55.11% 100.00% +system.ruby.l1_cntrl0.I.Load::total 18409 + +system.ruby.l1_cntrl0.I.Ifetch | 133 22.62% 22.62% | 455 77.38% 100.00% +system.ruby.l1_cntrl0.I.Ifetch::total 588 + +system.ruby.l1_cntrl0.I.Store | 5637 49.32% 49.32% | 5793 50.68% 100.00% +system.ruby.l1_cntrl0.I.Store::total 11430 + +system.ruby.l1_cntrl0.I.L1_Replacement | 8785 52.43% 52.43% | 7970 47.57% 100.00% +system.ruby.l1_cntrl0.I.L1_Replacement::total 16755 + +system.ruby.l1_cntrl0.S.Load | 574881 55.81% 55.81% | 455195 44.19% 100.00% +system.ruby.l1_cntrl0.S.Load::total 1030076 + +system.ruby.l1_cntrl0.S.Ifetch | 70023521 55.76% 55.76% | 55546818 44.24% 100.00% +system.ruby.l1_cntrl0.S.Ifetch::total 125570339 + +system.ruby.l1_cntrl0.S.Store | 11905 55.38% 55.38% | 9590 44.62% 100.00% +system.ruby.l1_cntrl0.S.Store::total 21495 + +system.ruby.l1_cntrl0.S.Inv | 10490 45.11% 45.11% | 12762 54.89% 100.00% +system.ruby.l1_cntrl0.S.Inv::total 23252 + +system.ruby.l1_cntrl0.S.L1_Replacement | 382802 42.59% 42.59% | 515920 57.41% 100.00% +system.ruby.l1_cntrl0.S.L1_Replacement::total 898722 + +system.ruby.l1_cntrl0.E.Load | 1245602 32.27% 32.27% | 2614611 67.73% 100.00% +system.ruby.l1_cntrl0.E.Load::total 3860213 + +system.ruby.l1_cntrl0.E.Store | 84222 50.59% 50.59% | 82245 49.41% 100.00% +system.ruby.l1_cntrl0.E.Store::total 166467 + +system.ruby.l1_cntrl0.E.Inv | 123 72.35% 72.35% | 47 27.65% 100.00% +system.ruby.l1_cntrl0.E.Inv::total 170 + +system.ruby.l1_cntrl0.E.L1_Replacement | 181362 16.31% 16.31% | 930398 83.69% 100.00% +system.ruby.l1_cntrl0.E.L1_Replacement::total 1111760 + +system.ruby.l1_cntrl0.E.Fwd_GETX | 229 57.39% 57.39% | 170 42.61% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GETX::total 399 + +system.ruby.l1_cntrl0.E.Fwd_GETS | 928 48.38% 48.38% | 990 51.62% 100.00% +system.ruby.l1_cntrl0.E.Fwd_GETS::total 1918 + +system.ruby.l1_cntrl0.M.Load | 4443932 51.71% 51.71% | 4150539 48.29% 100.00% +system.ruby.l1_cntrl0.M.Load::total 8594471 + +system.ruby.l1_cntrl0.M.Store | 5157599 51.48% 51.48% | 4860402 48.52% 100.00% +system.ruby.l1_cntrl0.M.Store::total 10018001 + +system.ruby.l1_cntrl0.M.Inv | 113 45.56% 45.56% | 135 54.44% 100.00% +system.ruby.l1_cntrl0.M.Inv::total 248 + +system.ruby.l1_cntrl0.M.L1_Replacement | 303232 52.87% 52.87% | 270328 47.13% 100.00% +system.ruby.l1_cntrl0.M.L1_Replacement::total 573560 + +system.ruby.l1_cntrl0.M.Fwd_GETX | 11865 51.08% 51.08% | 11363 48.92% 100.00% +system.ruby.l1_cntrl0.M.Fwd_GETX::total 23228 + +system.ruby.l1_cntrl0.M.Fwd_GETS | 12842 57.23% 57.23% | 9597 42.77% 100.00% +system.ruby.l1_cntrl0.M.Fwd_GETS::total 22439 + +system.ruby.l1_cntrl0.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.l1_cntrl0.M.Fwd_GET_INSTR::total 4 + +system.ruby.l1_cntrl0.IS.Data_Exclusive | 267049 20.85% 20.85% | 1013902 79.15% 100.00% +system.ruby.l1_cntrl0.IS.Data_Exclusive::total 1280951 + +system.ruby.l1_cntrl0.IS.DataS_fromL1 | 10587 43.46% 43.46% | 13774 56.54% 100.00% +system.ruby.l1_cntrl0.IS.DataS_fromL1::total 24361 + +system.ruby.l1_cntrl0.IS.Data_all_Acks | 381366 42.56% 42.56% | 514613 57.44% 100.00% +system.ruby.l1_cntrl0.IS.Data_all_Acks::total 895979 + +system.ruby.l1_cntrl0.IM.Data | 401 26.93% 26.93% | 1088 73.07% 100.00% +system.ruby.l1_cntrl0.IM.Data::total 1489 + +system.ruby.l1_cntrl0.IM.Data_all_Acks | 231834 53.85% 53.85% | 198657 46.15% 100.00% +system.ruby.l1_cntrl0.IM.Data_all_Acks::total 430491 + +system.ruby.l1_cntrl0.SM.Ack | 11905 55.38% 55.38% | 9590 44.62% 100.00% +system.ruby.l1_cntrl0.SM.Ack::total 21495 + +system.ruby.l1_cntrl0.SM.Ack_all | 12306 53.54% 53.54% | 10678 46.46% 100.00% +system.ruby.l1_cntrl0.SM.Ack_all::total 22984 + +system.ruby.l1_cntrl0.M_I.Ifetch | 8 88.89% 88.89% | 1 11.11% 100.00% +system.ruby.l1_cntrl0.M_I.Ifetch::total 9 + +system.ruby.l1_cntrl0.M_I.WB_Ack | 484594 28.75% 28.75% | 1200726 71.25% 100.00% +system.ruby.l1_cntrl0.M_I.WB_Ack::total 1685320 + +system.ruby.l2_cntrl0.L1_GET_INSTR 812269 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETS 1389202 0.00% 0.00% +system.ruby.l2_cntrl0.L1_GETX 431983 0.00% 0.00% +system.ruby.l2_cntrl0.L1_UPGRADE 21495 0.00% 0.00% +system.ruby.l2_cntrl0.L1_PUTX 1685320 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement 97653 0.00% 0.00% +system.ruby.l2_cntrl0.L2_Replacement_clean 16710 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Data 179888 0.00% 0.00% +system.ruby.l2_cntrl0.Mem_Ack 114363 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data 24092 0.00% 0.00% +system.ruby.l2_cntrl0.WB_Data_clean 517 0.00% 0.00% +system.ruby.l2_cntrl0.Ack 1738 0.00% 0.00% +system.ruby.l2_cntrl0.Ack_all 8306 0.00% 0.00% +system.ruby.l2_cntrl0.Unblock 24361 0.00% 0.00% +system.ruby.l2_cntrl0.Exclusive_Unblock 1734426 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GET_INSTR 16492 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETS 34063 0.00% 0.00% +system.ruby.l2_cntrl0.NP.L1_GETX 129333 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GET_INSTR 795465 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETS 83714 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_GETX 1688 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L1_UPGRADE 21495 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement 263 0.00% 0.00% +system.ruby.l2_cntrl0.SS.L2_Replacement_clean 7873 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GET_INSTR 308 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETS 1246888 0.00% 0.00% +system.ruby.l2_cntrl0.M.L1_GETX 277332 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement 97224 0.00% 0.00% +system.ruby.l2_cntrl0.M.L2_Replacement_clean 8585 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GET_INSTR 4 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GETS 24357 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_GETX 23627 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L1_PUTX 1685320 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement 166 0.00% 0.00% +system.ruby.l2_cntrl0.MT.L2_Replacement_clean 252 0.00% 0.00% +system.ruby.l2_cntrl0.M_I.Mem_Ack 114363 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.WB_Data 115 0.00% 0.00% +system.ruby.l2_cntrl0.MT_I.Ack_all 51 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.WB_Data 133 0.00% 0.00% +system.ruby.l2_cntrl0.MCT_I.Ack_all 119 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack 1476 0.00% 0.00% +system.ruby.l2_cntrl0.I_I.Ack_all 7873 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.Ack 262 0.00% 0.00% +system.ruby.l2_cntrl0.S_I.Ack_all 263 0.00% 0.00% +system.ruby.l2_cntrl0.ISS.Mem_Data 34063 0.00% 0.00% +system.ruby.l2_cntrl0.IS.Mem_Data 16492 0.00% 0.00% +system.ruby.l2_cntrl0.IM.Mem_Data 129333 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.L1_GETS 124 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.L1_GETX 1 0.00% 0.00% +system.ruby.l2_cntrl0.SS_MB.Exclusive_Unblock 23183 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L1_GETS 56 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.L1_GETX 2 0.00% 0.00% +system.ruby.l2_cntrl0.MT_MB.Exclusive_Unblock 1711243 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.WB_Data 23838 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean 517 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IIB.Unblock 6 0.00% 0.00% +system.ruby.l2_cntrl0.MT_IB.WB_Data 6 0.00% 0.00% +system.ruby.l2_cntrl0.MT_SB.Unblock 24355 0.00% 0.00% +system.ruby.dir_cntrl0.Fetch 179888 0.00% 0.00% +system.ruby.dir_cntrl0.Data 97786 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Data 179888 0.00% 0.00% +system.ruby.dir_cntrl0.Memory_Ack 97786 0.00% 0.00% +system.ruby.dir_cntrl0.CleanReplacement 16577 0.00% 0.00% +system.ruby.dir_cntrl0.I.Fetch 179888 0.00% 0.00% +system.ruby.dir_cntrl0.M.Data 97786 0.00% 0.00% +system.ruby.dir_cntrl0.M.CleanReplacement 16577 0.00% 0.00% +system.ruby.dir_cntrl0.IM.Memory_Data 179888 0.00% 0.00% +system.ruby.dir_cntrl0.MI.Memory_Ack 97786 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt index e69de29bb..f8bafa63e 100644 --- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt +++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt @@ -0,0 +1,138 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.233778 # Number of seconds simulated +sim_ticks 4467555024 # Number of ticks simulated +final_tick 4467555024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 2000000000 # Frequency of simulated ticks +host_inst_rate 3018077 # Simulator instruction rate (inst/s) +host_op_rate 3019263 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6051033 # Simulator tick rate (ticks/s) +host_mem_usage 556628 # Number of bytes of host memory used +host_seconds 738.31 # Real time elapsed on the host +sim_insts 2228284650 # Number of instructions simulated +sim_ops 2229160714 # Number of ops (including micro ops) simulated +system.hypervisor_desc.bytes_read::cpu.data 16792 # Number of bytes read from this memory +system.hypervisor_desc.bytes_read::total 16792 # Number of bytes read from this memory +system.hypervisor_desc.num_reads::cpu.data 9024 # Number of read requests responded to by this memory +system.hypervisor_desc.num_reads::total 9024 # Number of read requests responded to by this memory +system.hypervisor_desc.bw_read::cpu.data 7517 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_read::total 7517 # Total read bandwidth from this memory (bytes/s) +system.hypervisor_desc.bw_total::cpu.data 7517 # Total bandwidth to/from this memory (bytes/s) +system.hypervisor_desc.bw_total::total 7517 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bytes_read::cpu.data 4846 # Number of bytes read from this memory +system.partition_desc.bytes_read::total 4846 # Number of bytes read from this memory +system.partition_desc.num_reads::cpu.data 608 # Number of read requests responded to by this memory +system.partition_desc.num_reads::total 608 # Number of read requests responded to by this memory +system.partition_desc.bw_read::cpu.data 2169 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_read::total 2169 # Total read bandwidth from this memory (bytes/s) +system.partition_desc.bw_total::cpu.data 2169 # Total bandwidth to/from this memory (bytes/s) +system.partition_desc.bw_total::total 2169 # Total bandwidth to/from this memory (bytes/s) +system.rom.bytes_read::cpu.inst 432296 # Number of bytes read from this memory +system.rom.bytes_read::cpu.data 696392 # Number of bytes read from this memory +system.rom.bytes_read::total 1128688 # Number of bytes read from this memory +system.rom.bytes_inst_read::cpu.inst 432296 # Number of instructions bytes read from this memory +system.rom.bytes_inst_read::total 432296 # Number of instructions bytes read from this memory +system.rom.num_reads::cpu.inst 108074 # Number of read requests responded to by this memory +system.rom.num_reads::cpu.data 87049 # Number of read requests responded to by this memory +system.rom.num_reads::total 195123 # Number of read requests responded to by this memory +system.rom.bw_read::cpu.inst 193527 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::cpu.data 311755 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_read::total 505282 # Total read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::cpu.inst 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_inst_read::total 193527 # Instruction read bandwidth from this memory (bytes/s) +system.rom.bw_total::cpu.inst 193527 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::cpu.data 311755 # Total bandwidth to/from this memory (bytes/s) +system.rom.bw_total::total 505282 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bytes_read::cpu.data 284 # Number of bytes read from this memory +system.nvram.bytes_read::total 284 # Number of bytes read from this memory +system.nvram.bytes_written::cpu.data 92 # Number of bytes written to this memory +system.nvram.bytes_written::total 92 # Number of bytes written to this memory +system.nvram.num_reads::cpu.data 284 # Number of read requests responded to by this memory +system.nvram.num_reads::total 284 # Number of read requests responded to by this memory +system.nvram.num_writes::cpu.data 92 # Number of write requests responded to by this memory +system.nvram.num_writes::total 92 # Number of write requests responded to by this memory +system.nvram.bw_read::cpu.data 127 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_read::total 127 # Total read bandwidth from this memory (bytes/s) +system.nvram.bw_write::cpu.data 41 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_write::total 41 # Write bandwidth from this memory (bytes/s) +system.nvram.bw_total::cpu.data 168 # Total bandwidth to/from this memory (bytes/s) +system.nvram.bw_total::total 168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 612291324 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 97534024 # Number of bytes read from this memory +system.physmem.bytes_read::total 709825348 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 612291324 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 612291324 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 15400223 # Number of bytes written to this memory +system.physmem.bytes_written::total 15400223 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 153072831 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 12152054 # Number of read requests responded to by this memory +system.physmem.num_reads::total 165224885 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 1927067 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1927067 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 14 # Number of other requests responded to by this memory +system.physmem.num_other::total 14 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 274105779 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 43663267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 317769046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 274105779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 274105779 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6894251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6894251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 274105779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 50557518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 324663297 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bytes_read::cpu.inst 8318106840 # Number of bytes read from this memory +system.physmem2.bytes_read::cpu.data 1495885127 # Number of bytes read from this memory +system.physmem2.bytes_read::total 9813991967 # Number of bytes read from this memory +system.physmem2.bytes_inst_read::cpu.inst 8318106840 # Number of instructions bytes read from this memory +system.physmem2.bytes_inst_read::total 8318106840 # Number of instructions bytes read from this memory +system.physmem2.bytes_written::cpu.data 897268422 # Number of bytes written to this memory +system.physmem2.bytes_written::total 897268422 # Number of bytes written to this memory +system.physmem2.num_reads::cpu.inst 2079526710 # Number of read requests responded to by this memory +system.physmem2.num_reads::cpu.data 323962420 # Number of read requests responded to by this memory +system.physmem2.num_reads::total 2403489130 # Number of read requests responded to by this memory +system.physmem2.num_writes::cpu.data 187387796 # Number of write requests responded to by this memory +system.physmem2.num_writes::total 187387796 # Number of write requests responded to by this memory +system.physmem2.num_other::cpu.data 5403067 # Number of other requests responded to by this memory +system.physmem2.num_other::total 5403067 # Number of other requests responded to by this memory +system.physmem2.bw_read::cpu.inst 3723784842 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::cpu.data 669666123 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_read::total 4393450966 # Total read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::cpu.inst 3723784842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_inst_read::total 3723784842 # Instruction read bandwidth from this memory (bytes/s) +system.physmem2.bw_write::cpu.data 401682091 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_write::total 401682091 # Write bandwidth from this memory (bytes/s) +system.physmem2.bw_total::cpu.inst 3723784842 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::cpu.data 1071348214 # Total bandwidth to/from this memory (bytes/s) +system.physmem2.bw_total::total 4795133057 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 5163367605 # Throughput (bytes/s) +system.membus.data_through_bus 11533814443 # Total data (bytes) +system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) +system.iobus.throughput 15555081 # Throughput (bytes/s) +system.iobus.data_through_bus 34746591 # Total data (bytes) +system.cpu.numCycles 2233777513 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 2228284650 # Number of instructions committed +system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses +system.cpu.num_func_calls 44037246 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 316367761 # number of instructions that are conditional controls +system.cpu.num_int_insts 1839325658 # number of integer instructions +system.cpu.num_fp_insts 14608322 # number of float instructions +system.cpu.num_int_register_reads 4305540407 # number of times the integer registers were read +system.cpu.num_int_register_writes 2100562807 # number of times the integer registers were written +system.cpu.num_fp_register_reads 35401841 # number of times the floating registers were read +system.cpu.num_fp_register_writes 22917558 # number of times the floating registers were written +system.cpu.num_mem_refs 547951940 # number of memory refs +system.cpu.num_load_insts 349807670 # Number of load instructions +system.cpu.num_store_insts 198144270 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 2233777513 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.kern.inst.arm 0 # number of arm instructions executed +system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index c00464415..c258cba07 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,100 +1,100 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202265 # Number of seconds simulated -sim_ticks 202264702500 # Number of ticks simulated -final_tick 202264702500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202255 # Number of seconds simulated +sim_ticks 202254809500 # Number of ticks simulated +final_tick 202254809500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152154 # Simulator instruction rate (inst/s) -host_op_rate 171544 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 60912686 # Simulator tick rate (ticks/s) -host_mem_usage 250588 # Number of bytes of host memory used -host_seconds 3320.57 # Real time elapsed on the host +host_inst_rate 148306 # Simulator instruction rate (inst/s) +host_op_rate 167206 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59369383 # Simulator tick rate (ticks/s) +host_mem_usage 288744 # Number of bytes of host memory used +host_seconds 3406.72 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 569624283 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 216000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9260928 # Number of bytes read from this memory -system.physmem.bytes_read::total 9476928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 216000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 216000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6246016 # Number of bytes written to this memory -system.physmem.bytes_written::total 6246016 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3375 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144702 # Number of read requests responded to by this memory -system.physmem.num_reads::total 148077 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97594 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97594 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1067908 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 45786180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 46854087 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1067908 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1067908 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 30880405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 30880405 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 30880405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1067908 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 45786180 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 77734493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 148078 # Total number of read requests seen -system.physmem.writeReqs 97594 # Total number of write requests seen -system.physmem.cpureqs 245687 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 9476928 # Total number of bytes read from memory -system.physmem.bytesWritten 6246016 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 9476928 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6246016 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 65 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 9 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 9583 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 9207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 9281 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 8971 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 9774 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 9643 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 9100 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 8322 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 8802 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 8899 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 8932 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 9735 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 9616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 9782 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 8932 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 9434 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 6260 # Track writes on a per bank basis +system.physmem.bytes_read::cpu.inst 216064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9266496 # Number of bytes read from this memory +system.physmem.bytes_read::total 9482560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 216064 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 216064 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6247616 # Number of bytes written to this memory +system.physmem.bytes_written::total 6247616 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3376 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 144789 # Number of read requests responded to by this memory +system.physmem.num_reads::total 148165 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97619 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97619 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1068276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 45815949 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 46884225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1068276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1068276 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 30889827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 30889827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 30889827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1068276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 45815949 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 77774052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 148166 # Total number of read requests seen +system.physmem.writeReqs 97619 # Total number of write requests seen +system.physmem.cpureqs 245800 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 9482560 # Total number of bytes read from memory +system.physmem.bytesWritten 6247616 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 9482560 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6247616 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 82 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 10 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 9642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 9223 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 9266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 8974 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 9810 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 9620 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 9110 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 8299 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 8798 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 8898 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 8934 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 9719 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 9635 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 9761 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 8951 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 9444 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 6285 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 6145 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 6098 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 5882 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 6246 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 6280 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 6093 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 5883 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 6272 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 6268 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 6041 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 5558 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 5810 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 5899 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 5989 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 6521 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 6350 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 6340 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 6045 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 6130 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 5542 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 5814 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 5893 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 5986 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6510 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 6368 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6328 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 6050 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 6141 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 6 # Number of times wr buffer was full causing retry -system.physmem.totGap 202264683000 # Total gap between requests +system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry +system.physmem.totGap 202254789500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 148078 # Categorize read packet sizes +system.physmem.readPktSize::6 148166 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 0 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 97594 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 138541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 8888 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97619 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 138581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 8939 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 502 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 55 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -124,198 +124,199 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4226 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 4234 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 4236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4238 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 55927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 281.047508 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 134.123063 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 688.589570 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-65 27857 49.81% 49.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-129 10311 18.44% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-193 4742 8.48% 76.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-257 2859 5.11% 81.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-321 1799 3.22% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-385 1160 2.07% 87.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-449 842 1.51% 88.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-513 665 1.19% 89.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-577 468 0.84% 90.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-641 376 0.67% 91.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-705 271 0.48% 91.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-769 239 0.43% 92.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-833 201 0.36% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-897 180 0.32% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-961 171 0.31% 93.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1025 177 0.32% 93.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1089 169 0.30% 93.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1153 170 0.30% 94.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1217 147 0.26% 94.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1281 156 0.28% 94.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1345 167 0.30% 94.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1409 250 0.45% 95.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1473 974 1.74% 97.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1537 239 0.43% 97.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1601 147 0.26% 97.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1665 173 0.31% 98.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1729 101 0.18% 98.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1793 105 0.19% 98.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1857 71 0.13% 98.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1921 56 0.10% 98.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1985 36 0.06% 98.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2049 46 0.08% 98.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2113 27 0.05% 98.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2177 25 0.04% 99.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2241 21 0.04% 99.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2305 22 0.04% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2369 17 0.03% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2433 12 0.02% 99.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2497 14 0.03% 99.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2561 11 0.02% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2625 12 0.02% 99.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2689 9 0.02% 99.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2753 11 0.02% 99.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2817 10 0.02% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2881 4 0.01% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3009 8 0.01% 99.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3073 7 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3137 3 0.01% 99.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3201 5 0.01% 99.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 56237 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 279.600690 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.370876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 689.275557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-65 28174 50.10% 50.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-129 10389 18.47% 68.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-193 4755 8.46% 77.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-257 2751 4.89% 81.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-321 1840 3.27% 85.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-385 1148 2.04% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-449 864 1.54% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-513 636 1.13% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-577 440 0.78% 90.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-641 367 0.65% 91.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-705 311 0.55% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-769 257 0.46% 92.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-833 204 0.36% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-897 168 0.30% 93.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-961 168 0.30% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1025 154 0.27% 93.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1089 142 0.25% 93.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1153 160 0.28% 94.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1217 179 0.32% 94.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1281 140 0.25% 94.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1345 187 0.33% 95.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1409 266 0.47% 95.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1473 973 1.73% 97.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1537 245 0.44% 97.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1601 154 0.27% 97.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1665 175 0.31% 98.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1729 98 0.17% 98.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1793 108 0.19% 98.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1857 57 0.10% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1921 69 0.12% 98.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1985 37 0.07% 98.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2049 38 0.07% 98.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2113 29 0.05% 99.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2177 23 0.04% 99.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2241 13 0.02% 99.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2305 16 0.03% 99.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2369 14 0.02% 99.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2433 7 0.01% 99.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2497 15 0.03% 99.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2561 12 0.02% 99.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2625 9 0.02% 99.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2689 15 0.03% 99.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2753 6 0.01% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2817 12 0.02% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2881 9 0.02% 99.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2945 5 0.01% 99.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3009 5 0.01% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3073 1 0.00% 99.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3137 6 0.01% 99.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3201 8 0.01% 99.33% # Bytes accessed per row activation system.physmem.bytesPerActivate::3264-3265 3 0.01% 99.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3329 7 0.01% 99.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3329 3 0.01% 99.34% # Bytes accessed per row activation system.physmem.bytesPerActivate::3392-3393 4 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3457 3 0.01% 99.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3521 2 0.00% 99.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3585 9 0.02% 99.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3649 6 0.01% 99.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3713 4 0.01% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3777 1 0.00% 99.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3905 2 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3969 1 0.00% 99.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4033 4 0.01% 99.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4097 3 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3457 4 0.01% 99.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3521 8 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3585 3 0.01% 99.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3649 3 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3713 3 0.01% 99.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3777 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3841 2 0.00% 99.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3905 3 0.01% 99.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3969 7 0.01% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4033 2 0.00% 99.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4097 1 0.00% 99.41% # Bytes accessed per row activation system.physmem.bytesPerActivate::4160-4161 2 0.00% 99.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::4224-4225 1 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4289 2 0.00% 99.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4353 3 0.01% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4481 2 0.00% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4545 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4609 2 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4417 2 0.00% 99.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4481 4 0.01% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4545 2 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4609 1 0.00% 99.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4673 1 0.00% 99.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::4736-4737 1 0.00% 99.44% # Bytes accessed per row activation system.physmem.bytesPerActivate::4800-4801 1 0.00% 99.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4929 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5057 4 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4865 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4993 1 0.00% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5057 3 0.01% 99.45% # Bytes accessed per row activation system.physmem.bytesPerActivate::5120-5121 4 0.01% 99.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5185 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5249 1 0.00% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5441 3 0.01% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5569 2 0.00% 99.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5697 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5761 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5953 3 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6145 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5185 5 0.01% 99.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5313 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5377 2 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5697 2 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6017 2 0.00% 99.49% # Bytes accessed per row activation system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6273 2 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6785 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7169 2 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6401 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6529 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6785 2 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6913 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7361 2 0.00% 99.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7617 2 0.00% 99.52% # Bytes accessed per row activation system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.53% # Bytes accessed per row activation system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7809 2 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7873 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7937 1 0.00% 99.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8001 2 0.00% 99.54% # Bytes accessed per row activation system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8193 256 0.46% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 55927 # Bytes accessed per row activation -system.physmem.totQLat 1510568250 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 4629837000 # Sum of mem lat for all requests -system.physmem.totBusLat 740065000 # Total cycles spent in databus access -system.physmem.totBankLat 2379203750 # Total cycles spent in bank access -system.physmem.avgQLat 10205.65 # Average queueing delay per request -system.physmem.avgBankLat 16074.29 # Average bank access latency per request +system.physmem.bytesPerActivate::8192-8193 257 0.46% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 56237 # Bytes accessed per row activation +system.physmem.totQLat 1508178750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 4631350000 # Sum of mem lat for all requests +system.physmem.totBusLat 740420000 # Total cycles spent in databus access +system.physmem.totBankLat 2382751250 # Total cycles spent in bank access +system.physmem.avgQLat 10184.62 # Average queueing delay per request +system.physmem.avgBankLat 16090.54 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31279.93 # Average memory access latency -system.physmem.avgRdBW 46.85 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 30.88 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 46.85 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 30.88 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 31275.15 # Average memory access latency +system.physmem.avgRdBW 46.88 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 30.89 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 46.88 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 30.89 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 0.61 # Data bus utilization in percentage system.physmem.avgRdQLen 0.02 # Average read queue length over time -system.physmem.avgWrQLen 8.55 # Average write queue length over time -system.physmem.readRowHits 130620 # Number of row buffer hits during reads -system.physmem.writeRowHits 59055 # Number of row buffer hits during writes -system.physmem.readRowHitRate 88.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.51 # Row buffer hit rate for writes -system.physmem.avgGap 823311.91 # Average gap between requests -system.membus.throughput 77734493 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 46795 # Transaction distribution -system.membus.trans_dist::ReadResp 46794 # Transaction distribution -system.membus.trans_dist::Writeback 97594 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9 # Transaction distribution -system.membus.trans_dist::UpgradeResp 9 # Transaction distribution -system.membus.trans_dist::ReadExReq 101283 # Transaction distribution -system.membus.trans_dist::ReadExResp 101283 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side 393767 # Packet count per connected master and slave (bytes) -system.membus.pkt_count 393767 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15722944 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size 15722944 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 15722944 # Total data (bytes) +system.physmem.avgWrQLen 8.03 # Average write queue length over time +system.physmem.readRowHits 130565 # Number of row buffer hits during reads +system.physmem.writeRowHits 58894 # Number of row buffer hits during writes +system.physmem.readRowHitRate 88.17 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.33 # Row buffer hit rate for writes +system.physmem.avgGap 822893.14 # Average gap between requests +system.membus.throughput 77774052 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 46889 # Transaction distribution +system.membus.trans_dist::ReadResp 46888 # Transaction distribution +system.membus.trans_dist::Writeback 97619 # Transaction distribution +system.membus.trans_dist::UpgradeReq 10 # Transaction distribution +system.membus.trans_dist::UpgradeResp 10 # Transaction distribution +system.membus.trans_dist::ReadExReq 101277 # Transaction distribution +system.membus.trans_dist::ReadExResp 101277 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side 393970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count 393970 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 15730176 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size 15730176 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 15730176 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1079125750 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1080021750 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1399666492 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1400430490 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.7 # Layer utilization (%) -system.cpu.branchPred.lookups 182795351 # Number of BP lookups -system.cpu.branchPred.condPredicted 143107535 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7264975 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 93466227 # Number of BTB lookups -system.cpu.branchPred.BTBHits 87209092 # Number of BTB hits +system.cpu.branchPred.lookups 182798066 # Number of BP lookups +system.cpu.branchPred.condPredicted 143118312 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7265128 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 93487974 # Number of BTB lookups +system.cpu.branchPred.BTBHits 87210419 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.305459 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12678830 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 116057 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.285174 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12673306 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 115887 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -359,99 +360,99 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 404529406 # number of cpu cycles simulated +system.cpu.numCycles 404509620 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 119370904 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 761561247 # Number of instructions fetch has processed -system.cpu.fetch.Branches 182795351 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 99887922 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 170134463 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 35678521 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 77150212 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 98 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 455 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 48 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 114522843 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2439505 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 394266586 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.166435 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.987414 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 119370691 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 761605740 # Number of instructions fetch has processed +system.cpu.fetch.Branches 182798066 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 99883725 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 170135363 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 35678308 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 77091190 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 33 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 441 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 114522071 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2438323 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 394207776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.166768 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.987550 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 224144737 56.85% 56.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 14179887 3.60% 60.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22893161 5.81% 66.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 22745024 5.77% 72.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 20894474 5.30% 77.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 11598135 2.94% 80.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 13057002 3.31% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 11992402 3.04% 86.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 52761764 13.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 224085033 56.84% 56.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 14184034 3.60% 60.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22893795 5.81% 66.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 22742785 5.77% 72.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 20889438 5.30% 77.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 11596058 2.94% 80.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 13058827 3.31% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 11996655 3.04% 86.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 52761151 13.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 394266586 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.451872 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.882586 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 129061208 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 72641827 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 158799298 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6227893 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 27536360 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 26125699 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 76608 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 825532349 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 291942 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 27536360 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 135656827 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10155018 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 47441534 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 158249633 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 15227214 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 800580004 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1401 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 3056484 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 8970861 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 208 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 954230970 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3500428728 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3500427418 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1310 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 394207776 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.451900 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.882788 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 129058894 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 72583383 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 158800998 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6228602 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 27535899 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 26119356 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 76952 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 825527591 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 297029 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 27535899 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 135653385 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10117573 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 47448086 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 158253744 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 15199089 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 800585743 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1337 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 3048778 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 8951135 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 327 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 954274745 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3500443085 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3500441750 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1335 # Number of floating rename lookups system.cpu.rename.CommittedMaps 666252291 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 287978679 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2292969 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2292967 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 41852604 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 170255884 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 73472812 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 28582851 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15746500 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 755022174 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 3775311 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 665301102 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1380692 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 187339157 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 479760666 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 797679 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 394266586 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.687440 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.735091 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 288022454 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2292887 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2292884 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 41810314 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 170245714 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 73473402 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 28600787 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 15864837 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 755023538 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 3775253 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 665282495 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1376367 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 187359932 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 479861351 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 797621 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 394207776 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.687644 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.734895 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 138747020 35.19% 35.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 69982581 17.75% 52.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 71470863 18.13% 71.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 53423224 13.55% 84.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 31142023 7.90% 92.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 16022250 4.06% 96.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8747194 2.22% 98.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 2906831 0.74% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1824600 0.46% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 138685304 35.18% 35.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 69974148 17.75% 52.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 71487489 18.13% 71.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 53410155 13.55% 84.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 31169458 7.91% 92.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 15996787 4.06% 96.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8767931 2.22% 98.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 2898481 0.74% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1818023 0.46% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 394266586 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 394207776 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 480987 5.01% 5.01% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 480591 5.01% 5.01% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.01% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 5.01% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.01% # attempts to use FU when none available @@ -480,15 +481,15 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.01% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.01% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.01% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.01% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 6546208 68.16% 73.16% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 2577471 26.84% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 6540572 68.21% 73.22% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 2567937 26.78% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 447771708 67.30% 67.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 383310 0.06% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 447761903 67.30% 67.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 383485 0.06% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 90 0.00% 67.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 94 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.36% # Type of FU issued @@ -514,84 +515,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.36% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.36% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 153352638 23.05% 90.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 63793353 9.59% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 153367544 23.05% 90.41% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 63769466 9.59% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 665301102 # Type of FU issued -system.cpu.iq.rate 1.644630 # Inst issue rate -system.cpu.iq.fu_busy_cnt 9604666 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014437 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1735853933 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 946943275 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 646028886 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 215 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 665282495 # Type of FU issued +system.cpu.iq.rate 1.644664 # Inst issue rate +system.cpu.iq.fu_busy_cnt 9589100 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014414 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1735738010 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 946965616 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 646015342 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 223 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 298 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 674905659 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 8552862 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 674871482 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 113 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 8586210 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 44226329 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 41059 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 810522 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 16612335 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 44216159 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 41012 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 810921 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 16612925 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19495 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7104 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19492 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6939 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 27536360 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5290664 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 387489 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 760356154 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 1118953 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 170255884 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 73472812 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2286769 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 219863 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 12400 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 810522 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 4337912 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4002750 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8340662 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 655875003 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 150077564 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 9426099 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 27535899 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5281663 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 386285 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 760357745 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 1115007 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 170245714 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 73473402 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2286711 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 219038 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12304 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 810921 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 4337552 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4003513 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8341065 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 655860831 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 150086003 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 9421664 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1558669 # number of nop insts executed -system.cpu.iew.exec_refs 212570616 # number of memory reference insts executed -system.cpu.iew.exec_branches 138493352 # Number of branches executed -system.cpu.iew.exec_stores 62493052 # Number of stores executed -system.cpu.iew.exec_rate 1.621328 # Inst execution rate -system.cpu.iew.wb_sent 650999754 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 646028902 # cumulative count of insts written-back -system.cpu.iew.wb_producers 374692861 # num instructions producing a value -system.cpu.iew.wb_consumers 646290036 # num instructions consuming a value +system.cpu.iew.exec_nop 1558954 # number of nop insts executed +system.cpu.iew.exec_refs 212560295 # number of memory reference insts executed +system.cpu.iew.exec_branches 138490949 # Number of branches executed +system.cpu.iew.exec_stores 62474292 # Number of stores executed +system.cpu.iew.exec_rate 1.621373 # Inst execution rate +system.cpu.iew.wb_sent 650984327 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 646015358 # cumulative count of insts written-back +system.cpu.iew.wb_producers 374693412 # num instructions producing a value +system.cpu.iew.wb_consumers 646299598 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.596989 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.579760 # average fanout of values written-back +system.cpu.iew.wb_rate 1.597033 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.579752 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 189414626 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 189415917 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 7190929 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 366730226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.556916 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.230567 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 7190999 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 366671877 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.557164 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.230606 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 159030510 43.36% 43.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 98471088 26.85% 70.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 33850160 9.23% 79.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 18801710 5.13% 84.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 16194042 4.42% 88.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 7449344 2.03% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 6951093 1.90% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 3196049 0.87% 93.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22786230 6.21% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 158948889 43.35% 43.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 98517703 26.87% 70.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 33831327 9.23% 79.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 18775088 5.12% 84.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 16222583 4.42% 88.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7456199 2.03% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 6938304 1.89% 92.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 3192877 0.87% 93.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22788907 6.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 366730226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 366671877 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 570968167 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -602,225 +603,221 @@ system.cpu.commit.branches 121548301 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 470727693 # Number of committed integer instructions. system.cpu.commit.function_calls 9757362 # Number of function calls committed. -system.cpu.commit.bw_lim_events 22786230 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22788907 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1104319651 # The number of ROB reads -system.cpu.rob.rob_writes 1548423446 # The number of ROB writes -system.cpu.timesIdled 327931 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10262820 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1104259916 # The number of ROB reads +system.cpu.rob.rob_writes 1548425259 # The number of ROB writes +system.cpu.timesIdled 328032 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10301844 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 569624283 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 505237723 # Number of Instructions Simulated -system.cpu.cpi 0.800671 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.800671 # CPI: Total CPI of All Threads -system.cpu.ipc 1.248952 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.248952 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3058568749 # number of integer regfile reads -system.cpu.int_regfile_writes 751946172 # number of integer regfile writes +system.cpu.cpi 0.800632 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.800632 # CPI: Total CPI of All Threads +system.cpu.ipc 1.249013 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.249013 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3058504664 # number of integer regfile reads +system.cpu.int_regfile_writes 751970917 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 210826056 # number of misc regfile reads +system.cpu.misc_regfile_reads 210811449 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.toL2Bus.throughput 735267470 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 864400 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 864399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1110556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 92 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 92 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 348774 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 348774 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33891 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503090 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count 3536981 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1081088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147630784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size 148711872 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148711872 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 6784 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2272470744 # Layer occupancy (ticks) +system.cpu.toL2Bus.throughput 735317990 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 864350 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 864349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1110574 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 73 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 348852 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 348852 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 33690 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 3503354 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count 3537044 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1075520 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 147641024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.tot_pkt_size 148716544 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.data_through_bus 148716544 # Total data (bytes) +system.cpu.toL2Bus.snoop_data_through_bus 5056 # Total snoop data (bytes) +system.cpu.toL2Bus.reqLayer0.occupancy 2272504241 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 25507479 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 25334982 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1794320975 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1794529465 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.cpu.icache.replacements 15058 # number of replacements -system.cpu.icache.tagsinuse 1102.051233 # Cycle average of tags in use -system.cpu.icache.total_refs 114501571 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 16910 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6771.234240 # Average number of references to valid blocks. +system.cpu.icache.replacements 14954 # number of replacements +system.cpu.icache.tagsinuse 1101.424981 # Cycle average of tags in use +system.cpu.icache.total_refs 114501007 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 16812 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6810.671366 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 1102.051233 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.538111 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.538111 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 114501582 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 114501582 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 114501582 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 114501582 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 114501582 # number of overall hits -system.cpu.icache.overall_hits::total 114501582 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 21259 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 21259 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 21259 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 21259 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 21259 # number of overall misses -system.cpu.icache.overall_misses::total 21259 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 595415500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 595415500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 595415500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 595415500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 595415500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 595415500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 114522841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 114522841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 114522841 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 114522841 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 114522841 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 114522841 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000186 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000186 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000186 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000186 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000186 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28007.690860 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28007.690860 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28007.690860 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28007.690860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28007.690860 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28007.690860 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2365 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 1101.424981 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.537805 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.537805 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 114501007 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 114501007 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 114501007 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 114501007 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 114501007 # number of overall hits +system.cpu.icache.overall_hits::total 114501007 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 21063 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 21063 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 21063 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 21063 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 21063 # number of overall misses +system.cpu.icache.overall_misses::total 21063 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 592520500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 592520500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 592520500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 592520500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 592520500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 592520500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 114522070 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 114522070 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 114522070 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 114522070 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 114522070 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 114522070 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000184 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000184 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000184 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000184 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000184 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28130.869297 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28130.869297 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28130.869297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28130.869297 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28130.869297 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 770 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 12 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 181.923077 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 64.166667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4260 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4260 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4260 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4260 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4260 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4260 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16999 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 16999 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 16999 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 16999 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 16999 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 16999 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 426747521 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 426747521 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 426747521 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 426747521 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 426747521 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 426747521 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000148 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000148 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000148 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25104.272075 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25104.272075 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25104.272075 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25104.272075 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25104.272075 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25104.272075 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4178 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4178 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4178 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4178 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4178 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4178 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16885 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 16885 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 16885 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 16885 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 16885 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 16885 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 427572518 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 427572518 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 427572518 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 427572518 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 427572518 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 427572518 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000147 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000147 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000147 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000147 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25322.624696 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25322.624696 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25322.624696 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 25322.624696 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25322.624696 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 25322.624696 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 115327 # number of replacements -system.cpu.l2cache.tagsinuse 27103.990610 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1780423 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 146587 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 12.145845 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 89762160000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 23023.222015 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 362.369972 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 3718.398623 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.702613 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.011059 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.113477 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.827148 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 13513 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 803960 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 817473 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1110556 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1110556 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 83 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 83 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 247491 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 247491 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 13513 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1051451 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1064964 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 13513 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1051451 # number of overall hits -system.cpu.l2cache.overall_hits::total 1064964 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3380 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 43441 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 46821 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101283 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101283 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3380 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 144724 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 148104 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3380 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 144724 # number of overall misses -system.cpu.l2cache.overall_misses::total 148104 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 274234000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3645115500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3919349500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 22500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7042551500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7042551500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 274234000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10687667000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10961901000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 274234000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10687667000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10961901000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 16893 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 847401 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 864294 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1110556 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1110556 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 92 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 348774 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 348774 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 16893 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1196175 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1213068 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 16893 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1196175 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1213068 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.200083 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051264 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.054173 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.097826 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.097826 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290397 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.290397 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.200083 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.120989 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.122090 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200083 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.120989 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.122090 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81134.319527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83909.566999 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83709.222357 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 2500 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 2500 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69533.401459 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69533.401459 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81134.319527 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73848.615295 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74014.888187 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81134.319527 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73848.615295 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74014.888187 # average overall miss latency +system.cpu.l2cache.replacements 115420 # number of replacements +system.cpu.l2cache.tagsinuse 27103.497670 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1780537 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 146672 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 12.139584 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 102160649500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 23017.556020 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 361.817862 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 3724.123788 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.702440 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.inst 0.011042 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.113651 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.827133 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 13425 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 803929 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 817354 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1110574 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1110574 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 63 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 63 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 247575 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 247575 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 13425 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1051504 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1064929 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 13425 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1051504 # number of overall hits +system.cpu.l2cache.overall_hits::total 1064929 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3381 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 43536 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 46917 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 101277 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 101277 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3381 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 144813 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 148194 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3381 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 144813 # number of overall misses +system.cpu.l2cache.overall_misses::total 148194 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 276063000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3642504500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3918567500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7048588500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7048588500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 276063000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10691093000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10967156000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 276063000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10691093000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10967156000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 16806 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 847465 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 864271 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1110574 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1110574 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 73 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 73 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 348852 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 348852 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 16806 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1196317 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1213123 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 16806 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1196317 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1213123 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.201178 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.051372 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.054285 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.136986 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.136986 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.290315 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.290315 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.201178 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.121049 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.122159 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.201178 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.121049 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.122159 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81651.286602 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83666.494395 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83521.271607 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69597.129654 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69597.129654 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81651.286602 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73826.887089 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74005.398329 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81651.286602 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73826.887089 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74005.398329 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -829,195 +826,195 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97594 # number of writebacks -system.cpu.l2cache.writebacks::total 97594 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 97619 # number of writebacks +system.cpu.l2cache.writebacks::total 97619 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 26 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 24 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 26 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 24 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 22 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 26 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3376 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43419 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 46795 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101283 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 101283 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3376 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144702 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 148078 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3376 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144702 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 148078 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 231774000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3104828000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3336602000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 94508 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 94508 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5779215000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5779215000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 231774000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8884043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9115817000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 231774000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8884043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9115817000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051238 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054142 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.097826 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.097826 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290397 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290397 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.122069 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.199846 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.120971 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.122069 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68653.436019 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71508.510099 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71302.532322 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10500.888889 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10500.888889 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57060.069311 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57060.069311 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68653.436019 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61395.440284 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61560.913843 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68653.436019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61395.440284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61560.913843 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 24 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 28 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3377 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 43512 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 46889 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 101277 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 101277 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3377 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 144789 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 148166 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3377 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 144789 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 148166 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 233867750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3101136000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3335003750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 100010 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 100010 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5785341250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5785341250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 233867750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8886477250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9120345000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 233867750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8886477250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9120345000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.054253 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.136986 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.136986 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.290315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.290315 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.121029 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.122136 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200940 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.121029 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.122136 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69253.109269 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71270.821842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71125.503850 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57123.939789 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57123.939789 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69253.109269 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61375.361733 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61554.911383 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69253.109269 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61375.361733 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61554.911383 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1192079 # number of replacements -system.cpu.dcache.tagsinuse 4057.787384 # Cycle average of tags in use -system.cpu.dcache.total_refs 190170418 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1196175 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 158.982104 # Average number of references to valid blocks. +system.cpu.dcache.replacements 1192221 # number of replacements +system.cpu.dcache.tagsinuse 4057.785515 # Cycle average of tags in use +system.cpu.dcache.total_refs 190145872 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1196317 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 158.942715 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 4220492000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 4057.787384 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.990671 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.990671 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 136204469 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 136204469 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 50988281 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 50988281 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488831 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488831 # number of LoadLockedReq hits +system.cpu.dcache.occ_blocks::cpu.data 4057.785515 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.990670 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 136179358 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 136179358 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 50988931 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 50988931 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488837 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488837 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 187192750 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 187192750 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 187192750 # number of overall hits -system.cpu.dcache.overall_hits::total 187192750 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1701442 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1701442 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3251025 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3251025 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 38 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 38 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4952467 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4952467 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4952467 # number of overall misses -system.cpu.dcache.overall_misses::total 4952467 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29643398500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29643398500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 68982804444 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 68982804444 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 639500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 639500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 98626202944 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 98626202944 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 98626202944 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 98626202944 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 137905911 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 137905911 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 187168289 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 187168289 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 187168289 # number of overall hits +system.cpu.dcache.overall_hits::total 187168289 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1699578 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1699578 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3250375 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3250375 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 37 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 37 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 4949953 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4949953 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4949953 # number of overall misses +system.cpu.dcache.overall_misses::total 4949953 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29584540500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29584540500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 69108485945 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 69108485945 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 701500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 701500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 98693026445 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 98693026445 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 98693026445 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 98693026445 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 137878936 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 137878936 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488869 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488869 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488874 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488874 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 192145217 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 192145217 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 192145217 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 192145217 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012338 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012338 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059939 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.059939 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000026 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000026 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025775 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025775 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.025775 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.025775 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17422.514843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17422.514843 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21218.786212 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 21218.786212 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16828.947368 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16828.947368 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19914.560348 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19914.560348 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19914.560348 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 17857 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 40598 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1694 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 662 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 10.541322 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61.326284 # average number of cycles each access was blocked +system.cpu.dcache.demand_accesses::cpu.data 192118242 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 192118242 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 192118242 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 192118242 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012327 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012327 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.059927 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.059927 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000025 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025765 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025765 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.025765 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.025765 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17406.991912 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17406.991912 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21261.696249 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 21261.696249 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 18959.459459 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 18959.459459 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19938.174452 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19938.174452 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19938.174452 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 19233 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 40481 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1722 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 665 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 11.168990 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 60.873684 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1110556 # number of writebacks -system.cpu.dcache.writebacks::total 1110556 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 853509 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 853509 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902691 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2902691 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 38 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 38 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3756200 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3756200 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3756200 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3756200 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 847933 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 847933 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348334 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 348334 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1196267 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1196267 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1196267 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1196267 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12570935024 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12570935024 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9915738995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9915738995 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22486674019 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 22486674019 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22486674019 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 22486674019 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006226 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006226 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006226 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14825.387176 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14825.387176 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28466.181869 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28466.181869 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18797.370503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18797.370503 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1110574 # number of writebacks +system.cpu.dcache.writebacks::total 1110574 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 851549 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 851549 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2902014 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2902014 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 37 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3753563 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3753563 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3753563 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3753563 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 848029 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 848029 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 348361 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 348361 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1196390 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1196390 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1196390 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1196390 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12568519034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12568519034 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9922118995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 9922118995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22490638029 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22490638029 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22490638029 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22490638029 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006151 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006423 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006227 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006227 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006227 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14820.859940 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14820.859940 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28482.289909 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28482.289909 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18798.751268 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18798.751268 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |